coreboot-gerrit January 2019

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Lijian Zhao (Code Review) 29 Jan '19

29 Jan '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 1: Can we totally drop SOC_CANNONLAKE to make it easier? Consider zoombini/meowth already removed from coreboot tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 07:13:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by Patrick Rudolph (Code Review) 29 Jan '19

29 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Patch Set 9: Why are both CxDRT1 registers programmed with the same value ? Wouldn't that break if one channel has 8banks DIMMs, but the other 16banks DIMMs? What does the datasheet say? Does both channels need to be kept in sync ? -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 07:00:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Furquan Shaikh (Code Review) 29 Jan '19

29 Jan '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31133/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31133/1//COMMIT_MSG@7 PS1, Line 7: Add SOC_INTEL_WHISKEYLAKE kconfig : Does it really help? It seems to be adding another config but is used always with SOC_INTEL_COFFEELAKE. Should we wait until there is a need to split? -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 06:54:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Make SOC_INTEL_CANNONLAKE_MEMCFG_INIT common fo...
by Furquan Shaikh (Code Review) 29 Jan '19

29 Jan '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31134 ) Change subject: soc/intel/cannonlake: Make SOC_INTEL_CANNONLAKE_MEMCFG_INIT common for CFL/WHL SoC ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31134/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31134/1//COMMIT_MSG@7 PS1, Line 7: SOC_INTEL_CANNONLAKE_MEMCFG_INIT Why not just get rid of this config completely as it is always selected? You will have to update cannonlake_rvp to use the same callback as used by CFL/WHL boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/31134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Gerrit-Change-Number: 31134 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 06:53:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Ronak Kanabar (Code Review) 29 Jan '19

29 Jan '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 3: > Patch Set 2: > > in my mind, all Sagv value should be just enable because in MRC code SaGv enable handles both high and low freq training. so we shouldn't be bothered. > > I don't know what makes to select Fixed High or low specifically, unless its been early silicon. I think at this point we can change Its value to SaGv Enable. but doing it into this patch will not justify this patch objective. so pushed CB:31132 patch to enable SaGv in CNL-Y and CNL-U -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 05:46:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Ronak Kanabar (Code Review) 29 Jan '19

29 Jan '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 3: > Patch Set 2: > > in my mind, all Sagv value should be just enable because in MRC code SaGv enable handles both high and low freq training. so we shouldn't be bothered. > > I don't know what makes to select Fixed High or low specifically, unless its been early silicon. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 05:41:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Subrata Banik (Code Review) 29 Jan '19

29 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 2: in my mind, all Sagv value should be just enable because in MRC code SaGv enable handles both high and low freq training. so we shouldn't be bothered. I don't know what makes to select Fixed High or low specifically, unless its been early silicon. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 04:31:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp/../icl_y: Enable SaGv
by Subrata Banik (Code Review) 29 Jan '19

29 Jan '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31119 Change subject: mb/intel/icelake_rvp/../icl_y: Enable SaGv ...................................................................... mb/intel/icelake_rvp/../icl_y: Enable SaGv This patch enables SaGv on Intel ICL-Y RVP board. TEST=Able to build and boot to Chrome OS. Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31119/1 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 0972c29..4f41308 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -13,7 +13,7 @@ register "gpe0_dw2" = "GPP_E" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/31119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Gerrit-Change-Number: 31119 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Remove unnecessary USB charging ASL entries
by Subrata Banik (Code Review) 29 Jan '19

29 Jan '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31117 Change subject: soc/intel/icelake: Remove unnecessary USB charging ASL entries ...................................................................... soc/intel/icelake: Remove unnecessary USB charging ASL entries This patch removes stale ASL entries added in past due to chromeos requirement. BUG=115755982 Change-Id: I18b57822ce3198fb96aae977f0b552ff2d4a14ee --- M src/soc/intel/icelake/acpi/globalnvs.asl 1 file changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31117/1 diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/icelake/acpi/globalnvs.asl index b8f4d2f..678ce5a 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/icelake/acpi/globalnvs.asl @@ -48,34 +48,8 @@ U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume - S5U0, 8, // 0x30 - Enable USB in S5 - S3U0, 8, // 0x31 - Enable USB in S3 /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> } - -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) -} - -/* Set flag to enable USB charging in S5 */ -Method (S5UE) -{ - Store (One, \S5U0) -} - -/* Set flag to disable USB charging in S5 */ -Method (S5UD) -{ - Store (Zero, \S5U0) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18b57822ce3198fb96aae977f0b552ff2d4a14ee Gerrit-Change-Number: 31117 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/docker/doc.coreboot.org/Dockerfile: Update to Sphinx 1.8
by Tom Hiller (Code Review) 29 Jan '19

29 Jan '19

Tom Hiller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30616 Change subject: util/docker/doc.coreboot.org/Dockerfile: Update to Sphinx 1.8 ...................................................................... util/docker/doc.coreboot.org/Dockerfile: Update to Sphinx 1.8 Correct sphinx generate error. Change-Id: I5a7d8148a60a5b2e938ccddc2b1ee370ba8941aa Signed-off-by: Tom Hiller <thrilleratplay(a)gmail.com> --- M util/docker/doc.coreboot.org/Dockerfile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30616/1 diff --git a/util/docker/doc.coreboot.org/Dockerfile b/util/docker/doc.coreboot.org/Dockerfile index 8de0d46..f30c4db 100644 --- a/util/docker/doc.coreboot.org/Dockerfile +++ b/util/docker/doc.coreboot.org/Dockerfile @@ -5,7 +5,7 @@ RUN apk add --no-cache python3 make bash git \ && pip3 install --upgrade --no-cache-dir pip \ && pip3 install --no-cache-dir \ - sphinx===1.7.7 \ + sphinx===1.8.3 \ sphinx_rtd_theme===0.4.1 \ recommonmark===0.4.0 \ sphinx_autobuild===0.7.1 \ -- To view, visit https://review.coreboot.org/c/coreboot/+/30616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a7d8148a60a5b2e938ccddc2b1ee370ba8941aa Gerrit-Change-Number: 30616 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019