coreboot-gerrit January 2019

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Change in ...coreboot[master]: util/ifdtools: Consider EC region access
by Lijian Zhao (Code Review) 29 Jan '19

29 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31111 Change subject: util/ifdtools: Consider EC region access ...................................................................... util/ifdtools: Consider EC region access Version 2 IFD will have flmstr5 as EC region access control, consider it during descriptor lock/unlock process. BUG=N/A TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check flmstr5 value by hexdump the SPI image at offset FMBA+0x90. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8 --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31111/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 1181e8c..85623fd 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -943,6 +943,7 @@ fmba->flmstr1 &= 0xff; fmba->flmstr2 &= 0xff; fmba->flmstr3 &= 0xff; + fmba->flmstr5 &= 0xff; } else { wr_shift = FLMSTR_WR_SHIFT_V1; rd_shift = FLMSTR_RD_SHIFT_V1; @@ -1015,6 +1016,7 @@ fmba->flmstr1 = 0xffffff00 | (fmba->flmstr1 & 0xff); fmba->flmstr2 = 0xffffff00 | (fmba->flmstr2 & 0xff); fmba->flmstr3 = 0xffffff00 | (fmba->flmstr3 & 0xff); + fmba->flmstr5 = 0xffffff00 | (fmba->flmstr5 & 0xff); } else { fmba->flmstr1 = 0xffff0000; fmba->flmstr2 = 0xffff0000; -- To view, visit https://review.coreboot.org/c/coreboot/+/31111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8 Gerrit-Change-Number: 31111 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/ifdtool: Add lock support for cnl and icl
by Lijian Zhao (Code Review) 29 Jan '19

29 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31104 Change subject: util/ifdtool: Add lock support for cnl and icl ...................................................................... util/ifdtool: Add lock support for cnl and icl Cannonlake and Icelake have same read/write region permission settings with skylake and kabylake, so add it here as well. BUG=b:123199222 TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the setting matches 0x0D for read and 0x04 for write. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2 --- M util/ifdtool/ifdtool.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31104/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 69cd2a9..1181e8c 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -965,6 +965,8 @@ /* TXE can only write Device Expansion */ fmba->flmstr2 |= 0x20 << wr_shift; break; + case PLATFORM_CNL: + case PLATFORM_ICL: case PLATFORM_SKLKBL: /* CPU/BIOS can read descriptor, BIOS and GbE. */ fmba->flmstr1 |= 0xb << rd_shift; -- To view, visit https://review.coreboot.org/c/coreboot/+/31104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2 Gerrit-Change-Number: 31104 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/z61t/Kconfig: Select I945_LVDS
by Peter Lemenkov (Code Review) 29 Jan '19

29 Jan '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31115 Change subject: mb/lenovo/z61t/Kconfig: Select I945_LVDS ...................................................................... mb/lenovo/z61t/Kconfig: Select I945_LVDS This board has almost the same schematics as [xt]60 so this should work. See also commit 7971582e with Change-Id Iff6dac5a5f61af49456bc6312e7a376def02ab00. Change-Id: I8dc9b122eb64b5c1dcd0dbc99ac41aa0f8dd9766 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/z61t/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31115/1 diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig index bfa5c26..9aa6350 100644 --- a/src/mainboard/lenovo/z61t/Kconfig +++ b/src/mainboard/lenovo/z61t/Kconfig @@ -20,9 +20,9 @@ select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select MAINBOARD_HAS_NATIVE_VGA_INIT select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT + select I945_LVDS select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR -- To view, visit https://review.coreboot.org/c/coreboot/+/31115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dc9b122eb64b5c1dcd0dbc99ac41aa0f8dd9766 Gerrit-Change-Number: 31115 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by You-Cheng Syu (Code Review) 29 Jan '19

29 Jan '19

You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/#/c/30331/12//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30331/12//COMMIT_MSG@7 PS12, Line 7: google/kukui: Move some initialization from bootblock to verstage. > Please remove the dot/period at the end of the commit message summary. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 13 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 29 Jan 2019 12:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage
by You-Cheng Syu (Code Review) 29 Jan '19

29 Jan '19

Hello Julius Werner, Paul Menzel, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Chun-ta Lin, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30331 to look at the new patch set (#13). Change subject: google/kukui: Move some initialization from bootblock to verstage ...................................................................... google/kukui: Move some initialization from bootblock to verstage MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c A src/mainboard/google/kukui/early_init.c A src/mainboard/google/kukui/early_init.h M src/mainboard/google/kukui/romstage.c M src/mainboard/google/kukui/verstage.c M src/soc/mediatek/mt8183/Makefile.inc 7 files changed, 72 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30331/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 13 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Subrata Banik (Code Review) 29 Jan '19

29 Jan '19

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Change in ...coreboot[master]: soc/intel/cannonlake: Make SOC_INTEL_CANNONLAKE_MEMCFG_INIT common fo...
by Subrata Banik (Code Review) 29 Jan '19

29 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31134 ) Change subject: soc/intel/cannonlake: Make SOC_INTEL_CANNONLAKE_MEMCFG_INIT common for CFL/WHL SoC ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31134/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31134/1//COMMIT_MSG@7 PS1, Line 7: SOC_INTEL_CANNONLAKE_MEMCFG_INIT > Why not just get rid of this config completely as it is always selected? You will have to update can […] i don't think we are even using cnlrvp today hence didn't bother to make changes on something that not in use. -- To view, visit https://review.coreboot.org/c/coreboot/+/31134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Gerrit-Change-Number: 31134 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 07:43:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Subrata Banik (Code Review) 29 Jan '19

29 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/31133/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31133/1//COMMIT_MSG@7 PS1, Line 7: Add SOC_INTEL_WHISKEYLAKE kconfig : > Does it really help? It seems to be adding another config but is used always with SOC_INTEL_COFFEELA […] there is some confusion by seeing board support. CFL and WHL are different SOC from Intel side, in coreboot context both might look similar because its almost common code. But you can't ignore the fact that neither WHLRVP will boot with CFL SoC nor hatch board can have CFL SOC. adding WHL config might not add any value bt it will be clear from user level to know soc details along with board https://review.coreboot.org/#/c/31133/1//COMMIT_MSG@7 PS1, Line 7: Add SOC_INTEL_WHISKEYLAKE kconfig : > Same question here, we have separated WHL FSP already? With CML release, we might have some common FSP between WHL and CML. This patch is not to tell where FSP exist. as i said this to make notion clear about board. CFL != WHL in reality then why to select the same for all board ? -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 07:41:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lijian Zhao <lijian.zhao(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Lijian Zhao (Code Review) 29 Jan '19

29 Jan '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31133/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31133/1//COMMIT_MSG@7 PS1, Line 7: Add SOC_INTEL_WHISKEYLAKE kconfig : > Does it really help? It seems to be adding another config but is used always with SOC_INTEL_COFFEELA […] Same question here, we have separated WHL FSP already? -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 07:27:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Lijian Zhao (Code Review) 29 Jan '19

29 Jan '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 1: > Can we totally drop SOC_CANNONLAKE to make it easier? Consider > zoombini/meowth already removed from coreboot tree. I take it back, rdc still have regular update. Maybe somebody still use it. -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 07:18:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019