coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/amd/stoneyridge: Access SMBUS through MMIO
by Martin Roth (Code Review) 29 Jan '19

29 Jan '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29258 ) Change subject: soc/amd/stoneyridge: Access SMBUS through MMIO ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Gerrit-Change-Number: 29258 Gerrit-PatchSet: 12 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 16:58:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Pratikkumar V Prajapati (Code Review) 29 Jan '19

29 Jan '19

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 16:14:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Pratikkumar V Prajapati (Code Review) 29 Jan '19

29 Jan '19

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 3: > Patch Set 2: > > (1 comment) When i pushed the patch at that time value '3' was associated with 'Enabled'. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 16:13:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/stoneyridge: Access SMBUS through MMIO
by Richard Spiegel (Code Review) 29 Jan '19

29 Jan '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29258 ) Change subject: soc/amd/stoneyridge: Access SMBUS through MMIO ...................................................................... Patch Set 12: (3 comments) https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… File src/soc/amd/stoneyridge/include/soc/iomap.h: https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… PS12, Line 42: 0xfed80a00 > Not sure if there's actually an extra space here or if it's a gerrit artifact. […] gerrit artifact. https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/include/so… PS12, Line 116: /* SMBUS MMIO offsets 0xfed80a00 */ > Why did these get moved out of smbus. […] That was Marshall's request. His reasoning was that as it's now MMIO related, it should be placed under the southbridge.h were all MMIO related southbridge.h are. the remaining smbus.h are NOT MMIO related. https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/sm.c File src/soc/amd/stoneyridge/sm.c: https://review.coreboot.org/#/c/29258/12/src/soc/amd/stoneyridge/sm.c@64 PS12, Line 64: get_sm_mmio(dev) > It seems horribly inefficient to have to do this every time. […] The code being called is static on the same file. That said, it's 5 lines plus 2 pointers, so I believe it's optimized already. The procedure will return either the SMBUS or the ASF MMIO base address. It's definitely not being used for the SMBUS. I'm not sure if it's being used for ASF, though I don't think so. -- To view, visit https://review.coreboot.org/c/coreboot/+/29258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Gerrit-Change-Number: 29258 Gerrit-PatchSet: 12 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 16:10:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]cpu/x86/lapic: Link apic_timer.c into SMM
by HAOUAS Elyes (Code Review) 29 Jan '19

29 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30020 ) Change subject: [WIP]cpu/x86/lapic: Link apic_timer.c into SMM ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic14919f89b226b4d5185e49ae857e7dd61bbccce Gerrit-Change-Number: 30020 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 14:39:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig
by Paul Menzel (Code Review) 29 Jan '19

29 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31133 ) Change subject: soc/intel/cannonlake: Add SOC_INTEL_WHISKEYLAKE kconfig ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/31133/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31133/1//COMMIT_MSG@17 PS1, Line 17: added Present tense (imperative mood): add -- To view, visit https://review.coreboot.org/c/coreboot/+/31133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Gerrit-Change-Number: 31133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 29 Jan 2019 14:37:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945/udelay: Use get_ia32_fsb()
by HAOUAS Elyes (Code Review) 29 Jan '19

29 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30799 Change subject: nb/intel/i945/udelay: Use get_ia32_fsb() ...................................................................... nb/intel/i945/udelay: Use get_ia32_fsb() Change-Id: I2dcc9c9f1646c8d89f45de914eb1a431ef4bef2b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/udelay.c 1 file changed, 3 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30799/1 diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 8447453..5f5c1b8 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -17,8 +17,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> - +#include <cpu/intel/fsb.h> /** * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ @@ -31,35 +30,11 @@ u32 fsb = 0, divisor; u32 d; /* ticks per us */ - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - + fsb = get_ia32_fsb(); msr = rdmsr(IA32_PERF_STATUS); divisor = (msr.hi >> 8) & 0x1f; - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor); multiply_to_tsc(&tscd, us, d); -- To view, visit https://review.coreboot.org/c/coreboot/+/30799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dcc9c9f1646c8d89f45de914eb1a431ef4bef2b Gerrit-Change-Number: 30799 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Ronak Kanabar (Code Review) 29 Jan '19

29 Jan '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 3: > Patch Set 3: -Code-Review > > Please update the commit message, once the correct value is clear. I didn't get you can you. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 14:07:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Paul Menzel (Code Review) 29 Jan '19

29 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 3: -Code-Review Please update the commit message, once the correct value is clear. -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 14:03:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by HAOUAS Elyes (Code Review) 29 Jan '19

29 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Patch Set 9: > Why are both CxDRT1 registers programmed with the same value ? > Wouldn't that break if one channel has 8banks DIMMs, but the other > 16banks DIMMs? > What does the datasheet say? Does both channels need to be kept in > sync ? short answer: here intel's information: Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet (page 226): "DRAM Timing (CxDRT1): The x represents a channel, A or B represented by 0 and 1 respectively. The DRT Register defines the timing parameters for all devices in a channel. BIOS programs this register with “least common denominator” values after reading the SPD registers of each DIMM in the channel." Mobile Intel® 945 Express Chipset Family Datasheet (page 129): "Pre-All to Activate Delay (tRPALL): This is applicable only to 8-bank architectures. Must be set to 1 if any rank is populated with 8-bank device technology. 0: tRPALL = tRP 1: tRPALL = tRP + 1" Indeed looks like (even without this patch), when we use 2 different architectures and inbetween an empty slot i.e.: DIMM0 : 16 DIMM1 : empty DIMM2 : 8 it will not boot unless we remove the "if (sysinfo->banksize[i] == 0) continue;" here: https://review.coreboot.org/cgit/coreboot.git/tree/src/northbridge/intel/i9… this solution didn't make sense ! (or I'm wrong). Long answer: I'm trying to figure out why my board sin't boot when: 1) the channel0 is not populated at all 2) one of 4 DIMM is populated with a ram at 533 so, I'm trying to find documented registers and make a comparison between vendor, the document and coreboot. So I think that https://review.coreboot.org/cgit/coreboot.git/tree/src/northbridge/intel/i9… is probably wrong in case channel0 is not populated, I also found some R/WO that we try a re-write again ( see https://review.coreboot.org/#/q/status:open+project:coreboot+branch:master+… ) I just find that https://review.coreboot.org/cgit/coreboot.git/tree/src/northbridge/intel/i9… should be : temp_drt = MCHBAR32(C0DRT1) & 0xcf020088; (as [27:24] and [31:30] are reserved). this needs test This said, probably "CxDRT1 |= (1 << 16)" is not a big deal and we can just add a comment asking to test on Mobile i945 version vendor did set that bit for both channels, but even without it, the chip I have didn't complain (if there is no empty slot in between) So I can drop this and just add a comment ... but for sure, i945 needs more investigation to find why it didn't find the rising edge if channel0 is not populated, and why it didn't support ram at 533 (at least for desktop version) -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 Jan 2019 13:53:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019