coreboot-gerrit January 2019

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Change in ...coreboot[master]: soc/intel/skylake: select FSP_M_XIP if PLATFORM_USES_FSP2_0
by Matt DeVillier (Code Review) 28 Jan '19

28 Jan '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31110 Change subject: soc/intel/skylake: select FSP_M_XIP if PLATFORM_USES_FSP2_0 ...................................................................... soc/intel/skylake: select FSP_M_XIP if PLATFORM_USES_FSP2_0 Select FSP_M_XIP if PLATFORM_USES_FSP2_0, since all SkyKabylake boards require FSP-M XIP when FSP 2.0 is used, and since not having it selected results in a non-booting image. Also, put select FSP_T_XIP if FSP_CAR in proper alphabetical order. Change-Id: I6d3986eda18297b12490cefb236f5de5faca6550 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/skylake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31110/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 442b09a..383b397 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -28,6 +28,8 @@ select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select C_ENVIRONMENT_BOOTBLOCK + select FSP_M_XIP if PLATFORM_USES_FSP2_0 + select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -74,7 +76,6 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select FSP_T_XIP if FSP_CAR config CPU_INTEL_NUM_FIT_ENTRIES int -- To view, visit https://review.coreboot.org/c/coreboot/+/31110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d3986eda18297b12490cefb236f5de5faca6550 Gerrit-Change-Number: 31110 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/apollolake: Add IPU to disable_dev function
by Werner Zeh (Code Review) 28 Jan '19

28 Jan '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30992 Change subject: intel/apollolake: Add IPU to disable_dev function ...................................................................... intel/apollolake: Add IPU to disable_dev function The SoC has an Image Processing Unit which is located on PCI 00:03.0. There is a corresponding parameter for FSP which treats enable/disable of this functionality (IpuEn). Add this device to the disable_dev() function of the chip so that if this device is disabled in devicetree the matching FSP parameter will be disabled as well. Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/pci_devs.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/30992/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b38265f..102ba34 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -482,6 +482,9 @@ case PCH_DEVFN_SMBUS: silconfig->SmbusEnable = 0; break; + case SA_DEVFN_IPU: + silconfig->IpuEn = 0; + break; default: printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", PCI_SLOT(dev->path.pci.devfn), diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index ad726f8..363301d 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -45,6 +45,10 @@ #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEV_SLOT_IPU 0x03 +#define SA_DEVFN_IPU _SA_DEVFN(IPU) +#define SA_DEV_IPU _SA_DEV(IPU) + /* PCH Devices */ #define PCH_DEV_SLOT_NPK 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/30992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726 Gerrit-Change-Number: 30992 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intel/apollolake: Add fixed resources for VTd to system resources
by Werner Zeh (Code Review) 28 Jan '19

28 Jan '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30991 Change subject: intel/apollolake: Add fixed resources for VTd to system resources ...................................................................... intel/apollolake: Add fixed resources for VTd to system resources If the VTd feature is enabled, there will be up to two fixed resources which are set up by the FSP. Add this resources to the list of system resources so that the PCI enumerator will know them. Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/apollolake/systemagent.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/30991/1 diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index c8f1330..6acc3b5 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +20,7 @@ #include <cpu/cpu.h> #include <console/console.h> #include <device/device.h> +#include <device/pci_ops.h> #include <fsp/util.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> @@ -40,6 +42,24 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); + + /* Add VTd resources if VTd is enabled. These resources has been + set up by the FSP-S call. */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + if (MCHBAR32(GFXVTBAR) & VTBAR_ENABLED) { + mmio_resource(dev, *index, + (MCHBAR32(GFXVTBAR) & VTBAR_MASK) / KiB, + VTBAR_SIZE / KiB); + (*index)++; + } + if (MCHBAR32(DEFVTBAR) & VTBAR_ENABLED) { + mmio_resource(dev, *index, + (MCHBAR32(DEFVTBAR) & VTBAR_MASK) / KiB, + VTBAR_SIZE / KiB); + (*index)++; + } } int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, -- To view, visit https://review.coreboot.org/c/coreboot/+/30991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807 Gerrit-Change-Number: 30991 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/apollolake: Add generation of DMAR table
by Werner Zeh (Code Review) 28 Jan '19

28 Jan '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30990 Change subject: soc/apollolake: Add generation of DMAR table ...................................................................... soc/apollolake: Add generation of DMAR table Generate DMAR table if VTd feature is enabled. Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/p2sb.h 3 files changed, 93 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30990/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 0c4ff81..06ebf6c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. - * Copyright (C) 2017 Siemens AG + * Copyright (C) 2017-2018 Siemens AG * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,16 +20,19 @@ #include <arch/acpigen.h> #include <arch/io.h> #include <arch/smp/mpspec.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> #include <intelblocks/sgx.h> +#include <intelblocks/p2sb.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> #include <soc/pci_devs.h> +#include <soc/systemagent.h> #include <string.h> #include "chip.h" @@ -178,6 +181,82 @@ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } +static unsigned long soc_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + uint32_t gfxvtbar = MCHBAR32(GFXVTBAR) & VTBAR_MASK; + uint32_t defvtbar = MCHBAR32(DEFVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED; + unsigned long tmp; + + /* IGD has to be enabled, GFXVTBAR set and enabled as well as allocated + in 32-bit space. */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten + && !MCHBAR32(GFXVTBAR + 4)) { + tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_drhd_fixup(tmp, current); + + /* Add RMRR entry */ + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + /* DEFVTBAR has to be set, enabled, and allocated in 32-bit space. */ + if (defvtbar && defvten && !MCHBAR32(DEFVTBAR + 4)) { + tmp = current; + /* + * P2SB may already be hidden. There's no clear rule, when. + * It is needed to get bus, device and function for IOAPIC and + * HPET device which is stored in P2SB device. So unhide it to + * get the info and hide it again when done. + */ + p2sb_unhide(); + struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + /* Now that it is not needed any more hide P2SB device again. */ + p2sb_hide(); + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, defvtbar); + current += acpi_create_dmar_ds_ioapic(current, + 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long sa_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* Create DMAR table only if virtualization is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + current = acpi_align_current(current); + + return current; +} + void soc_power_states_generation(int core_id, int cores_per_package) { /* Generate P-state tables */ diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index fe9c15f..55fdccd 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,5 +29,12 @@ #define PCODE_INIT_DONE (1 << 8) #define MCHBAR_RAPL_PPL 0x70A8 #define CORE_DISABLE_MASK 0x7168 +#define CAPID0_A 0xE4 +#define VTD_DISABLE (1 << 23) +#define DEFVTBAR 0x6c80 +#define GFXVTBAR 0x6c88 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0xfffff000 +#define VTBAR_SIZE 0x1000 #endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index e5c1f3e..22ab140 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,8 +20,10 @@ #include <stddef.h> #include <stdint.h> -#define PCH_P2SB_E0 0xe0 -#define P2SB_E0_MASKLOCK (1 << 1) +#define PCH_P2SB_E0 0xe0 +#define P2SB_E0_MASKLOCK (1 << 1) +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70 enum { P2SB_EP_MASK_0_REG, -- To view, visit https://review.coreboot.org/c/coreboot/+/30990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Gerrit-Change-Number: 30990 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intelblocks/systemagent: Add ACPI table generation hook
by Werner Zeh (Code Review) 28 Jan '19

28 Jan '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30989 Change subject: intelblocks/systemagent: Add ACPI table generation hook ...................................................................... intelblocks/systemagent: Add ACPI table generation hook In preparation of generating DMAR tables provide the hook in SoC-scope for the systemagent to write ACPI tables. The complete functionality is SoC-specific. Therefore event the entry hook is defined as a weak-function which can be overridden by SoC-code. If the SoC does not have support for generating DMAR tables this hook will make no harm. Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 21 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/30989/1 diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 6b1b9bd..671aabb 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Intel Corp. - * Copyright (C) 2017 Siemens AG + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,6 +75,11 @@ /* Chipset specific settings for filling up fadt table */ void soc_fill_fadt(acpi_fadt_t *fadt); +/* Chipset specific settings for filling up dmar table */ +unsigned long sa_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp); + /* Return the polarity flag for SCI IRQ */ int soc_madt_sci_irq_polarity(int sci); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..7552afe 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2018 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,9 +20,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/systemagent.h> +#include <intelblocks/acpi.h> #include <soc/iomap.h> #include <soc/pci_devs.h> -#include <soc/systemagent.h> #include "systemagent_def.h" /* SoC override function */ @@ -48,6 +49,13 @@ return 0; } +__weak unsigned long sa_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + return current; +} + /* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. @@ -278,11 +286,12 @@ } static struct device_operations systemagent_ops = { - .read_resources = &systemagent_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = soc_systemagent_init, - .ops_pci = &pci_dev_ops_pci, + .read_resources = &systemagent_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .init = soc_systemagent_init, + .ops_pci = &pci_dev_ops_pci, + .write_acpi_tables = sa_write_acpi_tables, }; static const unsigned short systemagent_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/30989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1 Gerrit-Change-Number: 30989 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Don't use a #defines like Kconfig symbols
by HAOUAS Elyes (Code Review) 28 Jan '19

28 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31049 Change subject: src: Don't use a #defines like Kconfig symbols ...................................................................... src: Don't use a #defines like Kconfig symbols This is spoted using ./util/lint/kconfig_lint Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/pci_ops_conf1.c M src/drivers/spi/spi_flash_internal.h M src/include/console/uart.h M src/northbridge/amd/amdfam10/util.c M src/soc/rockchip/rk3288/sdram.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5420/clock.c M src/superio/acpi/pnp.asl M src/superio/acpi/pnp_config.asl M src/superio/smsc/lpc47n207/early_serial.c 10 files changed, 36 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31049/1 diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c index 30cbcb4..e088463 100644 --- a/src/arch/x86/pci_ops_conf1.c +++ b/src/arch/x86/pci_ops_conf1.c @@ -19,10 +19,10 @@ */ #if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) -#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \ +#define CONF_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \ (devfn << 8) | (where & ~3)) #else -#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \ +#define CONF_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \ (devfn << 8) | ((where & 0xff) & ~3) |\ ((where & 0xf00)<<16)) #endif @@ -30,46 +30,46 @@ static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(CONF_CMD(bus, devfn, where), 0xCF8); return inb(0xCFC + (where & 3)); } static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(CONF_CMD(bus, devfn, where), 0xCF8); return inw(0xCFC + (where & 2)); } static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(CONF_CMD(bus, devfn, where), 0xCF8); return inl(0xCFC); } static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(CONF_CMD(bus, devfn, where), 0xCF8); outb(value, 0xCFC + (where & 3)); } static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(CONF_CMD(bus, devfn, where), 0xCF8); outw(value, 0xCFC + (where & 2)); } static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(CONF_CMD(bus, devfn, where), 0xCF8); outl(value, 0xCFC); } -#undef CONFIG_CMD +#undef CONF_CMD const struct pci_bus_operations pci_cf8_conf1 = { .read8 = pci_conf1_read_config8, diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index b42df59..a89610a 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -11,10 +11,10 @@ * is a problem (and well your system already is broken), so err on the side * of caution in case we're dealing with slower SPI buses and/or processors. */ -#define CONFIG_SYS_HZ 100 -#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) -#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) +#define CONF_SYS_HZ 100 +#define SPI_FLASH_PROG_TIMEOUT (2 * CONF_SYS_HZ) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONF_SYS_HZ) +#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONF_SYS_HZ) /* Common commands */ #define CMD_READ_ID 0x9f diff --git a/src/include/console/uart.h b/src/include/console/uart.h index b074f35..5c6e679 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -87,16 +87,16 @@ #endif #if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) -#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE -static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } +#define CONF_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE +static inline void __gdb_hw_init(void) { uart_init(CONF_UART_FOR_GDB); } static inline void __gdb_tx_byte(u8 data) { - uart_tx_byte(CONFIG_UART_FOR_GDB, data); + uart_tx_byte(CONF_UART_FOR_GDB, data); } -static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline void __gdb_tx_flush(void) { uart_tx_flush(CONF_UART_FOR_GDB); } static inline u8 __gdb_rx_byte(void) { - return uart_rx_byte(CONFIG_UART_FOR_GDB); + return uart_rx_byte(CONF_UART_FOR_GDB); } #endif diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c index 4bcb11d..b50be81 100644 --- a/src/northbridge/amd/amdfam10/util.c +++ b/src/northbridge/amd/amdfam10/util.c @@ -38,8 +38,8 @@ #define MMIO_ROUTE_END 0xb8 #define PCIIO_ROUTE_START 0xc0 #define PCIIO_ROUTE_END 0xd8 -#define CONFIG_ROUTE_START 0xe0 -#define CONFIG_ROUTE_END 0xec +#define CONF_ROUTE_START 0xe0 +#define CONF_ROUTE_END 0xec #define PCI_IO_BASE0 0xc0 #define PCI_IO_BASE1 0xc8 @@ -246,7 +246,7 @@ static void showallconfig(int level, struct device *dev) { u8 reg; - for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) { + for (reg = CONF_ROUTE_START; reg <= CONF_ROUTE_END; reg += 4) { u32 val = pci_read_config32(dev, reg); if (val) showconfig(level, reg, val); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 4149a47..0a31964 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -382,7 +382,7 @@ #define PCTL_STAT_MSK (7) #define INIT_MEM (0) #define CONFIG (1) -#define CONFIG_REQ (2) +#define CONF_REQ (2) #define ACCESS (3) #define ACCESS_REQ (4) #define LOW_POWER (5) diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index a6cc3c7..7da7b74 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -22,7 +22,7 @@ #include <timer.h> /* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONF_SYS_CLK_FREQ 24000000 static struct arm_clk_ratios arm_clk_ratios[] = { { @@ -213,7 +213,7 @@ /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ; + freq = CONF_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 0da3522..6d92585 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -22,7 +22,7 @@ #include <timer.h> /* input clock of PLL: SMDK5420 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONF_SYS_CLK_FREQ 24000000 /* Epll Clock division values to achieve different frequency output */ static struct st_epll_con_val epll_div[] = { @@ -96,7 +96,7 @@ /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ; + freq = CONF_SYS_CLK_FREQ; if (pllreg == EPLL || pllreg == RPLL) { k = k & 0xffff; diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl index c5aba6d..002a87d 100644 --- a/src/superio/acpi/pnp.asl +++ b/src/superio/acpi/pnp.asl @@ -40,7 +40,7 @@ #define PNP_IRQ1 IRQ1 #define PNP_DMA0 DMA0 -#define CONFIG_MODE_MUTEX CMMX +#define CONF_MODE_MUTEX CMMX #define ENTER_CONFIG_MODE ENCM #define EXIT_CONFIG_MODE EXCM #define SWITCH_LDN SWLD diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl index a1da4c6..abebb6e 100644 --- a/src/superio/acpi/pnp_config.asl +++ b/src/superio/acpi/pnp_config.asl @@ -37,7 +37,7 @@ * Mutex for accesses to the configuration ports (prolog and * epilog commands are used, so synchronization is useful) */ -Mutex(CONFIG_MODE_MUTEX, 1) +Mutex(CONF_MODE_MUTEX, 1) /* * Enter configuration mode (and aquire mutex) @@ -47,7 +47,7 @@ */ Method (ENTER_CONFIG_MODE, 1) { - Acquire (CONFIG_MODE_MUTEX, 0xFFFF) + Acquire (CONF_MODE_MUTEX, 0xFFFF) #ifdef PNP_ENTER_MAGIC_1ST Store (PNP_ENTER_MAGIC_1ST, PNP_ADDR_REG) #ifdef PNP_ENTER_MAGIC_2ND @@ -77,12 +77,12 @@ #if defined(PNP_EXIT_SPECIAL_REG) && defined(PNP_EXIT_SPECIAL_VAL) Store (PNP_EXIT_SPECIAL_VAL, PNP_EXIT_SPECIAL_REG) #endif - Release (CONFIG_MODE_MUTEX) + Release (CONF_MODE_MUTEX) } /* * Just change the LDN. Make sure that you are in config mode (or - * have otherwise acquired CONFIG_MODE_MUTEX), when calling. + * have otherwise acquired CONF_MODE_MUTEX), when calling. */ Method (SWITCH_LDN, 1) { diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index b8d3960..b8e5c0b 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -49,16 +49,16 @@ u16 lpc_port; int i, j; -#define CONFIG_ENABLE 0x55 -#define CONFIG_DISABLE 0xaa +#define CONF_ENABLE 0x55 +#define CONF_DISABLE 0xaa for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) { lpc_port = lpc_ports[j]; /* enable CONFIG mode */ - outb(CONFIG_ENABLE, lpc_port); + outb(CONF_ENABLE, lpc_port); reg_value = inb(lpc_port); - if (reg_value != CONFIG_ENABLE) { + if (reg_value != CONF_ENABLE) { continue; /* There is no LPC device at this address */ } @@ -94,6 +94,6 @@ outb(reg_value, lpc_port + 1); } } while (0); - outb(CONFIG_DISABLE, lpc_port); + outb(CONF_DISABLE, lpc_port); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b Gerrit-Change-Number: 31049 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

6 18

Change in ...coreboot[master]: vboot: Makefile: Also apply CPPFLAGS include path fixups to ccopts
by Julius Werner (Code Review) 28 Jan '19

28 Jan '19

Hello Thomas Heijligen, Nico Huber, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31084 to review the following change. Change subject: vboot: Makefile: Also apply CPPFLAGS include path fixups to ccopts ...................................................................... vboot: Makefile: Also apply CPPFLAGS include path fixups to ccopts In some cases (e.g. Arm architecture variants), include paths are stuck into <stage>-generic-ccopts rather than CPPFLAGS_<stage> (in fact, the whole redundancy between these two is kinda stupid and we should probably eliminate the latter, but I don't want to get into that right now). This patch makes sure those paths are also correctly translated when invoking $(MAKE) for vboot. Change-Id: I37f09b88e555567590664e0e6fac23c34fd887df Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/Makefile.inc 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31084/1 diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index ae80a02..6c63f7b 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -81,16 +81,17 @@ romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c +vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ + $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ + $(filter-out -I$(obj),$(1)))) # call with $1 = stage name to create rules for building the library # for the stage and adding it to the stage's set of object files. define vboot-for-stage VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a -VBOOT_CFLAGS_$(1) += $$(patsubst -I%,-I$(top)/%,\ - $$(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ - $$(filter-out -I$(obj), $$(CPPFLAGS_$(1))))) +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) -VBOOT_CFLAGS_$(1) += $$($(1)-c-ccopts) +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG -- To view, visit https://review.coreboot.org/c/coreboot/+/31084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f09b88e555567590664e0e6fac23c34fd887df Gerrit-Change-Number: 31084 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mb/asus/h61m-cs: Add ASUS H61M-CS
by DevMaster64 (Code Review) 28 Jan '19

28 Jan '19

DevMaster64 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30767 Change subject: mb/asus/h61m-cs: Add ASUS H61M-CS ...................................................................... mb/asus/h61m-cs: Add ASUS H61M-CS Working: - USB - PCIe - PCIe graphics - All SATA ports - Native memory init - On-board audio (back and front) Not working: - S3 (Resume causes a reboot) - Fan control Untested: - PS/2 - On board graphics Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2 Signed-off-by: DevMaster64 (realdevmaster64(a)gmail.com) --- A src/mainboard/asus/h61m-cs/Kconfig A src/mainboard/asus/h61m-cs/Kconfig.name A src/mainboard/asus/h61m-cs/Makefile.inc A src/mainboard/asus/h61m-cs/acpi/ec.asl A src/mainboard/asus/h61m-cs/acpi/platform.asl A src/mainboard/asus/h61m-cs/acpi/superio.asl A src/mainboard/asus/h61m-cs/acpi_tables.c A src/mainboard/asus/h61m-cs/board_info.txt A src/mainboard/asus/h61m-cs/cmos.default A src/mainboard/asus/h61m-cs/cmos.layout A src/mainboard/asus/h61m-cs/devicetree.cb A src/mainboard/asus/h61m-cs/dsdt.asl A src/mainboard/asus/h61m-cs/gma-mainboard.ads A src/mainboard/asus/h61m-cs/gnvs.c A src/mainboard/asus/h61m-cs/gpio.c A src/mainboard/asus/h61m-cs/hda_verb.c A src/mainboard/asus/h61m-cs/mainboard.c A src/mainboard/asus/h61m-cs/romstage.c 18 files changed, 863 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30767/1 diff --git a/src/mainboard/asus/h61m-cs/Kconfig b/src/mainboard/asus/h61m-cs/Kconfig new file mode 100644 index 0000000..e5f2b05 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/Kconfig @@ -0,0 +1,44 @@ +if BOARD_ASUS_H61M_CS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA1155 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_NUVOTON_NCT6779D + +config MAINBOARD_DIR + string + default asus/h61m-cs + +config MAINBOARD_PART_NUMBER + string + default "H61M-CS" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x844d + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/asus/h61m-cs/Kconfig.name b/src/mainboard/asus/h61m-cs/Kconfig.name new file mode 100644 index 0000000..7a111b1 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_H61M_CS + bool "H61M-CS" diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc new file mode 100644 index 0000000..c55eebe --- /dev/null +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/asus/h61m-cs/acpi/ec.asl b/src/mainboard/asus/h61m-cs/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi/ec.asl diff --git a/src/mainboard/asus/h61m-cs/acpi/platform.asl b/src/mainboard/asus/h61m-cs/acpi/platform.asl new file mode 100644 index 0000000..0222986 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asus/h61m-cs/acpi/superio.asl b/src/mainboard/asus/h61m-cs/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi/superio.asl diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/h61m-cs/board_info.txt b/src/mainboard/asus/h61m-cs/board_info.txt new file mode 100644 index 0000000..b0a8878 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/in/Motherboards/H61MCS +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: n diff --git a/src/mainboard/asus/h61m-cs/cmos.default b/src/mainboard/asus/h61m-cs/cmos.default new file mode 100644 index 0000000..6f3cec7 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/asus/h61m-cs/cmos.layout b/src/mainboard/asus/h61m-cs/cmos.layout new file mode 100644 index 0000000..095e383 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/cmos.layout @@ -0,0 +1,107 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb new file mode 100644 index 0000000..286e8a7 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -0,0 +1,112 @@ +chip northbridge/intel/sandybridge # The board has a D-SUB only. I don't have a D-SUB monitor. So this is not tested. + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x13" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1043 0x844d + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1043 0x844d + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1043 0x8445 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1043 0x844d + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1043 0x844d + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x1043 0x844d + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1043 0x844d + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1043 0x844d + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1043 0x844d + end + device pci 1f.3 on # SMBus + subsystemid 0x1043 0x844d + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1043 0x844d + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x1043 0x844d + end + device pci 02.0 off # Internal graphics + end + end +end diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl new file mode 100644 index 0000000..02a5e32 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/asus/h61m-cs/gma-mainboard.ads b/src/mainboard/asus/h61m-cs/gma-mainboard.ads new file mode 100644 index 0000000..d2233d6 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; version 2 of the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe. Thus, probe ports that likely have a high-resolution + -- display attached first. + + ports : constant Port_List := + (HDMI3, -- mainboard HDMI port + HDMI1, -- mainboard DVI-D port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61m-cs/gnvs.c b/src/mainboard/asus/h61m-cs/gnvs.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/gnvs.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/h61m-cs/gpio.c b/src/mainboard/asus/h61m-cs/gpio.c new file mode 100644 index 0000000..b963f6e --- /dev/null +++ b/src/mainboard/asus/h61m-cs/gpio.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61m-cs/hda_verb.c b/src/mainboard/asus/h61m-cs/hda_verb.c new file mode 100644 index 0000000..2290fdc --- /dev/null +++ b/src/mainboard/asus/h61m-cs/hda_verb.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x40330000), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19030), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19040), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181303f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214020), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4024c601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h61m-cs/mainboard.c b/src/mainboard/asus/h61m-cs/mainboard.c new file mode 100644 index 0000000..17b2cec --- /dev/null +++ b/src/mainboard/asus/h61m-cs/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c new file mode 100644 index 0000000..2d430ca --- /dev/null +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define SIO_PORT 0x2e +#define SIO_DEV PNP_DEV(SIO_PORT, 0) +#define GPIO_PPOD_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO_PP_OD) +#define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI) +#define HWM_DEV PNP_DEV(SIO_PORT, NCT6779D_HWM_FPLED) +#define GPIO_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO12345678_V) +#define GPIO01_DEV PNP_DEV(SIO_PORT, NCT6779D_WDT1_GPIO01_V) + + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(SIO_DEV); +/* Pin function selection */ + pnp_write_config(SIO_DEV, 0x1a, 0x00); + pnp_write_config(SIO_DEV, 0x2a, 0x40); + pnp_write_config(SIO_DEV, 0x2c, 0x00); + + pnp_set_logical_device(GPIO_PPOD_DEV); + pnp_write_config(SIO_DEV, 0xe4, 0xfc); + pnp_write_config(SIO_DEV, 0xe6, 0x7f); + + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x76); + + /* Power RAM in S3 */ + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + pnp_set_logical_device(HWM_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x7f); + pnp_write_config(SIO_DEV, 0xe4, 0xf1); + pnp_write_config(SIO_DEV, 0xf0, 0x3e); + + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(SIO_DEV, 0x30, 0x2e); + + /* GPIO2 */ + pnp_write_config(SIO_DEV, 0xe0, 0xdf); + pnp_write_config(SIO_DEV, 0xe2, 0x00); + pnp_write_config(SIO_DEV, 0xe9, 0x00); + pnp_write_config(SIO_DEV, 0xe1, 0xc0); + + /* GPIO3 */ + pnp_write_config(SIO_DEV, 0xe4, 0x7f); + pnp_write_config(SIO_DEV, 0xe6, 0x00); + pnp_write_config(SIO_DEV, 0xea, 0x00); + pnp_write_config(SIO_DEV, 0xe5, 0x70); + + /* GPIO5 */ + pnp_write_config(SIO_DEV, 0xf4, 0xfc); + pnp_write_config(SIO_DEV, 0xf6, 0x00); + pnp_write_config(SIO_DEV, 0xeb, 0x00); + pnp_write_config(SIO_DEV, 0xf5, 0x88); + + pnp_set_logical_device(GPIO01_DEV); + + /* GPIO1 */ + pnp_write_config(SIO_DEV, 0xf0, 0x7f); + pnp_write_config(SIO_DEV, 0xf2, 0x00); + pnp_write_config(SIO_DEV, 0xf4, 0x00); + pnp_write_config(SIO_DEV, 0xf1, 0x03); + + nuvoton_pnp_exit_conf_state(SIO_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); //My slot 0 is short so assuming 0x50 + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2 Gerrit-Change-Number: 30767 Gerrit-PatchSet: 1 Gerrit-Owner: DevMaster64 <realdevmaster64(a)gmail.com> Gerrit-MessageType: newchange

7 42

Change in ...coreboot[master]: mb/google/octopus: Fix termination for unused dual voltage pins
by Shamile Khan (Code Review) 28 Jan '19

28 Jan '19

Shamile Khan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30823 Change subject: mb/google/octopus: Fix termination for unused dual voltage pins ...................................................................... mb/google/octopus: Fix termination for unused dual voltage pins These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5 Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> --- M src/mainboard/google/octopus/variants/casta/gpio.c M src/mainboard/google/octopus/variants/fleex/gpio.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30823/1 diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index ba26e31..d061cb2 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -27,11 +27,11 @@ PAD_NC(GPIO_67, UP_20K), /* EN_PP3300_DX_LTE_SOC -- unused */ - PAD_NC(GPIO_105, DN_20K), /* TOUCHSCREEN_RST -- unused */ + PAD_NC(GPIO_105, UP_20K), /* TOUCHSCREEN_RST -- unused */ PAD_NC(GPIO_108, NONE), /* PMU_SUSCLK -- unused */ - PAD_NC(GPIO_114, DN_20K), /* I2C7 Touchscreen -- unused */ - PAD_NC(GPIO_115, DN_20K), /* I2C7 Touchscreen -- unused */ + PAD_NC(GPIO_114, UP_20K), /* I2C7 Touchscreen -- unused */ + PAD_NC(GPIO_115, UP_20K), /* I2C7 Touchscreen -- unused */ PAD_NC(GPIO_117, UP_20K), /* PCIE_WAKE1_B - No LTE*/ PAD_NC(GPIO_119, UP_20K), /* PCIE_WAKE3_B - only use CNVI */ diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 39d239b..b8db331 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -32,8 +32,8 @@ PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), - PAD_NC(GPIO_138, DN_20K), - PAD_NC(GPIO_139, DN_20K), + PAD_NC(GPIO_138, UP_20K), + PAD_NC(GPIO_139, UP_20K), PAD_NC(GPIO_140, UP_20K), PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), -- To view, visit https://review.coreboot.org/c/coreboot/+/30823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5 Gerrit-Change-Number: 30823 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK fr...
by Seunghwan Kim (Code Review) 28 Jan '19

28 Jan '19

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31085 Change subject: mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequency ...................................................................... mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequency ELAN touchpad supports up to 400KHz, so we need to limit its CLK frequency to 400HKz. BUG=NONE BRANCH=octopus TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/octopus/variants/casta/overridetree.cb 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31085/1 diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index 8915e1a..fbb1826 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -8,12 +7,25 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, }" device domain 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/31085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf Gerrit-Change-Number: 31085 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019