DevMaster64 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30767
Change subject: mb/asus/h61m-cs: Add ASUS H61M-CS ......................................................................
mb/asus/h61m-cs: Add ASUS H61M-CS
Working: - USB - PCIe - PCIe graphics - All SATA ports - Native memory init - On-board audio (back and front)
Not working: - S3 (Resume causes a reboot) - Fan control
Untested: - PS/2 - On board graphics Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2 Signed-off-by: DevMaster64 (realdevmaster64@gmail.com) --- A src/mainboard/asus/h61m-cs/Kconfig A src/mainboard/asus/h61m-cs/Kconfig.name A src/mainboard/asus/h61m-cs/Makefile.inc A src/mainboard/asus/h61m-cs/acpi/ec.asl A src/mainboard/asus/h61m-cs/acpi/platform.asl A src/mainboard/asus/h61m-cs/acpi/superio.asl A src/mainboard/asus/h61m-cs/acpi_tables.c A src/mainboard/asus/h61m-cs/board_info.txt A src/mainboard/asus/h61m-cs/cmos.default A src/mainboard/asus/h61m-cs/cmos.layout A src/mainboard/asus/h61m-cs/devicetree.cb A src/mainboard/asus/h61m-cs/dsdt.asl A src/mainboard/asus/h61m-cs/gma-mainboard.ads A src/mainboard/asus/h61m-cs/gnvs.c A src/mainboard/asus/h61m-cs/gpio.c A src/mainboard/asus/h61m-cs/hda_verb.c A src/mainboard/asus/h61m-cs/mainboard.c A src/mainboard/asus/h61m-cs/romstage.c 18 files changed, 863 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30767/1
diff --git a/src/mainboard/asus/h61m-cs/Kconfig b/src/mainboard/asus/h61m-cs/Kconfig new file mode 100644 index 0000000..e5f2b05 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/Kconfig @@ -0,0 +1,44 @@ +if BOARD_ASUS_H61M_CS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA1155 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_NUVOTON_NCT6779D + +config MAINBOARD_DIR + string + default asus/h61m-cs + +config MAINBOARD_PART_NUMBER + string + default "H61M-CS" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x844d + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/asus/h61m-cs/Kconfig.name b/src/mainboard/asus/h61m-cs/Kconfig.name new file mode 100644 index 0000000..7a111b1 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_H61M_CS + bool "H61M-CS" diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc new file mode 100644 index 0000000..c55eebe --- /dev/null +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/asus/h61m-cs/acpi/ec.asl b/src/mainboard/asus/h61m-cs/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi/ec.asl diff --git a/src/mainboard/asus/h61m-cs/acpi/platform.asl b/src/mainboard/asus/h61m-cs/acpi/platform.asl new file mode 100644 index 0000000..0222986 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asus/h61m-cs/acpi/superio.asl b/src/mainboard/asus/h61m-cs/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi/superio.asl diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/h61m-cs/board_info.txt b/src/mainboard/asus/h61m-cs/board_info.txt new file mode 100644 index 0000000..b0a8878 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/in/Motherboards/H61MCS +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: n diff --git a/src/mainboard/asus/h61m-cs/cmos.default b/src/mainboard/asus/h61m-cs/cmos.default new file mode 100644 index 0000000..6f3cec7 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/asus/h61m-cs/cmos.layout b/src/mainboard/asus/h61m-cs/cmos.layout new file mode 100644 index 0000000..095e383 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/cmos.layout @@ -0,0 +1,107 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb new file mode 100644 index 0000000..286e8a7 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -0,0 +1,112 @@ +chip northbridge/intel/sandybridge # The board has a D-SUB only. I don't have a D-SUB monitor. So this is not tested. + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x13" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1043 0x844d + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1043 0x844d + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1043 0x8445 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1043 0x844d + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1043 0x844d + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x1043 0x844d + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1043 0x844d + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1043 0x844d + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1043 0x844d + end + device pci 1f.3 on # SMBus + subsystemid 0x1043 0x844d + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1043 0x844d + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x1043 0x844d + end + device pci 02.0 off # Internal graphics + end + end +end diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl new file mode 100644 index 0000000..02a5e32 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/asus/h61m-cs/gma-mainboard.ads b/src/mainboard/asus/h61m-cs/gma-mainboard.ads new file mode 100644 index 0000000..d2233d6 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Angel Pons th3fanbus@gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; version 2 of the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe. Thus, probe ports that likely have a high-resolution + -- display attached first. + + ports : constant Port_List := + (HDMI3, -- mainboard HDMI port + HDMI1, -- mainboard DVI-D port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h61m-cs/gnvs.c b/src/mainboard/asus/h61m-cs/gnvs.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/asus/h61m-cs/gnvs.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/h61m-cs/gpio.c b/src/mainboard/asus/h61m-cs/gpio.c new file mode 100644 index 0000000..b963f6e --- /dev/null +++ b/src/mainboard/asus/h61m-cs/gpio.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/h61m-cs/hda_verb.c b/src/mainboard/asus/h61m-cs/hda_verb.c new file mode 100644 index 0000000..2290fdc --- /dev/null +++ b/src/mainboard/asus/h61m-cs/hda_verb.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x40330000), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19030), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19040), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181303f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214020), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4024c601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h61m-cs/mainboard.c b/src/mainboard/asus/h61m-cs/mainboard.c new file mode 100644 index 0000000..17b2cec --- /dev/null +++ b/src/mainboard/asus/h61m-cs/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c new file mode 100644 index 0000000..2d430ca --- /dev/null +++ b/src/mainboard/asus/h61m-cs/romstage.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define SIO_PORT 0x2e +#define SIO_DEV PNP_DEV(SIO_PORT, 0) +#define GPIO_PPOD_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO_PP_OD) +#define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI) +#define HWM_DEV PNP_DEV(SIO_PORT, NCT6779D_HWM_FPLED) +#define GPIO_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO12345678_V) +#define GPIO01_DEV PNP_DEV(SIO_PORT, NCT6779D_WDT1_GPIO01_V) + + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(SIO_DEV); +/* Pin function selection */ + pnp_write_config(SIO_DEV, 0x1a, 0x00); + pnp_write_config(SIO_DEV, 0x2a, 0x40); + pnp_write_config(SIO_DEV, 0x2c, 0x00); + + pnp_set_logical_device(GPIO_PPOD_DEV); + pnp_write_config(SIO_DEV, 0xe4, 0xfc); + pnp_write_config(SIO_DEV, 0xe6, 0x7f); + + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x76); + + /* Power RAM in S3 */ + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + pnp_set_logical_device(HWM_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x7f); + pnp_write_config(SIO_DEV, 0xe4, 0xf1); + pnp_write_config(SIO_DEV, 0xf0, 0x3e); + + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(SIO_DEV, 0x30, 0x2e); + + /* GPIO2 */ + pnp_write_config(SIO_DEV, 0xe0, 0xdf); + pnp_write_config(SIO_DEV, 0xe2, 0x00); + pnp_write_config(SIO_DEV, 0xe9, 0x00); + pnp_write_config(SIO_DEV, 0xe1, 0xc0); + + /* GPIO3 */ + pnp_write_config(SIO_DEV, 0xe4, 0x7f); + pnp_write_config(SIO_DEV, 0xe6, 0x00); + pnp_write_config(SIO_DEV, 0xea, 0x00); + pnp_write_config(SIO_DEV, 0xe5, 0x70); + + /* GPIO5 */ + pnp_write_config(SIO_DEV, 0xf4, 0xfc); + pnp_write_config(SIO_DEV, 0xf6, 0x00); + pnp_write_config(SIO_DEV, 0xeb, 0x00); + pnp_write_config(SIO_DEV, 0xf5, 0x88); + + pnp_set_logical_device(GPIO01_DEV); + + /* GPIO1 */ + pnp_write_config(SIO_DEV, 0xf0, 0x7f); + pnp_write_config(SIO_DEV, 0xf2, 0x00); + pnp_write_config(SIO_DEV, 0xf4, 0x00); + pnp_write_config(SIO_DEV, 0xf1, 0x03); + + nuvoton_pnp_exit_conf_state(SIO_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); //My slot 0 is short so assuming 0x50 + read_spd(&spd[2], 0x52, id_only); +}