coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/lenovo/thinkcentre_a58: Extend mb name
by Arthur Heymans (Code Review) 28 Jan '19

28 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31109 Change subject: mb/lenovo/thinkcentre_a58: Extend mb name ...................................................................... mb/lenovo/thinkcentre_a58: Extend mb name While branded as thinkcentre a58 this board can also be found as "L-IG41M". Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/thinkcentre_a58/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31109/1 diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig.name b/src/mainboard/lenovo/thinkcentre_a58/Kconfig.name index edc44fa..97c07cb 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig.name +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_LENOVO_THINKCENTRE_A58 - bool "ThinkCentre A58" + bool "ThinkCentre A58 (L-IG41M)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3 Gerrit-Change-Number: 31109 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Using HID over I2C to enable Melf T...
by Chris Zhou (Code Review) 28 Jan '19

28 Jan '19

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31062 Change subject: mb/google/sarien/variants/sarien: Using HID over I2C to enable Melf TouchScreen ...................................................................... mb/google/sarien/variants/sarien: Using HID over I2C to enable Melf TouchScreen Current Melfas touchscreen driver cannot unregister ifself when connecting without Melfas touchscreen or connecting with other devices. And Melfas touchscreen FW can use I2C and HID over I2C driver, so switch to using HID over I2C driver. BUG=b:122710830 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186 --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/31062/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 59f1f30..05c63bd 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -221,14 +221,16 @@ end device pci 14.5 off end # SDCard device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""MLFS0000"" - register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "probed" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "enable_delay_ms" = "5" - register "has_power_resource" = "1" + chip drivers/i2c/hid + register "generic.hid" = ""ACPI0C50"" + register "generic.desc" = ""Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + register "generic.enable_delay_ms" = "5" + register "generic.enable_off_delay_ms" = "100" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x0" device i2c 10 on end end end # I2C #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/31062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186 Gerrit-Change-Number: 31062 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: amd/stoneyridge: Disable GPIO MASK STATUS
by Raul Rangel (Code Review) 28 Jan '19

28 Jan '19

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31082 Change subject: amd/stoneyridge: Disable GPIO MASK STATUS ...................................................................... amd/stoneyridge: Disable GPIO MASK STATUS MASK_STATUS disables interrupt status generation for the entire GPIO controller when any debounce register is configured. This causes problems when the kernel is loading drivers because we could lose interrupts for previously loaded devices. sb_program_gpios is also not setup to wait when configuring PAD_DEBOUNCE, so there is a potential that we could lose the interrupt status enable bit for other registers. By disabling MASK_STATUS we avoid that problem. BUG=b:113880780 BRANCH=none TEST=Ran a reboot stress test that concluded that we are no longer losing TPM interrupts while booting. Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31082/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index bca8f5d..9b0d2b1 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -251,15 +251,31 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { uint8_t *mux_ptr; - uint32_t *gpio_ptr; + uint32_t *gpio_ptr, *inter_master; uint32_t control, control_flags, edge_level, direction; uint32_t mask, bit_edge, bit_level, debounce; uint8_t mux, index, gpio; int gevent_num; + inter_master = (uint32_t *)(uintptr_t)(GPIO_CONTROL_MMIO_BASE + + INTER_MASTER_SWITCH); direction = 0; edge_level = 0; mask = 0; + + /* Disable blocking wake/interrupt status generation while updating + debounce registers. Otherwise when a debounce register is updated + the whole GPIO controller will zero out all interrupt enable status + bits while the delay happens. This could cause us to drop the bits + due to the read-modify-write that happens on each register. + + Additionally disable interrupt generation so we don't get any + spurious interrupts while updating the registers. + */ + mem_read_write32(inter_master, + MASK_STATUS_DISABLE | GPIO_INTER_DISABLE, + MASK_STATUS_MASK | GPIO_INTER_MASK); + for (index = 0; index < size; index++) { gpio = gpio_list_ptr[index].gpio; mux = gpio_list_ptr[index].function; @@ -323,6 +339,12 @@ AMD_GPIO_CONTROL_MASK); } } + + /* Re-enable interrupt status generation. We leave MASK_STATUS disabled + because the kernel will reconfigure the debounce registers while the + drivers load. This will cause interrupts to be missed during boot. */ + mem_read_write32(inter_master, GPIO_INTER_ENABLE, GPIO_INTER_MASK); + /* Set all SCI trigger direction (high/low) */ mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_TRIG), direction, mask); diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 422ee57..bf2b714 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -41,6 +41,16 @@ uint8_t mux_value; }; +#define INTER_MASTER_SWITCH 0xFC +#define MASK_STATUS_SHIFT 28 +#define MASK_STATUS_MASK (1 << MASK_STATUS_SHIFT) +#define MASK_STATUS_ENABLE (1 << MASK_STATUS_SHIFT) +#define MASK_STATUS_DISABLE 0 +#define GPIO_INTER_SHIFT 30 +#define GPIO_INTER_MASK (1 << GPIO_INTER_SHIFT) +#define GPIO_INTER_ENABLE (1 << GPIO_INTER_SHIFT) +#define GPIO_INTER_DISABLE 0 + #define GPIO_I2C0_SCL BIT(0) #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) -- To view, visit https://review.coreboot.org/c/coreboot/+/31082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a Gerrit-Change-Number: 31082 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/denverton_ns: Add ACPI T-States and P-States
by Patrick Georgi (Code Review) 28 Jan '19

28 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25430 ) Change subject: soc/intel/denverton_ns: Add ACPI T-States and P-States ...................................................................... soc/intel/denverton_ns: Add ACPI T-States and P-States Also make soc_get_tss_table public and weak instead of static in intelblock so it can be overridden in denverton. Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/25430 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Vanny E <vanessa.f.eusebio(a)intel.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott(a)sysproconsulting.com> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/denverton_ns/acpi.c 3 files changed, 31 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Vanny E: Looks good to me, but someone else must approve Jay Talbott: Looks good to me, but someone else must approve David Guckian: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 5a1cc81..0027744 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -380,7 +380,7 @@ acpigen_pop_len(); } -static acpi_tstate_t *soc_get_tss_table(int *entries) +__attribute__ ((weak)) acpi_tstate_t *soc_get_tss_table(int *entries) { *entries = 0; return NULL; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 6b1b9bd..029174f 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -66,6 +66,12 @@ acpi_cstate_t *soc_get_cstate_map(size_t *num_entries); /* + * get_tstate_map returns a table of processor specific acpi_tstate_t entries + * and number of entries in the table + */ +acpi_tstate_t *soc_get_tss_table(int *entries); + +/* * Chipset specific quirks for the wake enable bits. * Returns wake events for the soc. */ diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index c7eb931..fd89c79 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -248,6 +248,30 @@ motherboard_fill_fadt(fadt); } +static acpi_tstate_t denverton_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = ARRAY_SIZE(denverton_tss_table); + return denverton_tss_table; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ + generate_p_state_entries(core_id, cores_per_package); + + generate_t_state_entries(core_id, cores_per_package); +} + int soc_madt_sci_irq_polarity(int sci) { if (sci >= 20) -- To view, visit https://review.coreboot.org/c/coreboot/+/25430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Gerrit-Change-Number: 25430 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by HAOUAS Elyes (Code Review) 28 Jan '19

28 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Patch Set 9: > Also, according to "Intel® 945G/945GZ/945GC/945P/945PL Express > Chipset Family", this bit is reserved on desktop variants. I don't > think it should be set. regarding that document , Refresh Cycle Time (tRFC), Pre-All to Activate Delay (tRPALL), Activate to Precharge Delay (tRAS), Read to Precharge (tRTP) are also reserved ... ! :) -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 13:27:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by HAOUAS Elyes (Code Review) 28 Jan '19

28 Jan '19

Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28648 to look at the new patch set (#9). Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank Regarding "Mobile Intel® 945 Express Chipset Family - June 2008" datasheet, page #129, CxDRT1 bit #16 "Pre-All to Activate Delay" must be set if any rank is populated with 8-bank device technology. Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28648/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by HAOUAS Elyes (Code Review) 28 Jan '19

28 Jan '19

Hello Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28648 to look at the new patch set (#8). Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank Regarding "Mobile Intel® 945 Express Chipset Family - June 2008" datasheet, page #129, CxDRT1 bit #16 "Pre-All to Activate Delay" must be set if any rank is populated with 8-bank device technology. Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28648/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by HAOUAS Elyes (Code Review) 28 Jan '19

28 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Patch Set 7: (1 comment) > Also, according to "Intel® 945G/945GZ/945GC/945P/945PL Express > Chipset Family", this bit is reserved on desktop variants. I don't > think it should be set. "Intel® 945G/945GZ/945GC/945P/945PL Express Chipset Family" is shitty.. :) https://review.coreboot.org/#/c/28648/7/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/28648/7/src/northbridge/intel/i945/raminit.… PS7, Line 1495: if (sysinfo->banks[i] != 8) : continue; : temp_drt |= (1 << 16); > Since we only want to set this bit once, why don't we do the following: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 13:01:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/{google,intel}: Remove SaGv hard coding
by Angel Pons (Code Review) 28 Jan '19

28 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31120 ) Change subject: mainboard/{google,intel}: Remove SaGv hard coding ...................................................................... Patch Set 2: Code-Review+1 Thank you! -- To view, visit https://review.coreboot.org/c/coreboot/+/31120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Gerrit-Change-Number: 31120 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 28 Jan 2019 12:52:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank
by Angel Pons (Code Review) 28 Jan '19

28 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 ) Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ...................................................................... Patch Set 7: Also, according to "Intel® 945G/945GZ/945GC/945P/945PL Express Chipset Family", this bit is reserved on desktop variants. I don't think it should be set. -- To view, visit https://review.coreboot.org/c/coreboot/+/28648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c7dccd295e187acfe00a08294010af53b4d0ee Gerrit-Change-Number: 28648 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Jan 2019 12:46:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019