coreboot-gerrit January 2019

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Nico Huber (Code Review) 27 Jan '19

27 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: > Aha, I recall now. What is the issue with the current setup? Does it fail to see something is attached on the DP port, or do eDP ports need some additional config to enable the backlight? It's a historical issue. Originally, libgfxinit (on Ironlake) only … [View More]

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Angel Pons (Code Review) 27 Jan '19

27 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: > Patch Set 6: Code-Review-1 > > tl;dr don't expect this to work. > > >> looks good to me, but should be tested again before i give a +2 > > > > I have build current master (edbf5d91) with patch set 6 applied for both a normal … [View More]x230 and x230_fhd. > > I have tested the following setup: coreboot -> seabios -> grub on both devices. > > > > The normal x230 works as expected. > > > > On the device with FHD-mod booting works as well, but graphical output of coreboot, seabios and grub is only visible if an additional external monitor is attached via VGA or DP. The internal FHD panel becomes active as soon as the linux kernel takes over. Right now I am unsure if this is due to misconfiguration on my part or if coreboot/libgfxinit needs to be told to use eDP1 for output on modded devices. > > That is exactly the problem. libgfxinit needs to be taught to > treat the DP as eDP (i.e. with a panel attached). That's what > I said in my very first comment on this change ;) to avoid all > the confusion. Obviously that wasn't visible enough, hence the > score now. > > It only works by coincidence with the setup this was tested > with originally. So please either write down what exact setup > this was, or implement proper power sequencing first. Aha, I recall now. What is the issue with the current setup? Does it fail to see something is attached on the DP port, or do eDP ports need some additional config to enable the backlight? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Sun, 27 Jan 2019 14:45:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment [View Less]

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Change in ...coreboot[master]: [WIP] add i945G based mainboard
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25509 ) Change subject: [WIP] add i945G based mainboard ...................................................................... Patch Set 25: (1 comment) https://review.coreboot.org/#/c/25509/25//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25509/25//COMMIT_MSG@11 PS25, Line 11: CPUID 0f65.Mmicrocode loaded correctly. CPUID 0F65 Microcode loaded correctly. -- To view, visit … [View More]

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Change in ...coreboot[master]: [WIP] add i945G based mainboard
by build bot (Jenkins) (Code Review) 27 Jan '19

27 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25509 ) Change subject: [WIP] add i945G based mainboard ...................................................................... Patch Set 25: (8 comments) https://review.coreboot.org/#/c/25509/25/src/mainboard/nec/945g-m4/superio_… File src/mainboard/nec/945g-m4/superio_hwm.c: https://review.coreboot.org/#/c/25509/25/src/mainboard/nec/945g-m4/superio_… PS25, Line 83: //if (get_option(&… [View More]

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Change in ...coreboot[master]: [WIP] add i945G based mainboard
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

Hello Kyösti Mälkki, Patrick Rudolph, Arthur Heymans, Idwer Vollering, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25509 to look at the new patch set (#25). Change subject: [WIP] add i945G based mainboard ...................................................................... [WIP] add i945G based mainboard 82945GC - 82801Gx - W83627EHG CPU: CPUID 0f65.Mmicrocode … [View More]loaded correctly. DDR2: Supports Up to 4 DIMM. S3: working properly. Issues: 1) It will not boot when using RAM 533MHz. I believe that there is a problem with time/clock or something related to clock when RAM 533 is used. 2) It will not boot if channel 0 is not populated at all. 3) HWM is not working. The FAN is running at high speed. Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A src/mainboard/nec/945g-m4/Kconfig A src/mainboard/nec/945g-m4/Kconfig.name A src/mainboard/nec/945g-m4/Makefile.inc A src/mainboard/nec/945g-m4/acpi/ec.asl A src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl A src/mainboard/nec/945g-m4/acpi/mainboard.asl A src/mainboard/nec/945g-m4/acpi/platform.asl A src/mainboard/nec/945g-m4/acpi/superio.asl A src/mainboard/nec/945g-m4/acpi/thermal.asl A src/mainboard/nec/945g-m4/acpi/video.asl A src/mainboard/nec/945g-m4/acpi_tables.c A src/mainboard/nec/945g-m4/board_info.txt A src/mainboard/nec/945g-m4/cmos.default A src/mainboard/nec/945g-m4/cmos.layout A src/mainboard/nec/945g-m4/cstates.c A src/mainboard/nec/945g-m4/devicetree.cb A src/mainboard/nec/945g-m4/dsdt.asl A src/mainboard/nec/945g-m4/gpio.c A src/mainboard/nec/945g-m4/hda_verb.c A src/mainboard/nec/945g-m4/mainboard.c A src/mainboard/nec/945g-m4/romstage.c A src/mainboard/nec/945g-m4/superio_hwm.c A src/mainboard/nec/945g-m4/superio_hwm.h A src/mainboard/nec/Kconfig A src/mainboard/nec/Kconfig.name M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/gma.c 27 files changed, 1,410 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/25509/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 25 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset [View Less]

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Change in ...coreboot[master]: src/cpu/intel: Set get_ia32_fsb function common
by Nico Huber (Code Review) 27 Jan '19

27 Jan '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30103 ) Change subject: src/cpu/intel: Set get_ia32_fsb function common ...................................................................... src/cpu/intel: Set get_ia32_fsb function common Add get_ia32_fsb returns FSB values in MHz of intel's CPUs. Also add get_ia32_fsb_x3 function. It returns round up 3 * get_ia32_fsb. Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Signed-off-by: … [View More]Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/30103 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/common/Makefile.inc A src/cpu/intel/common/fsb.c M src/cpu/x86/lapic/apic_timer.c A src/include/cpu/intel/fsb.h 4 files changed, 125 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 1e94ec9..b67ca85 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1 +1,5 @@ ramstage-y += common_init.c +romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c +ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c +postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c new file mode 100644 index 0000000..1f7c391 --- /dev/null +++ b/src/cpu/intel/common/fsb.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/fsb.h> +#include <console/console.h> +#include <commonlib/helpers.h> + +int get_ia32_fsb(void) +{ + struct cpuinfo_x86 c; + static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; + static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 }; + static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 }; + msr_t msr; + int ret = -2; + + get_fms(&c, cpuid_eax(1)); + switch (c.x86) { + case 0x6: + switch (c.x86_model) { + case 0xe: /* Core Solo/Duo */ + case 0x1c: /* Atom */ + ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + break; + case 0xf: /* Core 2 or Xeon */ + case 0x17: /* Enhanced Core */ + ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + break; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + ret = 100; + break; + } + break; + case 0xf: /* Netburst */ + msr = rdmsr(MSR_EBC_FREQUENCY_ID); + switch (c.x86_model) { + case 0x2: + ret = f2x_fsb[(msr.lo >> 16) & 7]; + break; + case 0x3: + case 0x4: + case 0x6: + ret = core2_fsb[(msr.lo >> 16) & 7]; + break; + } + } + if (ret == -1) + printk(BIOS_ERR, "FSB not found\n"); + if (ret == -2) + printk(BIOS_ERR, "CPU not supported\n"); + return ret; +} + +/** + * @brief Returns three times the FSB clock in MHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ +int get_ia32_fsb_x3(void) +{ + const int fsb = get_ia32_fsb(); + + if (fsb > 0) + return 100 * DIV_ROUND_CLOSEST(3 * fsb, 100); + + printk(BIOS_ERR, "FSB not supported or not found\n"); + return -1; +} diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index e6a12ce..b3ddeac 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <arch/cpu.h> #include <arch/early_variables.h> +#include <cpu/intel/fsb.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> @@ -44,53 +45,13 @@ static int set_timer_fsb(void) { - struct cpuinfo_x86 c; - int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; - int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 }; - int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 }; - msr_t msr; + int ia32_fsb = get_ia32_fsb(); - get_fms(&c, cpuid_eax(1)); - switch (c.x86) { - case 0x6: - switch (c.x86_model) { - case 0xe: /* Core Solo/Duo */ - case 0x1c: /* Atom */ - car_set_var(g_timer_fsb, - core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); - return 0; - case 0xf: /* Core 2 or Xeon */ - case 0x17: /* Enhanced Core */ - car_set_var(g_timer_fsb, - core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); - return 0; - case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ - case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ - case 0x3c: /* Haswell BCLK fixed at 100MHz */ - case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - car_set_var(g_timer_fsb, 100); - return 0; - default: - car_set_var(g_timer_fsb, 200); - return 0; - } - case 0xf: /* Netburst */ - msr = rdmsr(MSR_EBC_FREQUENCY_ID); - switch (c.x86_model) { - case 0x2: - car_set_var(g_timer_fsb, - f2x_fsb[(msr.lo >> 16) & 7]); - return 0; - case 0x3: - case 0x4: - case 0x6: - car_set_var(g_timer_fsb, - core2_fsb[(msr.lo >> 16) & 7]); - return 0; - } /* default: fallthrough */ - default: - return -1; + if (ia32_fsb > 0) { + car_set_var(g_timer_fsb, ia32_fsb); + return 0; } + return -1; } static inline u32 get_timer_fsb(void) diff --git a/src/include/cpu/intel/fsb.h b/src/include/cpu/intel/fsb.h new file mode 100644 index 0000000..49f3b17 --- /dev/null +++ b/src/include/cpu/intel/fsb.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CPU_INTEL_FSB_H +#define CPU_INTEL_FSB_H + +/* + * This function returns: + * the system bus speed value in MHz + * -1 if FSB is not found + * -2 if the CPU is not supported + */ +int get_ia32_fsb(void); + +/* + * This function returns round up 3 * get_ia32_fsb() + */ +int get_ia32_fsb_x3(void); + +#endif /* CPU_INTEL_FSB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Gerrit-Change-Number: 30103 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged [View Less]

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Change in ...coreboot[master]: src/cpu/intel: Set get_ia32_fsb function common
by build bot (Jenkins) (Code Review) 27 Jan '19

27 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30103 ) Change subject: src/cpu/intel: Set get_ia32_fsb function common ...................................................................... Patch Set 25: (1 comment) https://review.coreboot.org/#/c/30103/25/src/cpu/intel/common/fsb.c File src/cpu/intel/common/fsb.c: https://review.coreboot.org/#/c/30103/25/src/cpu/intel/common/fsb.c@25 PS25, Line 25: static const short core2_fsb[8] = { … [View More]

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Change in ...coreboot[master]: src/cpu/intel: Add model_f6x
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25565 to look at the new patch set (#28). Change subject: src/cpu/intel: Add model_f6x ...................................................................... src/cpu/intel: Add model_f6x Tested with a cpuid 0xf65 on 945G-M4 board. BIOS Implementation Test Suite (bits-2079)… [View More]

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Change in ...coreboot[master]: arch/x86/smbios(type4): Write processor_upgrade field
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29529 ) Change subject: arch/x86/smbios(type4): Write processor_upgrade field ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Nico Huber (Code Review) 27 Jan '19

27 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: Code-Review-1 tl;dr don't expect this to work. >> looks good to me, but should be tested again before i give a +2 > > I have build current master (edbf5d91) with patch set 6 applied for both a normal x230 and x230_fhd. > I have tested the … [View More]following setup: coreboot -> seabios -> grub on both devices. > > The normal x230 works as expected. > > On the device with FHD-mod booting works as well, but graphical output of coreboot, seabios and grub is only visible if an additional external monitor is attached via VGA or DP. The internal FHD panel becomes active as soon as the linux kernel takes over. Right now I am unsure if this is due to misconfiguration on my part or if coreboot/libgfxinit needs to be told to use eDP1 for output on modded devices. That is exactly the problem. libgfxinit needs to be taught to treat the DP as eDP (i.e. with a panel attached). That's what I said in my very first comment on this change ;) to avoid all the confusion. Obviously that wasn't visible enough, hence the score now. It only works by coincidence with the setup this was tested with originally. So please either write down what exact setup this was, or implement proper power sequencing first. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Sun, 27 Jan 2019 11:30:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment [View Less]

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coreboot-gerrit January 2019