coreboot-gerrit January 2019

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Change in ...coreboot[master]: Revert "util/bincfg: code cleanup: convert sym_table to a local varia...
by Angel Pons (Code Review) 26 Jan '19

26 Jan '19

Hello Denis 'GNUtoo' Carikli, Paul Kocialkowski, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31105 to review the following change. Change subject: Revert "util/bincfg: code cleanup: convert sym_table to a local variable" ...................................................................... Revert "util/bincfg: code cleanup: convert sym_table to a local variable" This … [View More]reverts commit 48c24ce5eefe64b1aa82237f0a4be2772c686ef6. Reason for revert: Commit broke bincfg, and sym_table as a global variable is less bad than passing it around in function calls. Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac --- M util/bincfg/bincfg.h M util/bincfg/bincfg.y 2 files changed, 41 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31105/1 diff --git a/util/bincfg/bincfg.h b/util/bincfg/bincfg.h index c0e1242..b8c6688 100644 --- a/util/bincfg/bincfg.h +++ b/util/bincfg/bincfg.h @@ -37,12 +37,13 @@ unsigned int lenactualblob; }; -static struct field *putsym(field_ptr_t, char const *, unsigned int); -static struct field *getsym(field_ptr_t, char const *); -static void yyerror(FILE *, field_ptr_t, char const *); -int yylex(void); +static struct field *putsym (char const *, unsigned int); +static struct field *getsym (char const *); +static void yyerror (FILE* fp, char const *); +int yylex (void); static struct blob *binary; +static struct field *sym_table; static struct field *sym_table_tail; #endif /* __BINCFG_H */ diff --git a/util/bincfg/bincfg.y b/util/bincfg/bincfg.y index ac65d0f..8be11e9 100644 --- a/util/bincfg/bincfg.y +++ b/util/bincfg/bincfg.y @@ -59,12 +59,10 @@ binary->bloblen += w; } -static void set_bitfield(struct field **sym_table_ptr, char *name, - unsigned int value) +static void set_bitfield(char *name, unsigned int value) { unsigned long long i; - - struct field *bf = getsym(sym_table_ptr, name); + struct field *bf = getsym (name); if (bf) { bf->value = value & 0xffffffff; i = (1 << bf->width) - 1; @@ -80,30 +78,28 @@ } } -static void set_bitfield_array(struct field **sym_table_ptr, char *name, - unsigned int n, unsigned int value) +static void set_bitfield_array(char *name, unsigned int n, unsigned int value) { unsigned int i; unsigned long len = strlen (name); char *namen = (char *) malloc ((len + 9) * sizeof (char)); - check_pointer(namen); for (i = 0; i < n; i++) { snprintf (namen, len + 8, "%s%x", name, i); - set_bitfield (sym_table_ptr, namen, value); + set_bitfield (namen, value); } free(namen); } -static void create_new_bitfield(struct field **sym_table_ptr, char *name, unsigned int width) +static void create_new_bitfield(char *name, unsigned int width) { struct field *bf; - if (!(bf = putsym (sym_table_ptr, name, width))) return; + if (!(bf = putsym (name, width))) return; //fprintf(stderr, "Added bitfield `%s` : %d\n", bf->name, width); } -static void create_new_bitfields(struct field **sym_table_ptr, char *name, unsigned int n, unsigned int width) +static void create_new_bitfields(char *name, unsigned int n, unsigned int width) { unsigned int i; unsigned long len = strlen (name); @@ -111,41 +107,38 @@ check_pointer(namen); for (i = 0; i < n; i++) { snprintf (namen, len + 8, "%s%x", name, i); - create_new_bitfield (sym_table_ptr, namen, width); + create_new_bitfield (namen, width); } free(namen); } -static struct field *putsym (struct field **sym_table_ptr, char const *sym_name, - unsigned int w) +static struct field *putsym (char const *sym_name, unsigned int w) { - if (getsym(sym_table_ptr, sym_name)) { + if (getsym(sym_name)) { fprintf(stderr, "Cannot add duplicate named bitfield `%s`\n", sym_name); return 0; } - struct field *ptr = (field_t ) malloc (sizeof (struct field)); + struct field *ptr = (struct field *) malloc (sizeof (struct field)); check_pointer(ptr); ptr->name = (char *) malloc (strlen (sym_name) + 1); check_pointer(ptr->name); strcpy (ptr->name, sym_name); ptr->width = w; ptr->value = 0; - ptr->next = (field_t)0; + ptr->next = (struct field *)0; if (sym_table_tail) { sym_table_tail->next = ptr; } else { - *sym_table_ptr = ptr; + sym_table = ptr; } sym_table_tail = ptr; return ptr; } -static struct field *getsym (struct field **sym_table_ptr, char const *sym_name) +static struct field *getsym (char const *sym_name) { struct field *ptr; - struct field *sym_table = *sym_table_ptr; - for (ptr = sym_table; ptr != (struct field *) 0; ptr = (struct field *)ptr->next) { if (strcmp (ptr->name, sym_name) == 0) @@ -154,11 +147,9 @@ return 0; } -static void dump_all_values (struct field **sym_table_ptr) +static void dump_all_values (void) { struct field *ptr; - struct field *sym_table = *sym_table_ptr; - for (ptr = sym_table; ptr != (struct field *) 0; ptr = (struct field *)ptr->next) { fprintf(stderr, "%s = %d (%d bits)\n", @@ -168,13 +159,11 @@ } } -static void empty_field_table(struct field **sym_table_ptr) +static void empty_field_table(void) { struct field *ptr; struct field *ptrnext; - struct field *sym_table = *sym_table_ptr; - for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptrnext) { if (ptr) { ptrnext = ptr->next; @@ -219,12 +208,10 @@ } /* {}%BIN -> {} */ -static void generate_setter_bitfields(FILE* fp, struct field **sym_table_ptr, - unsigned char *bin) +static void generate_setter_bitfields(FILE* fp, unsigned char *bin) { unsigned int i; struct field *ptr; - struct field *sym_table = *sym_table_ptr; /* Convert bytes to bit array */ for (i = 0; i < binary->lenactualblob; i++) { @@ -246,14 +233,11 @@ fprintf (fp, "\n}\n"); } -static void generate_binary_with_gbe_checksum(FILE* fp, - struct field **sym_table_ptr) +static void generate_binary_with_gbe_checksum(FILE* fp) { int i; unsigned short checksum; - struct field *sym_table = *sym_table_ptr; - /* traverse spec, push to blob and add up for checksum */ struct field *ptr; unsigned int uptochksum = 0; @@ -293,7 +277,7 @@ checksum = (0xbaba - binary->checksum) & 0xffff; /* Now write checksum */ - set_bitfield (sym_table_ptr, "checksum_gbe", checksum); + set_bitfield ("checksum_gbe", checksum); fprintf(fp, "%c", checksum & 0xff); fprintf(fp, "%c", (checksum & 0xff00) >> 8); @@ -321,11 +305,10 @@ } /* {}{} -> BIN */ -static void generate_binary(FILE* fp, struct field **sym_table_ptr) +static void generate_binary(FILE* fp) { unsigned int i; struct field *ptr; - struct field *sym_table = *sym_table_ptr; if (binary->bloblen % 8) { fprintf (stderr, @@ -333,8 +316,8 @@ exit (1); } - if (getsym (sym_table_ptr, "checksum_gbe")) { - generate_binary_with_gbe_checksum(fp, sym_table_ptr); + if (getsym ("checksum_gbe")) { + generate_binary_with_gbe_checksum(fp); return; } @@ -370,7 +353,7 @@ unsigned char u8; unsigned char *u8array; } -%parse-param {FILE* fp} {struct field** sym_table_ptr} +%parse-param {FILE* fp} %token <str> name %token <u32> val @@ -389,13 +372,13 @@ input: /* empty */ -| input spec setter eof { empty_field_table(sym_table_ptr); YYACCEPT;} +| input spec setter eof { empty_field_table(); YYACCEPT;} | input spec blob { fprintf (stderr, "Parsed all bytes\n"); - empty_field_table(sym_table_ptr); YYACCEPT;} + empty_field_table(); YYACCEPT;} ; blob: - '%' eof { generate_setter_bitfields(fp, sym_table_ptr, + '%' eof { generate_setter_bitfields(fp, binary->actualblob); } ; @@ -411,15 +394,14 @@ ; specpair: - name ':' val { create_new_bitfield(sym_table_ptr, $1, $3); } -| name '[' val ']' ':' val { create_new_bitfields(sym_table_ptr, $1, $3, - $6); } + name ':' val { create_new_bitfield($1, $3); } +| name '[' val ']' ':' val { create_new_bitfields($1, $3, $6); } ; setter: '{' '}' { fprintf (stderr, "No values\n"); } | '{' valuemembers '}' { fprintf (stderr, "Parsed all values\n"); - generate_binary(fp, sym_table_ptr); } + generate_binary(fp); } ; valuemembers: @@ -428,15 +410,14 @@ ; setpair: -name '=' val { set_bitfield(sym_table_ptr, $1, $3); } -| name '[' val ']' '=' val { set_bitfield_array(sym_table_ptr, $1, $3, - $6); } + name '=' val { set_bitfield($1, $3); } +| name '[' val ']' '=' val { set_bitfield_array($1, $3, $6); } ; %% /* Called by yyparse on error. */ -static void yyerror (FILE* fp, struct field **sym_table_ptr, char const *s) +static void yyerror (FILE* fp, char const *s) { fprintf (stderr, "yyerror: %s\n", s); } @@ -445,10 +426,9 @@ void set_input_string(char* in); /* This function parses a string */ -static int parse_string(FILE* fp, struct field **sym_table_ptr, unsigned char* in) -{ +static int parse_string(FILE* fp, unsigned char* in) { set_input_string ((char *)in); - return yyparse (fp, sym_table_ptr); + return yyparse (fp); } static unsigned int loadfile (FILE* fp, char *file, char *filetype, @@ -484,7 +464,6 @@ unsigned int pos = 0; int ret = 0; FILE* fp; - struct field *sym_table; #if YYDEBUG == 1 yydebug = 1; @@ -505,7 +484,7 @@ argv[3]); exit(1); } - ret = parse_string(fp, &sym_table, parsestring); + ret = parse_string(fp, parsestring); free(parsestring); } else if (argc == 5 && strcmp (argv[1], "-d") == 0) { /* Decompile mode */ @@ -537,7 +516,7 @@ argv[4]); exit(1); } - ret = parse_string(fp, &sym_table, parsestring); + ret = parse_string(fp, parsestring); free(parsestring); free(binary->actualblob); fclose(fp); -- To view, visit https://review.coreboot.org/c/coreboot/+/31105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac Gerrit-Change-Number: 31105 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange [View Less]

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Change in ...coreboot[master]: crossgcc: Update CMake to version 3.13.3
by HAOUAS Elyes (Code Review) 26 Jan '19

26 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30966 Change subject: crossgcc: Update CMake to version 3.13.3 ...................................................................... crossgcc: Update CMake to version 3.13.3 Change-Id: If3bd670e2273715b6996e2ca78a0b9c412bfd220 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.13.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.13.3.tar.gz.cksum … [View More]

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Change in ...coreboot[master]: util/crossgcc: Update to binutils 2.31.1 and gcc 8.2
by Patrick Georgi (Code Review) 26 Jan '19

26 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31089 Change subject: util/crossgcc: Update to binutils 2.31.1 and gcc 8.2 ...................................................................... util/crossgcc: Update to binutils 2.31.1 and gcc 8.2 Change-Id: Icf7c6bdd4021bf84cc295c819f93838248e0f4c7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/buildgcc D util/crossgcc/patches/binutils-2.30_nds32.patch R util/… [View More]

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Change in ...coreboot[master]: util/bincfg: code cleanup: convert sym_table to a local variable
by Angel Pons (Code Review) 26 Jan '19

26 Jan '19

Angel Pons has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/27810 ) Change subject: util/bincfg: code cleanup: convert sym_table to a local variable ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/27810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in ...coreboot[master]: util/bincfg: code cleanup: convert sym_table to a local variable
by Arthur Heymans (Code Review) 26 Jan '19

26 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27810 ) Change subject: util/bincfg: code cleanup: convert sym_table to a local variable ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/27810/6/util/bincfg/bincfg.h File util/bincfg/bincfg.h: https://review.coreboot.org/#/c/27810/6/util/bincfg/bincfg.h@39 PS6, Line 39: : static struct field *putsym(… [View More]

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Change in ...coreboot[master]: src/soc/intel/cnl/chip.h: Fix preprocessor condition
by Angel Pons (Code Review) 26 Jan '19

26 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31095 ) Change subject: src/soc/intel/cnl/chip.h: Fix preprocessor condition ...................................................................... Patch Set 4: > Patch Set 4: Code-Review-1 > > Kindly hold this CL, till the time submitter of original CL come and share his view. > -1 just to block this CL from merge else no issue Ack, I will add them as reviewer. -- To view, visit … [View More]

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Change in ...coreboot[master]: src/soc/intel/cnl/chip.h: Fix preprocessor condition
by Subrata Banik (Code Review) 26 Jan '19

26 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31095 ) Change subject: src/soc/intel/cnl/chip.h: Fix preprocessor condition ...................................................................... Patch Set 4: Code-Review-1 Kindly hold this CL, till the time submitter of original CL come and share his view. -1 just to block this CL from merge else no issue -- To view, visit https://review.coreboot.org/c/coreboot/+/31095 To unsubscribe, or for … [View More]

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Change in ...coreboot[master]: mb/clevo/n130wu: Add variants
by Felix Singer (Code Review) 26 Jan '19

26 Jan '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30897 Change subject: mb/clevo/n130wu: Add variants ...................................................................... mb/clevo/n130wu: Add variants Devices: - N130BU / N131BU Change-Id: I1e771c48409f79edb1355af6992ba43269b98b8e Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/mainboard/clevo/n130wu/Kconfig M src/mainboard/clevo/n130wu/Kconfig.name A src/mainboard/clevo/… [View More]n130wu/variants/n13xbu/data.vbt A src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb 4 files changed, 271 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/30897/1 diff --git a/src/mainboard/clevo/n130wu/Kconfig b/src/mainboard/clevo/n130wu/Kconfig index 49a6b56..cb90d01 100644 --- a/src/mainboard/clevo/n130wu/Kconfig +++ b/src/mainboard/clevo/n130wu/Kconfig @@ -1,4 +1,4 @@ -if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU +if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU || BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU config BOARD_SPECIFIC_OPTIONS def_bool y @@ -23,10 +23,13 @@ config VARIANT_DIR string + default "n13xbu" if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default "n13xwu" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU config MAINBOARD_PART_NUMBER string + default "N130BU" if BOARD_CLEVO_N130BU + default "N131BU" if BOARD_CLEVO_N131BU default "N130WU" if BOARD_CLEVO_N130WU default "N131WU" if BOARD_CLEVO_N131WU @@ -44,6 +47,7 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex + default 0x1303 if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default 0x1313 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU config CONSOLE_POST @@ -60,6 +64,7 @@ config MAX_CPUS int + default 4 if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default 8 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU config DIMM_MAX @@ -72,10 +77,12 @@ config VGA_BIOS_FILE string + default "pci8086,5916.rom" if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default "pci8086,5917.rom" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU config VGA_BIOS_ID string + default "8086,5916" if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default "8086,5917" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU config PXE_ROM_ID diff --git a/src/mainboard/clevo/n130wu/Kconfig.name b/src/mainboard/clevo/n130wu/Kconfig.name index f252f0b..a6c84b9 100644 --- a/src/mainboard/clevo/n130wu/Kconfig.name +++ b/src/mainboard/clevo/n130wu/Kconfig.name @@ -1,3 +1,9 @@ +config BOARD_CLEVO_N130BU + bool "N130BU" + +config BOARD_CLEVO_N131BU + bool "N131BU" + config BOARD_CLEVO_N130WU bool "N130WU" diff --git a/src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt b/src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt new file mode 100644 index 0000000..fafa43f --- /dev/null +++ b/src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt Binary files differ diff --git a/src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb b/src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb new file mode 100644 index 0000000..d094df5 --- /dev/null +++ b/src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb @@ -0,0 +1,257 @@ +# WIP + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + register "VmxEnable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_E" + register "gpe0_dw1" = "GPP_A" + register "gpe0_dw2" = "GPP_C" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 5A | 32A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(5), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(32), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Enable root ports + register "PcieRpEnable[0]" = "1" # TBT + register "PcieRpEnable[1]" = "1" # TBT + register "PcieRpEnable[2]" = "1" # TBT + register "PcieRpEnable[3]" = "1" # TBT + register "PcieRpEnable[4]" = "1" # LAN / Card reader + register "PcieRpEnable[5]" = "1" # WLAN + register "PcieRpEnable[8]" = "1" # SSD PCIEx4 + register "PcieRpEnable[9]" = "1" # SSD PCIEx4 + register "PcieRpEnable[10]" = "1" # SSD PCIEx4 + register "PcieRpEnable[11]" = "1" # SSD PCIEx4 + + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" # TBT + register "PcieRpClkReqSupport[1]" = "1" # TBT + register "PcieRpClkReqSupport[2]" = "1" # TBT + register "PcieRpClkReqSupport[3]" = "1" # TBT + register "PcieRpClkReqSupport[4]" = "1" # LAN / Card reader + register "PcieRpClkReqSupport[5]" = "1" # WLAN + register "PcieRpClkReqSupport[8]" = "1" # SSD PCIEx4 + register "PcieRpClkReqSupport[9]" = "1" # SSD PCIEx4 + register "PcieRpClkReqSupport[10]" = "1" # SSD PCIEx4 + register "PcieRpClkReqSupport[11]" = "1" # SSD PCIEx4 + + # Configure SRCCLKREQ# + register "PcieRpClkReqNumber[0]" = "4" # TBT + register "PcieRpClkReqNumber[1]" = "4" # TBT + register "PcieRpClkReqNumber[2]" = "4" # TBT + register "PcieRpClkReqNumber[3]" = "4" # TBT + register "PcieRpClkReqNumber[4]" = "3" # LAN / Card reader + register "PcieRpClkReqNumber[5]" = "2" # WLAN + register "PcieRpClkReqNumber[8]" = "5" # SSD PCIEx4 + register "PcieRpClkReqNumber[9]" = "5" # SSD PCIEx4 + register "PcieRpClkReqNumber[10]" = "5" # SSD PCIEx4 + register "PcieRpClkReqNumber[11]" = "5" # SSD PCIEx4 + + # Configure USB2 ports + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC + + # Configure USB3 ports + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + + # PL2 override 44W + register "tdp_pl2_override" = "40" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Processor Gaussian Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/30897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e771c48409f79edb1355af6992ba43269b98b8e Gerrit-Change-Number: 30897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange [View Less]

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Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard
by build bot (Jenkins) (Code Review) 26 Jan '19

26 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 ) Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... Patch Set 77: (2 comments) https://review.coreboot.org/#/c/28640/77/src/mainboard/clevo/n130wu/gpio.h File src/mainboard/clevo/n130wu/gpio.h: https://review.coreboot.org/#/c/28640/77/src/mainboard/clevo/n130wu/gpio.h@… PS77, Line 168: /* I2C5_SDA/ISH_I2C2_SDA */ … [View More]

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Change in ...coreboot[master]: mb/clevo/n130wu: Add mainboard
by Felix Singer (Code Review) 26 Jan '19

26 Jan '19

Hello Paul Menzel, Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28640 to look at the new patch set (#77). Change subject: mb/clevo/n130wu: Add mainboard ...................................................................... mb/clevo/n130wu: Add mainboard Devices: - N130WU / N131WU Working: - Compiling - Seabios, iPXE - NVMe, SATA3, booting from SSD … [View More]into Arch Linux - USB2, USB3 - Graphics, mDP, HDMI - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux Works, but needs testing: - Thunderbolt WIP: - Documentation Not working: - EC ACPI Untested: - Virtualization Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A Documentation/mainboard/clevo/index.md A Documentation/mainboard/clevo/n130wu/index.md A Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg M Documentation/mainboard/index.md A src/mainboard/clevo/Kconfig A src/mainboard/clevo/Kconfig.name A src/mainboard/clevo/n130wu/Kconfig A src/mainboard/clevo/n130wu/Kconfig.name A src/mainboard/clevo/n130wu/Makefile.inc A src/mainboard/clevo/n130wu/acpi/ec.asl A src/mainboard/clevo/n130wu/acpi/superio.asl A src/mainboard/clevo/n130wu/acpi_tables.c A src/mainboard/clevo/n130wu/board_info.txt A src/mainboard/clevo/n130wu/devicetree.cb A src/mainboard/clevo/n130wu/dsdt.asl A src/mainboard/clevo/n130wu/gpio.h A src/mainboard/clevo/n130wu/hda_verb.c A src/mainboard/clevo/n130wu/pei_data.c A src/mainboard/clevo/n130wu/pei_data.h A src/mainboard/clevo/n130wu/ramstage.c A src/mainboard/clevo/n130wu/romstage.c A src/mainboard/clevo/n130wu/variants/n13xwu/data.vbt A src/mainboard/clevo/n130wu/variants/n13xwu/overridetree.cb 23 files changed, 933 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28640/77 -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 77 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-MessageType: newpatchset [View Less]

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