Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31097 )
Change subject: src/mb/google/hatch: disable HECI
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31097/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31097/1//COMMIT_MSG@7
PS1, Line 7: disable HECI
Looks like there is bug currently which causes a boot hang if heci is disabled. Shelley just …
[View More]raised a bug here: 123413775
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 )
Change subject: lenovo/x230: introduce FHD variant
......................................................................
Patch Set 6:
> Patch Set 6:
>
> > Patch Set 6:
> >
> > > Patch Set 6:
> > >
> > > > Patch Set 6:
> > > >
> > > > > Patch Set 6:
> > > > >
> > > > > > Patch Set 6: …
[View More]-Code-Review
> > > > > >
> > > > > > > On the device with FHD-mod booting works as well, but graphical output of coreboot, seabios and grub is only visible if an additional external monitor is attached via VGA or DP. The internal FHD panel becomes active as soon as the linux kernel takes over. Right now I am unsure if this is due to misconfiguration on my part or if coreboot/libgfxinit needs to be told to use eDP1 for output on modded devices. Hints for further tests appreciated.
> > > > > >
> > > > > > Can you test revision 5 of the patch? I haven't looked into libgfxinit, so it might be that GFX_GMA_INTERNAL_IS_LVDS is used to determine which backlight interface to use
> > > > >
> > > > > I have tried reversion 5 without success
> > > > > After reading Documentation/gfx/libgfxinit.md I also tried explicitly declaring FX_GMA_INTERNAL_IS_EDP (which should not be necessary since it is the default)
> > > > > I also tried moving DP3 to the top of the list of ports to probe in src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads but that did not change anything either
> > > > >
> > > > > any other ideas?
> > > >
> > > > How did you download revision 5?
> > >
> > > git reset origin/master --hard
> > > git pull
> > > git fetch https://review.coreboot.org/coreboot refs/changes/50/28950/5 && git cherry-pick FETCH_HEAD
> >
> > Right, so this cherry-picks the change on top of current master, which isn't the same than "master patchset 5 was created on". Could you please repeat the test running this command before fetching and cherry-picking?
> >
> > git checkout 034e5e6f
>
> same result. LVDS is disabled and full functionality of FHD-panel in linux (as intended), but no coreboot console output on the FHD-panel during boot until kernel takes over.
Could it be that the backlight is not lighting up? I am a bit out of ideas.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31097 )
Change subject: src/mb/google/hatch: disable HECI
......................................................................
Patch Set 1:
This change is ready for review.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25213 )
Change subject: sdm845: Add USB support on cheza platform
......................................................................
Patch Set 65:
(3 comments)
https://review.coreboot.org/#/c/25213/64/src/mainboard/google/cheza/romstag…
File src/mainboard/google/cheza/romstage.c:
https://review.coreboot.org/#/c/25213/64/src/mainboard/google/cheza/romstag…
PS64, Line 22: these resets
…
[View More] : * off early so they get
> "these resets" here i mean is core+ PHYs resets which is plural here. […]
Oh, right, okay, makes sense.
https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c
File src/soc/qualcomm/sdm845/usb.c:
https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@585
PS64, Line 585: int serdes_tbl_num;
> we can not do this as we have differences in all the regsiter sets(serdes, tx,rx,pcs). […]
Hmmm... okay, crap, I didn't see all those other differences.
Then let's maybe follow a different strategy. Keep the lists separate as you have them right now, but also split up the usb_host_base array into two independent structures, and then write independent entry functions like this:
static struct usb_dwc3_cfg usb_port0 = {
.usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE,
...
};
static struct usb_dwc3_cfg usb_port1 = {
.usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE,
...
};
void reset_usb0(void)
{
reset_usb(&usb_port0, 0);
}
void reset_usb0(void)
{
reset_usb(&usb_port1, 1);
}
void setup_usb0(void)
{
setup_usb(&usb_port0, 0);
}
void setup_usb0(void)
{
setup_usb(&usb_port1, 1);
}
The advantage of this is that it allows the linker to eliminate the port data (including all those tables) for ports that are not being used, so it will at least allow us to save all the port0 stuff on Cheza.
https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@824
PS64, Line 824: USB3_PCS_PHYSTATUS));
> Yes, SW wait untill phystatus become 0. […]
Okay, thanks, just wanted to double-check. ;) I (think I?) don't have access to your programming guide so I can't confirm these independently.
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Hello Patrick Rudolph, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31095
to look at the new patch set (#2).
Change subject: src/soc/intel/cnl/chip.h: Fix preprocessor condition
......................................................................
src/soc/intel/cnl/chip.h: Fix preprocessor condition
Commit dc666f5 (soc/intel/cannonlake: Change in SaGv options) added a
conditional preprocessor directive, but its condition …
[View More]was incorrect.
While we are at it, clean up the comment above a bit.
Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/cannonlake/chip.h
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/31095/2
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Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31081
Change subject: mb/google/sarien: Enable GPIO ACPI pin for Chrome OS
......................................................................
mb/google/sarien: Enable GPIO ACPI pin for Chrome OS
Enable the option to have the Chrome OS ACPI GPIO table use the
GPIO ACPI pin number rather than the pad number. This is necessary
because the OS GPIO driver does not have a contiguous number space
due …
[View More]to https://lore.kernel.org/patchwork/patch/855244
BUG=b:120686247
TEST=pass firmware_WriteProtect test on Sarien
Change-Id: I2d3e17f23884ca27ac8d55f6421565e30dd33d5c
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/mainboard/google/sarien/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31081/1
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index f93910f..d544ca2 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -30,6 +30,7 @@
config CHROMEOS
bool
default y
+ select CHROMEOS_ACPI_GPIO_GENERATE_PIN
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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Hello Paul Menzel, Stefan Reinauer, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/28640
to look at the new patch set (#73).
Change subject: mb/clevo/n130wu: Add mainboard
......................................................................
mb/clevo/n130wu: Add mainboard
Devices:
- N130WU / N131WU
Working:
- Compiling
- Seabios, iPXE
- NVMe, SATA3, booting from SSD …
[View More]into Arch Linux
- USB2, USB3
- Graphics, mDP, HDMI
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
WIP:
- Documentation
Not working:
- EC ACPI
- Thunderbolt
Untested:
- Virtualization
Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
A Documentation/mainboard/clevo/index.md
A Documentation/mainboard/clevo/n130wu/index.md
A Documentation/mainboard/clevo/n130wu/n130wu_overview.jpg
M Documentation/mainboard/index.md
A src/mainboard/clevo/Kconfig
A src/mainboard/clevo/Kconfig.name
A src/mainboard/clevo/n130wu/Kconfig
A src/mainboard/clevo/n130wu/Kconfig.name
A src/mainboard/clevo/n130wu/Makefile.inc
A src/mainboard/clevo/n130wu/acpi/ec.asl
A src/mainboard/clevo/n130wu/acpi/superio.asl
A src/mainboard/clevo/n130wu/acpi_tables.c
A src/mainboard/clevo/n130wu/board_info.txt
A src/mainboard/clevo/n130wu/dsdt.asl
A src/mainboard/clevo/n130wu/gpio.h
A src/mainboard/clevo/n130wu/hda_verb.c
A src/mainboard/clevo/n130wu/pei_data.c
A src/mainboard/clevo/n130wu/pei_data.h
A src/mainboard/clevo/n130wu/ramstage.c
A src/mainboard/clevo/n130wu/romstage.c
A src/mainboard/clevo/n130wu/variants/n13xwu/data.vbt
A src/mainboard/clevo/n130wu/variants/n13xwu/devicetree.cb
22 files changed, 926 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28640/73
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