coreboot-gerrit January 2019

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Change in ...coreboot[master]: soc/intel/cannonlake: Export function to set After G3 state
by Duncan Laurie (Code Review) 25 Jan '19

25 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31056 Change subject: soc/intel/cannonlake: Export function to set After G3 state ...................................................................... soc/intel/cannonlake: Export function to set After G3 state Export the SOC level function to set the After G3 state so it can be changed by the mainboard. The setting will be restored by a normal boot but in some circumstances coreboot wants to ensure that it will be powered up again after a reset. BUG=b:121380403 TEST=update cr50 firmware on sarien and reboot and ensure the host does not power off after the cr50 initiated reset. Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/cannonlake/pmc.c 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31056/1 diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 992e60d..c3957d3 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -162,4 +162,8 @@ #define SCIS_IRQ21 5 #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 + +struct device; +void pmc_set_afterg3(struct device *dev, int s5pwr); + #endif diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 4dabb2e..e111e94 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -30,7 +30,7 @@ * Set which power state system will be after reapplying * the power (from G3 State) */ -static void pmc_set_afterg3(struct device *dev, int s5pwr) +void pmc_set_afterg3(struct device *dev, int s5pwr) { uint8_t reg8; uint8_t *pmcbase = pmc_mmio_regs(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32 Gerrit-Change-Number: 31056 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery
by Duncan Laurie (Code Review) 25 Jan '19

25 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31055 Change subject: soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery ...................................................................... soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery Disabling CpuRatio UPD for FSP will ensure it does not force a hard reset to set the CPU Flex Ratio at boot. This is important in a recovery mode boot where the SOC will lose power and need to set the flex ratio again. Disabling SaGv makes recovery mode training faster and mirrors the setting that was done on Skylake. BUG=b:123305400 TEST=reliably enter recovery mode on sarien Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31055/1 diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 91810e8..ed7ece5 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -20,6 +20,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <vendorcode/google/chromeos/chromeos.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { @@ -54,6 +55,13 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + + /* Disable CPU Flex Ratio and SaGv in recovery mode */ + if (vboot_recovery_mode_enabled()) { + m_cfg->CpuRatio = 0; + m_cfg->SaGv = 0; + } + /* If ISH is enabled, enable ISH elements */ if (!dev) m_cfg->PchIshEnable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73 Gerrit-Change-Number: 31055 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Override GLK usb clock gating register
by John Zhao (Code Review) 25 Jan '19

25 Jan '19

Hello John Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30918 to review the following change. Change subject: soc/intel/apollolake: Override GLK usb clock gating register ...................................................................... soc/intel/apollolake: Override GLK usb clock gating register It was observed system suspend/resume failure while running RunInDozingStress. Apply correct GLK usb clock gating register value to mitigate the failure. BRANCH=octopus BUG=b:120526309 TEST=Verified GLK clock gating register value after booting to kernel. Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30918/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b38265f..ad98f5f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -60,6 +60,8 @@ #define DRD_MODE_MASK (1 << 29) #define DRD_MODE_HOST (1 << 29) +#define CFG_XHCLKGTEN 0x8650 + const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -733,6 +735,11 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) { + uint32_t *cfg; + const struct resource *res; + uint32_t reg; + struct device *xhci_dev = PCH_DEV_XHCI; + if (phase == END_OF_FIRMWARE) { /* @@ -758,6 +765,18 @@ */ if (check_xdci_enable()) configure_xhci_host_mode_port0(); + + /* + * Override GLK clock gating register(XHCLKGTEN) to mitigate + * usb device suspend and resume failure. + */ + if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + { + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN); + reg = 0x0FCE6E5F; + write32(cfg, reg); + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747 Gerrit-Change-Number: 30918 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Aleena/Kasumi: Add support Synaptics touch pad for Aleena/Kasumi
by Lucas Chen (Code Review) 25 Jan '19

25 Jan '19

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31064 Change subject: Aleena/Kasumi: Add support Synaptics touch pad for Aleena/Kasumi ...................................................................... Aleena/Kasumi: Add support Synaptics touch pad for Aleena/Kasumi Add support Synaptics touch pad for Aleena/Kasumi. BUG=b:122549449 BRANCH=master TEST= Check if synaptics touch pad working in ChromeOS. Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31064/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index fd807c4..c55bb8b 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -138,8 +138,18 @@ register "desc" = ""ELAN Touchpad"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "wake" = "7" + register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end device mmio 0xfedc5000 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/31064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee Gerrit-Change-Number: 31064 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: Show "Add gigabit ethernet firmware" only for boards...
by Jan Tatje (Code Review) 25 Jan '19

25 Jan '19

Jan Tatje has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30790 Change subject: sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that need it ...................................................................... sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that need it Hide "Add gigabit ethernet firmware" option for boards that do not use GbE firmware in GbE section. The option is now hidden by default and can be reenabled on a per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the mainboards Kconfig. The following boards seem to use this: mb/siemens/mc_bdx1 mb/roda/rv11 mb/ocp/wedge100s mb/ocp/monolake mb/lenovo/x230 mb/lenovo/x220 mb/lenovo/x201 mb/lenovo/x200 mb/lenovo/t530 mb/lenovo/t520 mb/lenovo/t430s mb/lenovo/t430 mb/lenovo/t420s mb/lenovo/t420 mb/lenovo/t400 mb/kontron/ktqm77 mb/intel/saddlebrook mb/intel/kblrvp mb/intel/dg43gt mb/intel/dcp847ske mb/intel/coffeelake_rvp mb/intel/camelbackmountain_fsp mb/hp/revolve_810_g1 mb/hp/folio_9470m mb/hp/compaq_8200_elite_sff mb/hp/8770w mb/hp/8470p mb/hp/8460p mb/hp/2760p mb/hp/2570p mb/google/sarien mb/facebook/watson mb/compulab/intense_pc mb/asus/maximus_iv_gene-z The boards were identified by looking at devicetree.cb, but this list is possibly still incomplete. Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79 Signed-off-by: Jan Tatje <jan(a)jnt.io> --- M src/mainboard/asus/maximus_iv_gene-z/Kconfig M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/facebook/watson/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/hp/2570p/Kconfig M src/mainboard/hp/2760p/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8470p/Kconfig M src/mainboard/hp/8770w/Kconfig M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/folio_9470m/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/intel/camelbackmountain_fsp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/dcp847ske/Kconfig M src/mainboard/intel/dg43gt/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/kontron/ktqm77/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/roda/rv11/Kconfig M src/mainboard/siemens/mc_bdx1/Kconfig M src/southbridge/intel/common/firmware/Kconfig 35 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30790/1 diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig index c6e0dce..8258f2f 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -33,6 +33,7 @@ select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_NUVOTON_NCT6776 select USE_NATIVE_RAMINIT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index fccfb86..d7a6578 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -15,6 +15,7 @@ select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT select SUPERIO_SMSC_SIO1007 + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig index 9771407..00bdbea 100644 --- a/src/mainboard/facebook/watson/Kconfig +++ b/src/mainboard/facebook/watson/Kconfig @@ -8,6 +8,7 @@ select HAVE_OPTION_TABLE select INTEGRATED_UART select SERIRQ_CONTINUOUS_MODE + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 5bf4824..9d72c94 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -23,6 +23,7 @@ select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_SARIEN if BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig index 8cda10c..b1924ca 100644 --- a/src/mainboard/hp/2570p/Kconfig +++ b/src/mainboard/hp/2570p/Kconfig @@ -33,6 +33,7 @@ select GFX_GMA_INTERNAL_IS_LVDS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index 529862e..9da82b2 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -33,6 +33,7 @@ select GFX_GMA_INTERNAL_IS_LVDS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index 57e6268..6c8b8bf 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -36,6 +36,7 @@ select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/hp/8470p/Kconfig b/src/mainboard/hp/8470p/Kconfig index fafa686..aac1be5 100644 --- a/src/mainboard/hp/8470p/Kconfig +++ b/src/mainboard/hp/8470p/Kconfig @@ -34,6 +34,7 @@ select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index 1ab9c60..ecfcb98 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -32,6 +32,7 @@ select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index 48132a8..4d99c64 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -18,6 +18,7 @@ select SUPERIO_NUVOTON_NPCD378 select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index eaeebdb..1d64002 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -19,6 +19,7 @@ select HAVE_CMOS_DEFAULT select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index 81f5d39..ac23213 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -21,6 +21,7 @@ select HAVE_CMOS_DEFAULT select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig b/src/mainboard/intel/camelbackmountain_fsp/Kconfig index 295091f..2829b84 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig +++ b/src/mainboard/intel/camelbackmountain_fsp/Kconfig @@ -10,6 +10,7 @@ select INTEGRATED_UART if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 9474c51..baf80a1 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -17,6 +17,7 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_INTEL_COFFEELAKE_RVPU config MAINBOARD_DIR string diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index 0086bb7..e0988d4 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -12,6 +12,7 @@ select SERIRQ_CONTINUOUS_MODE select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION menu "Debugging" diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index 6438f4c..341baaa 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -34,6 +34,7 @@ select DRIVERS_I2C_CK505 select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION config VGA_BIOS_ID string diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 5fa7817..35a2b6c 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_KBLRVP8 config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index c8113d2..77c23a5 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -31,6 +31,7 @@ select SUPERIO_NUVOTON_NCT6776_COM_A select SADDLEBROOK_USES_FSP1_1 select HAVE_CMOS_DEFAULT + select MAINBOARD_USES_IFD_GBE_REGION config SADDLEBROOK_USES_FSP1_1 bool "FSP driver 1.1" diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index eddca02..75e3db9 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_ANALOG_I2C_HDMI_B select GFX_GMA_INTERNAL_IS_LVDS + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index fb13276..3fc2d03 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -24,6 +24,7 @@ select SUPERIO_NSC_PC87384 select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 696558c..d366cfa 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -24,6 +24,7 @@ select GFX_GMA_INTERNAL_IS_LVDS select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 0f9a957..44e3b4e 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -21,6 +21,7 @@ select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7272d53..14957ac 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -25,6 +25,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 22af597..2f0d839 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS if BOARD_LENOVO_T430S select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 6bc5884..90fd567 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -20,6 +20,7 @@ select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT if BOARD_LENOVO_T520 + select MAINBOARD_USES_IFD_GBE_REGION # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b5c4048..ede4b39 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -21,6 +21,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 32184b3..42a1af2 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -22,6 +22,7 @@ select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index ace5495..ca2556e 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -20,6 +20,7 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 068cf9b..0839c09 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 524d4d3..227fea1 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -23,6 +23,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 09678c7..76ecb48 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -10,6 +10,7 @@ select INTEGRATED_UART if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index df6c57e..854da55 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -15,6 +15,7 @@ select ENABLE_FSP_FAST_BOOT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig index 33994c3..9a0da9c 100644 --- a/src/mainboard/roda/rv11/Kconfig +++ b/src/mainboard/roda/rv11/Kconfig @@ -14,6 +14,7 @@ select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT select SUPERIO_ITE_IT8783EF if BOARD_RODA_RW11 + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index 667a6ee..9de7895 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -14,6 +14,7 @@ select DRIVER_SIEMENS_NC_FPGA select DRIVERS_I2C_RX6110SA select DRIVERS_I2C_PCA9538 + select MAINBOARD_USES_IFD_GBE_REGION config MAINBOARD_DIR string diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 8891c61..ba54fcd 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -107,9 +107,12 @@ depends on USE_ME_CLEANER default "-S" +config MAINBOARD_USES_IFD_GBE_REGION + def_bool n + config HAVE_GBE_BIN bool "Add gigabit ethernet firmware" - depends on HAVE_IFD_BIN + depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_GBE_REGION help The integrated gigabit ethernet controller needs a firmware file. Select this if you are going to use the PCH integrated controller -- To view, visit https://review.coreboot.org/c/coreboot/+/30790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79 Gerrit-Change-Number: 30790 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-MessageType: newchange

4 15

Change in ...coreboot[master]: mb/kontron/986lcd-m: Use pcidev_on_root()
by HAOUAS Elyes (Code Review) 25 Jan '19

25 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31051 Change subject: mb/kontron/986lcd-m: Use pcidev_on_root() ...................................................................... mb/kontron/986lcd-m: Use pcidev_on_root() Change-Id: I61b3e5c92830f02d61a108dadde25ff261099e57 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/986lcd-m/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31051/1 diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index d0d6c6b..73d5997 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -173,7 +173,7 @@ if (!ethernet_disable) continue; printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i); - dev = dev_find_slot(0, PCI_DEVFN(28, i - 1)); + dev = pcidev_on_root(28, i - 1); if (dev == NULL) { printk(BIOS_ERR, "Disabling Ethernet NIC: Cannot find 00:1c.%d!\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/31051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61b3e5c92830f02d61a108dadde25ff261099e57 Gerrit-Change-Number: 31051 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
by Nico Huber (Code Review) 25 Jan '19

25 Jan '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29668 ) Change subject: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU ...................................................................... nb/intel/sandybridge/acpi: Add RMRR entry for iGPU The iGPU always needs access to its stolen memory. For proper IOMMU support, we have to make the OS aware of that. Directly below TOLUD lies the data stolen memory (BDSM) followed by the GTT stolen memory (BGSM), the iGPU needs access to both. Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/29668 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/acpi.c 1 file changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index c7914a0..48be666 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -17,6 +17,7 @@ #include <types.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> @@ -66,16 +67,42 @@ return current; } +static unsigned long acpi_create_igfx_rmrr(const unsigned long current) +{ + const u32 base_mask = ~(u32)(MiB - 1); + + struct device *const host = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!host) + return 0; + + const u32 bgsm = pci_read_config32(host, BGSM) & base_mask; + const u32 tolud = pci_read_config32(host, TOLUD) & base_mask; + if (!bgsm || !tolud) + return 0; + + return acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); +} + static unsigned long acpi_fill_dmar(unsigned long current) { const struct device *const igfx = pcidev_on_root(2, 0); if (igfx && igfx->enabled) { - const unsigned long tmp = current; + unsigned long tmp; + + tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); + + tmp = current; + current += acpi_create_igfx_rmrr(current); + if (current != tmp) { + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + current += acpi_create_dmar_ds_pci(current, 0, 2, 1); + acpi_dmar_rmrr_fixup(tmp, current); + } } const unsigned long tmp = current; -- To view, visit https://review.coreboot.org/c/coreboot/+/29668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Gerrit-Change-Number: 29668 Gerrit-PatchSet: 10 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
by Patrick Rudolph (Code Review) 25 Jan '19

25 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29668 ) Change subject: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Gerrit-Change-Number: 29668 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 25 Jan 2019 07:50:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: sdm845: Add USB support on cheza platform
by Chandana Kishori Chiluveru (Code Review) 25 Jan '19

25 Jan '19

Chandana Kishori Chiluveru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25213 ) Change subject: sdm845: Add USB support on cheza platform ...................................................................... Patch Set 65: (7 comments) https://review.coreboot.org/#/c/25213/64/src/mainboard/google/cheza/mainboa… File src/mainboard/google/cheza/mainboard.c: https://review.coreboot.org/#/c/25213/64/src/mainboard/google/cheza/mainboa… PS64, Line 30: /* Setting up Secondary USB DWC3 controller. */ > nit: maybe mention that the primary isn't needed here because it's only used for DP on Cheza? Ok i will modify this as below /* * Primary USB is used only for DP functionality on cheza platform. * Hence Setting up only Secondary USB DWC3 controller. */ https://review.coreboot.org/#/c/25213/64/src/mainboard/google/cheza/romstag… File src/mainboard/google/cheza/romstage.c: https://review.coreboot.org/#/c/25213/64/src/mainboard/google/cheza/romstag… PS64, Line 22: these resets : * off early so they get > nit: singular now "these resets" here i mean is core+ PHYs resets which is plural here. reset_usb() on usb.c driver takes care of all the resets(usb core+qub phy+qmp phy) required for usb. >>>> /* Assert Core reset */ clock_reset_bcr(dwc3->usb3_bcr, 1); /* Assert QUSB PHY reset */ clock_reset_bcr(dwc3->qusb2phy_bcr, 1); /* Assert QMP PHY reset */ clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c File src/soc/qualcomm/sdm845/usb.c: https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@359 PS64, Line 359: static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { > Okay, this is too much duplication. […] for phy initialization order should be important. we can not change the sequence in SW which is suggested in HPG. if you remember the ss change which i pushed separatly i used the same logic which you suggested here https://review.coreboot.org/c/coreboot/+/29200/6/src/soc/qualcomm/sdm845/us… static void qcom_qmp_phy_configure(void *base, const struct qmp_phy_init_tbl tbl[], int num) { int i; const struct qmp_phy_init_tbl *t = tbl; if (!t) return; for (i = 0; i < num; i++, t++) write32(base + t->offset, t->val); } static void ss_qmp_uni_phy_init(struct usb_dwc3_cfg *dwc3) { struct stopwatch sw; void *phy_base = dwc3->qmp_phy_base; /* power up USB3 PHY */ write32(phy_base + USB3_UNI_POWER_DOWN_CONTROL, 0x01); /* Serdes configuration */ qcom_qmp_phy_configure(&dwc3->qmp_phy_base->usb3_uniphy_qmp_pll_reg, dwc3->serdes_tbl, dwc3->serdes_tbl_num); /* Tx, Rx, and PCS configurations */ qcom_qmp_phy_configure(&dwc3->qmp_phy_base->usb3_uniphy_qmp_tx, dwc3->tx_tbl, dwc3->tx_tbl_num); qcom_qmp_phy_configure(&dwc3->qmp_phy_base->usb3_uniphy_qmp_rx, dwc3->rx_tbl, dwc3->rx_tbl_num); qcom_qmp_phy_configure(&dwc3->qmp_phy_base->usb3_uniphy_qmp_pcs, dwc3->pcs_tbl, dwc3->pcs_tbl_num); /* perform software reset of PCS/Serdes */ write32(phy_base + USB3_UNI_SW_RESET, 0x00); /* start PCS/Serdes to operation mode */ write32(phy_base + USB3_UNI_START, 0x03); I did these changes again to make use of registers from the structures. https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@467 PS64, Line 467: usb3_uniphy > nit: it's a little confusing that these structs are all called "usb3" and "usb3_uniphy"... […] Here usb_uniphy is uniphy which is used for secondary port. USB3 phy is primay phy( USB+DP phy). we can use this macro directly to search the registers related to the phy qmp in HPG document for SW programming. https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@585 PS64, Line 585: int serdes_tbl_num; > Only one table (the first one with the differences) needs to remain here if you combine them as ment […] we can not do this as we have differences in all the regsiter sets(serdes, tx,rx,pcs). below are the differences for q phys {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, {&qserdes_com_reg_layout->com_cmn_config, 0x16}, {&uniphy_qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x04}, {&uniphy_qserdes_com_reg_layout->com_cmn_config, 0x06}, {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, {&uniphy_qserdes_tx_reg_layout->tx_lane_mode_1, 0xc6}, {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x06}, {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, {&uniphy_qserdes_rx_reg_layout->rx_vga_cal_ctrl2, 0x0c}, {&uniphy_qserdes_rx_reg_layout->rx_rx_mode_00, 0x50}, {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0e}, {&uniphy_qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x1c}, {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, {&uniphy_pcs_reg_layout->pcs_txmgn_v2, 0xb5}, {&uniphy_pcs_reg_layout->pcs_txmgn_v3, 0x4c}, {&uniphy_pcs_reg_layout->pcs_txmgn_v4, 0x64}, {&uniphy_pcs_reg_layout->pcs_txmgn_ls, 0x6a} {&uniphy_pcs_reg_layout->pcs_refgen_req_config1, 0x21}, {&uniphy_pcs_reg_layout->pcs_refgen_req_config2, 0x60}, https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@782 PS64, Line 782: ! > Wait, just to double-check: are we waiting for the bit to become 1 or 0? wait_us() waits for the con […] I have checked this and as you said we need to check vstatus bit to become 1. i will correct it. HPG DOC: QUSB2PHY_DEBUG_STAT5 wait for 88 uS for PLL lock; vstatus[0] changes from 0 to 1 I will the comment like below for this /* DEBUG_STAT5: wait for 160uS for PLL lock; vstatus[0] changes from 0 to 1 */ long lock_us = wait_us(160, (read32(&dwc3->qusb_phy_dig->debug_stat5) & VSTATUS_PLL_LOCK_STATUS_MASK)); if (!lock_us) printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); else printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", lock_us); https://review.coreboot.org/#/c/25213/64/src/soc/qualcomm/sdm845/usb.c@824 PS64, Line 824: USB3_PCS_PHYSTATUS)); > Again, this waits for PHYSTATUS to become 0, please make sure that's actually what you mean. Yes, SW wait untill phystatus become 0. you can refer the Software programming guide shared for phy init sequences. Read PCS_PCS_STATUS This can be done either of the two ways: 1) Finite delay can be added before observing PHYSTATUS = 1’b0 2) SW can continuously poll for PHYSTATUS = 1’b0 I will add this info as comment below /* Wait for PHY initialization to be done * PCS_STATUS: wait for 1ms for PHY STATUS; * SW can continuously check for PHYSTATUS = 1.b0 */ long lock_us = wait_us(1000, !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & USB3_PCS_PHYSTATUS)); -- To view, visit https://review.coreboot.org/c/coreboot/+/25213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc Gerrit-Change-Number: 25213 Gerrit-PatchSet: 65 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Ciluveru chandana kishori <cchiluve(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Chandana Kishori Chiluveru <cchiluve(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Fri, 25 Jan 2019 05:45:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by Xiang Wang (Code Review) 25 Jan '19

25 Jan '19

Hello ron minnich, Shawn C, Jonathan Neuschäfer, Paul Menzel, build bot (Jenkins), Philipp Hug, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29494 to look at the new patch set (#30). Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... riscv: add support to select the privilege level of the payload running Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/arch/riscv/include/arch/boot.h D src/arch/riscv/payload.S A src/arch/riscv/payload.c 6 files changed, 83 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29494/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 30 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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