coreboot-gerrit January 2019

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Change in ...coreboot[master]: qcs405 [temp]: Combine BB with QC-Sec for ROM boot
by Patrick Georgi (Code Review) 25 Jan '19

25 Jan '19

Patrick Georgi has uploaded a new patch set (#10) to the change originally created by nsekar(a)codeaurora.org. ( https://review.coreboot.org/c/coreboot/+/29973 ) Change subject: qcs405 [temp]: Combine BB with QC-Sec for ROM boot ...................................................................... qcs405 [temp]: Combine BB with QC-Sec for ROM boot Some of the changes in this patch are part of the SDM845 upstream patches. Those will be needed until the sdm845 patches are merged. After that the remaining delta would have to be patched out and pushed separately. TEST=build & run Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/arch/arm64/armv8/cpu.S M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq40xx/mbn_header.h M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/mbn_header.h M src/soc/qualcomm/sdm845/Makefile.inc R util/qualcomm/createxbl.py M util/qualcomm/description.md R util/qualcomm/ipqheader.py R util/qualcomm/mbn_tools.py R util/qualcomm/mbncat.py A util/qualcomm/qgpt.py M util/qualcomm/scripts/cmm/debug_cb_405.cmm M util/qualcomm/scripts/cmm/debug_cb_845.cmm M util/qualcomm/scripts/cmm/debug_cb_common.cmm M util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm 16 files changed, 446 insertions(+), 187 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29973/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/29973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4d92214cdc7ec06e90b0c7e73c11b6d6deddb9 Gerrit-Change-Number: 29973 Gerrit-PatchSet: 10 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Combine BB with QC-Sec for ROM boot
by Patrick Georgi (Code Review) 25 Jan '19

25 Jan '19

Patrick Georgi has uploaded a new patch set (#9) to the change originally created by nsekar(a)codeaurora.org. ( https://review.coreboot.org/c/coreboot/+/29958 ) Change subject: qcs405: Combine BB with QC-Sec for ROM boot ...................................................................... qcs405: Combine BB with QC-Sec for ROM boot TEST=build & run Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/29958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Gerrit-Change-Number: 29958 Gerrit-PatchSet: 9 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/lenovo/x131e: remove PMH7
by James (Code Review) 25 Jan '19

25 Jan '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31065 Change subject: mb/lenovo/x131e: remove PMH7 ...................................................................... mb/lenovo/x131e: remove PMH7 This board does not have PMH7. Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x131e/devicetree.cb 2 files changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31065/1 diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index 2a58020..946b945 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -7,7 +7,6 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 - select EC_LENOVO_PMH7 select EC_LENOVO_H8 select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index ccdff7c..4adc94b 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -92,18 +92,12 @@ device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge - chip ec/lenovo/pmh7 - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x00" - device pnp ff.1 on end # dummy - end - chip drivers/pc80/tpm device pnp 0c31.0 on end end chip ec/lenovo/h8 - device pnp ff.2 on # dummy + device pnp ff.1 on # dummy io 0x60 = 0x62 io 0x62 = 0x66 io 0x64 = 0x1600 -- To view, visit https://review.coreboot.org/c/coreboot/+/31065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4 Gerrit-Change-Number: 31065 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...em100[master]: em100: Add ability to update spi flash with given start address.
by Peter Tsung Ho Wu (Code Review) 25 Jan '19

25 Jan '19

Peter Tsung Ho Wu has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/30938 Change subject: em100: Add ability to update spi flash with given start address. ...................................................................... em100: Add ability to update spi flash with given start address. Add an option to load file to a given start address in the spi flash and keep the rest of content unchanged. Change-Id: I645db8155d32a3832d99840886d68e4522b66bdb --- M em100.c 1 file changed, 36 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/38/30938/1 diff --git a/em100.c b/em100.c index 4673266..64a4ab2 100644 --- a/em100.c +++ b/em100.c @@ -515,6 +515,7 @@ static const struct option longopts[] = { {"set", 1, 0, 'c'}, {"download", 1, 0, 'd'}, + {"start-address", 1, 0, 'a'}, {"start", 0, 0, 'r'}, {"stop", 0, 0, 's'}, {"verify", 0, 0, 'v'}, @@ -540,7 +541,8 @@ "\nUsage:\n" " -c|--set CHIP: select chip emulation\n" " -d|--download FILE: download FILE into EM100pro\n" - " -u|--upload FILE: upload from EM100pro into FILE\n" + " -a|--start address: only works with -d (E.g. -d file.bin -a 0x300000)\n" + " -u|--upload FILE: upload from EM100pro into FILE\n" " -r|--start: em100 shall run\n" " -s|--stop: em100 shall stop\n" " -v|--verify: verify EM100 content matches the file\n" @@ -576,8 +578,9 @@ int firmware_is_dpfw = 0; unsigned int serial_number = 0; unsigned long address_offset = 0; + unsigned long spi_start_address = 0; - while ((opt = getopt_long(argc, argv, "c:d:u:rsvtO:F:f:g:S:p:Dx:lhT", + while ((opt = getopt_long(argc, argv, "c:d:a:u:rsvtO:F:f:g:S:p:Dx:lhT", longopts, &idx)) != -1) { switch (opt) { case 'c': @@ -587,6 +590,10 @@ filename = optarg; /* TODO: check that file exists */ break; + case 'a': + sscanf(optarg, "%lx", &spi_start_address); + printf("Spi address: 0x%08lx\n", spi_start_address); + break; case 'u': read_filename = optarg; break; @@ -775,8 +782,11 @@ } if (filename) { - int maxlen = 0x4000000; /* largest size - 64MB */ + int maxlen = desiredchip ? chip->size : 0x4000000; /* largest size - 64MB */ void *data = malloc(maxlen); + int done; + void *readback = NULL; + if (data == NULL) { printf("FATAL: couldn't allocate memory\n"); return 1; @@ -808,15 +818,34 @@ return 1; } - write_sdram(&em100, (unsigned char *)data, 0x00000000, length); + if (desiredchip && (length != (chip->size - spi_start_address)) ) + { + printf("FATAL: file size does not match to chip size.\n"); + free(data); + return 1; + } + + if (spi_start_address) { + readback = malloc(maxlen); + if (data == NULL) { + printf("FATAL: couldn't allocate memory(size: %x)\n", maxlen); + return 1; + } + done = read_sdram(&em100, readback, 0, maxlen); + memcpy((unsigned char*)readback + spi_start_address, data, length); + write_sdram(&em100, (unsigned char*)readback, 0x00000000, maxlen); + free(readback); + } else { + write_sdram(&em100, (unsigned char*)data, 0x00000000, length); + } + if (verify) { - int done; - void *readback = malloc(length); + readback = malloc(length); if (data == NULL) { printf("FATAL: couldn't allocate memory\n"); return 1; } - done = read_sdram(&em100, readback, 0x00000000, length); + done = read_sdram(&em100, readback, spi_start_address, length); if (done && (memcmp(data, readback, length) == 0)) printf("Verify: PASS\n"); else -- To view, visit https://review.coreboot.org/c/em100/+/30938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I645db8155d32a3832d99840886d68e4522b66bdb Gerrit-Change-Number: 30938 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 25 Jan '19

25 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 25: (2 comments) https://review.coreboot.org/#/c/29563/25/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/25/src/include/memlayout.h@168 PS25, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/25/src/include/memlayout.h@168 PS25, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 25 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 25 Jan 2019 12:07:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/superiotool: detect Fintek F81866, F8196*
by Kyle Stevenson (Code Review) 25 Jan '19

25 Jan '19

Kyle Stevenson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31052 Change subject: util/superiotool: detect Fintek F81866, F8196* ...................................................................... util/superiotool: detect Fintek F81866, F8196* Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39 Signed-off-by: Kyle Stevenson <kstevenson(a)comqi.com> --- M util/superiotool/fintek.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31052/1 diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index 74e7f76..347462e 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -467,6 +467,10 @@ {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}}, {EOT}}}, + {0x1010, "F81866", { + {EOT}}}, + {0x0215, "F81962/F81964/F81966/F81967", { + {EOT}}}, {EOT} }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39 Gerrit-Change-Number: 31052 Gerrit-PatchSet: 1 Gerrit-Owner: Kyle Stevenson <kstevenson(a)comqi.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/denverton_ns: Enable ACPI using intelblock
by Patrick Georgi (Code Review) 25 Jan '19

25 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25428 ) Change subject: soc/intel/denverton_ns: Enable ACPI using intelblock ...................................................................... soc/intel/denverton_ns: Enable ACPI using intelblock - Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/harcuvar/fadt.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h 11 files changed, 96 insertions(+), 172 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 92cf5a2..c0e830d 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <cpu/x86/msr.h> +#include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -41,17 +42,3 @@ /* TPM Present */ gnvs->tpmp = 0; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, - IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index 9f41f64..e33adde 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -21,30 +21,8 @@ #include <soc/acpi.h> #include <soc/soc_util.h> -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +void motherboard_fill_fadt(acpi_fadt_t *fadt) { - acpi_header_t *header = &(fadt->header); - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy_s(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy_s(header->oem_id, OEM_ID, 6); - memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy_s(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long)facs; - fadt->dsdt = (unsigned long)dsdt; fadt->model = 1; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *)fadt, header->length); } diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 92cf5a2..c0e830d 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <cpu/x86/msr.h> +#include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -41,17 +42,3 @@ /* TPM Present */ gnvs->tpmp = 0; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, - IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index 9f41f64..6259c2d 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -3,6 +3,7 @@ * * Copyright (C) 2007 - 2009 coresystems GmbH * Copyright (C) 2014 - 2017 Intel Corporation. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,30 +22,8 @@ #include <soc/acpi.h> #include <soc/soc_util.h> -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +void motherboard_fill_fadt(acpi_fadt_t *fadt) { - acpi_header_t *header = &(fadt->header); - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy_s(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy_s(header->oem_id, OEM_ID, 6); - memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy_s(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long)facs; - fadt->dsdt = (unsigned long)dsdt; fadt->model = 1; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = acpi_checksum((void *)fadt, header->length); } diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 21d877b..5a1cc81 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -31,7 +31,7 @@ #include <soc/nvs.h> #include <soc/pm.h> -unsigned long acpi_fill_mcfg(unsigned long current) +__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ current += acpi_create_mcfg_mmconfig((void *)current, @@ -180,6 +180,7 @@ return generic_pm1_en; } +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* * Save wake source information for calculating ACPI _SWS values * @@ -218,6 +219,7 @@ return GPE0_REG_MAX; } +#endif __weak void acpi_create_gnvs(struct global_nvs_t *gnvs) { diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index e34e4d1..273ce30 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -43,8 +43,10 @@ select PCR_COMMON_IOSF_1_0 select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE + select COMMON_FADT select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 5fd56b6..c7eb931 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -4,6 +4,7 @@ * Copyright (C) 2007 - 2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2014 - 2017 Intel Corporation. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,54 @@ #include <device/pci.h> #include <cbmem.h> +#include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/soc_util.h> #include <soc/pmc.h> #include <soc/systemagent.h> +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 2, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 10, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, + ACPI_BASE_ADDRESS + 0x14), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, + ACPI_BASE_ADDRESS + 0x15), + } +}; + void acpi_init_gnvs(global_nvs_t *gnvs) { /* CPU core count */ @@ -53,36 +96,20 @@ gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory()); } -static int acpi_sci_irq(void) +uint32_t soc_read_sci_irq_select(void) { - int scis, sci_irq; struct device *dev = get_pmc_dev(); if (!dev) return 0; - /* Determine how SCI is routed. */ - scis = pci_read_config32(dev, PMC_ACPI_CNT) & PMC_ACPI_CNT_SCIS_MASK; - switch (scis) { - case PMC_ACPI_CNT_SCIS_IRQ9: - case PMC_ACPI_CNT_SCIS_IRQ10: - case PMC_ACPI_CNT_SCIS_IRQ11: - sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ9 + 9; - break; - case PMC_ACPI_CNT_SCIS_IRQ20: - case PMC_ACPI_CNT_SCIS_IRQ21: - case PMC_ACPI_CNT_SCIS_IRQ22: - case PMC_ACPI_CNT_SCIS_IRQ23: - sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } + return pci_read_config32(dev, PMC_ACPI_CNT); +} - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return cstate_map; } unsigned long acpi_fill_mcfg(unsigned long current) @@ -103,38 +130,27 @@ return current; } -void acpi_fill_in_fadt(acpi_fadt_t *fadt) +__attribute__ ((weak)) void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ +} + +void soc_fill_fadt(acpi_fadt_t *fadt) { u16 pmbase = get_pmbase(); /* System Management */ - fadt->sci_int = acpi_sci_irq(); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; -#else - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; -#endif + if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + fadt->smi_cmd = 0x00; + fadt->acpi_enable = 0x00; + fadt->acpi_disable = 0x00; + } /* Power Control */ - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD); fadt->gpe1_blk = 0; /* Control Registers - Length */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; @@ -228,59 +244,16 @@ fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; fadt->x_gpe1_blk.addrh = 0x00; + + motherboard_fill_fadt(fadt); } -void generate_cpu_entries(struct device *device) +int soc_madt_sci_irq_polarity(int sci) { - int core; - int pcontrol_blk = get_pmbase(), plen = 6; - int num_cpus = get_cpu_count(); - - for (core = 0; core < num_cpus; core++) { - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor(core, pcontrol_blk, plen); - - /* Generate P-state tables */ - - /* Generate C-state tables */ - - /* Generate T-state tables */ - - acpigen_pop_len(); - } - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, num_cpus); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(num_cpus); -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci_irq = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (acpi_madt_irqoverride_t *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; + if (sci >= 20) + return MP_IRQ_POLARITY_LOW; else - sci_flags |= MP_IRQ_POLARITY_HIGH; - - irqovr = (acpi_madt_irqoverride_t *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, (u8)sci_irq, sci_irq, - sci_flags); - - return current; + return MP_IRQ_POLARITY_HIGH; } unsigned long southcluster_write_acpi_tables(struct device *device, diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 14eb167..5de58ea 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -23,12 +23,12 @@ void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(struct device *device); +void motherboard_fill_fadt(acpi_fadt_t *fadt); #endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index cf10823..5a94b24 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -19,7 +19,7 @@ #ifndef _DENVERTON_NS_NVS_H_ #define _DENVERTON_NS_NVS_H_ -typedef struct { +typedef struct global_nvs_t { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -63,9 +63,8 @@ u32 tsegl; /* 0x58 - TSEG Length/Size */ u8 rsvd3[164]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; -void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 32d8a76..09ce158 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -24,6 +24,12 @@ #define GPE_MAX 127 +/* P-state configuration */ +#define PSS_MAX_ENTRIES 15 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 4db3981..f5df21a 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -38,6 +38,17 @@ #define PMC_ACPI_CNT_SCIS_IRQ21 0x05 #define PMC_ACPI_CNT_SCIS_IRQ22 0x06 #define PMC_ACPI_CNT_SCIS_IRQ23 0x07 + +#define SCI_IRQ_ADJUST 0 +#define SCI_IRQ_SEL (0x07 << SCI_IRQ_ADJUST) +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07 + #define PMC_PWRM_BASE 0x48 /* MEM BAR */ #define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */ #define PMC_GEN_PMCON_A 0xA0 -- To view, visit https://review.coreboot.org/c/coreboot/+/25428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Gerrit-Change-Number: 25428 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dg <dg1979ie(a)yahoo.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/google/octopus: Override emmc DLL values for Ampton
by Kane Chen (Code Review) 25 Jan '19

25 Jan '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31048 Change subject: mb/google/octopus: Override emmc DLL values for Ampton ...................................................................... mb/google/octopus: Override emmc DLL values for Ampton New emmc DLL values for Ampton BUG=b:122307153 TEST=Boot to OS on 5 systems Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/octopus/variants/ampton/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31048/1 diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 1b4b9ba..10ff7d7 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0a0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c292929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x001a1c1c" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10026" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/31048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Gerrit-Change-Number: 31048 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/google/sarien: Force power on after cr50 update
by Duncan Laurie (Code Review) 25 Jan '19

25 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31058 Change subject: mb/google/sarien: Force power on after cr50 update ...................................................................... mb/google/sarien: Force power on after cr50 update By default this board is configured to not power up after an EC reset. However in the case of a cr50 firmware update that will reset the EC it will end up powered off. In order to have it stay powered up configure the board to power up. This will get reset to the configured default when it boots again. BUG=b:121380403 TEST=update cr50 firmware and reboot to ensure system boots and does not end up powered off. Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/chromeos.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31058/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 0ea237a..f9e42e0 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -21,6 +21,10 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <soc/pmc.h> +#include <soc/pci_devs.h> enum rec_mode_state { REC_MODE_UNINITIALIZED, @@ -111,3 +115,11 @@ { return 1; } + +void mainboard_cr50_update_reset(void) +{ +#if ENV_RAMSTAGE + /* Ensure system powers up after CR50 reset */ + pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON); +#endif +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8 Gerrit-Change-Number: 31058 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: vendorcode/google/chromeos: Add mainboard hook before cr50 update
by Duncan Laurie (Code Review) 25 Jan '19

25 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31057 Change subject: vendorcode/google/chromeos: Add mainboard hook before cr50 update ...................................................................... vendorcode/google/chromeos: Add mainboard hook before cr50 update In order to allow the mainboard to configure the system before a cr50 initiated update reset add a weak function that the mainboard can override if necessary. This will allow a board that would otherwise be configured to stay off after an EC reset to instead power up after the reset and not end up in a shut down state after a cr50 update. BUG=b:121380403 TEST=update cr50 firmware on sarien and reboot Change-Id: I11f9e8c9bfe810f69b4eaa2c633252c25004cbd0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/cr50_enable_update.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31057/1 diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index df61596..f7e2ae9 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -33,6 +33,9 @@ static inline void reboot_from_watchdog(void) { return; } #endif /* CONFIG_CHROMEOS */ +/* Defined as weak function in cr50_enable_update.c */ +void mainboard_cr50_update_reset(void); + struct romstage_handoff; #include "gnvs.h" diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index 06416bd..da9a16d 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -21,6 +21,9 @@ #include <security/tpm/tss.h> #include <vb2_api.h> #include <security/vboot/vboot_common.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void __weak mainboard_cr50_update_reset(void) {} static void enable_update(void *unused) { @@ -52,6 +55,9 @@ if (!num_restored_headers) return; + /* Give mainboard a chance to take action */ + mainboard_cr50_update_reset(); + elog_add_event(ELOG_TYPE_CR50_UPDATE); /* clear current post code avoid chatty eventlog on subsequent boot*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/31057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11f9e8c9bfe810f69b4eaa2c633252c25004cbd0 Gerrit-Change-Number: 31057 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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