coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

1 participants
1296 discussions

Change in ...coreboot[master]: src/mb/asrock/../g41m-s3: Remove spurious devices
by Angel Pons (Code Review) 24 Jan '19

24 Jan '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31020 Change subject: src/mb/asrock/../g41m-s3: Remove spurious devices ...................................................................... src/mb/asrock/../g41m-s3: Remove spurious devices This fixes errors regarding "PCI: Leftover static devices" Change-Id: Ie45fe6934df4a9dad4c8f6b1af665034853c4c5a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31020/1 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index cdcadba..971eebd7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -33,8 +33,6 @@ device pci 2.0 on # Integrated graphics controller subsystemid 0x1849 0x2e32 end - device pci 3.0 off end # ME - device pci 3.1 off end # ME chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" @@ -140,9 +138,6 @@ device pci 1f.3 on # SMbus subsystemid 0x1849 0x27da end - device pci 1f.4 off end - device pci 1f.5 off end - device pci 1f.6 off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/31020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie45fe6934df4a9dad4c8f6b1af665034853c4c5a Gerrit-Change-Number: 31020 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP, DONOTMERGE: Add inteltool support to dump GPIOs
by Angel Pons (Code Review) 24 Jan '19

24 Jan '19

Angel Pons has restored this change. ( https://review.coreboot.org/c/coreboot/+/29459 ) Change subject: WIP, DONOTMERGE: Add inteltool support to dump GPIOs ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/29459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b0d49a175e656ef88d66c559239cac17e51b880 Gerrit-Change-Number: 29459 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Angel Pons (Code Review) 24 Jan '19

24 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: > Patch Set 6: > > > Patch Set 6: > > > > > Patch Set 6: > > > > > > > Patch Set 6: -Code-Review > > > > > > > > > On the device with FHD-mod booting works as well, but graphical output of coreboot, seabios and grub is only visible if an additional external monitor is attached via VGA or DP. The internal FHD panel becomes active as soon as the linux kernel takes over. Right now I am unsure if this is due to misconfiguration on my part or if coreboot/libgfxinit needs to be told to use eDP1 for output on modded devices. Hints for further tests appreciated. > > > > > > > > Can you test revision 5 of the patch? I haven't looked into libgfxinit, so it might be that GFX_GMA_INTERNAL_IS_LVDS is used to determine which backlight interface to use > > > > > > I have tried reversion 5 without success > > > After reading Documentation/gfx/libgfxinit.md I also tried explicitly declaring FX_GMA_INTERNAL_IS_EDP (which should not be necessary since it is the default) > > > I also tried moving DP3 to the top of the list of ports to probe in src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads but that did not change anything either > > > > > > any other ideas? > > > > How did you download revision 5? > > git reset origin/master --hard > git pull > git fetch https://review.coreboot.org/coreboot refs/changes/50/28950/5 && git cherry-pick FETCH_HEAD Right, so this cherry-picks the change on top of current master, which isn't the same than "master patchset 5 was created on". Could you please repeat the test running this command before fetching and cherry-picking? git checkout 034e5e6f -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 22:09:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco: Turn on wake up from lid
by Duncan Laurie (Code Review) 24 Jan '19

24 Jan '19

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30824 ) Change subject: ec/google/wilco: Turn on wake up from lid ...................................................................... ec/google/wilco: Turn on wake up from lid Send required EC command to enable ACPI S3 wake up from lid switch. BUG=b:120748824 TEST=Put Sarien system into S3 and then wake up from lid switch successful. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30824 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/ec/google/wilco/commands.c M src/ec/google/wilco/commands.h M src/ec/google/wilco/smihandler.c 3 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index c42699d..1c76461 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -158,3 +158,12 @@ radio_control, ARRAY_SIZE(radio_control), NULL, 0); } + +int wilco_ec_change_wake(uint8_t source, enum ec_wake_change change) +{ + uint8_t wake_source[3] = { change, source }; + + return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ACPI_WAKEUP_CHANGE, + wake_source, ARRAY_SIZE(wake_source), + NULL, 0); +} diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 752e19b..53f6d0f 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -38,6 +38,8 @@ KB_EC_INFO = 0x38, /* Set ACPI mode on or off */ KB_ACPI = 0x3a, + /* Change ACPI wake up source */ + KB_ACPI_WAKEUP_CHANGE = 0x4a, /* Manage the EC power button passthru to the host */ KB_POWER_BUTTON_TO_HOST = 0x3e, /* Manage the EC control of speaker mute */ @@ -257,4 +259,25 @@ */ int wilco_ec_get_lid_state(void); +enum ec_wake_change { + WAKE_OFF = 0, + WAKE_ON +}; +/** + * wilco_ec_change_wake_source + * + * Change acpi wake up source. + * @source: Wake up source that can be enabled/disabled. + * @ec_wake_change: On/off switch. + * + * Returns -1 if the EC command failed + */ +int wilco_ec_change_wake(uint8_t source, enum ec_wake_change change); + +enum ec_acpi_wake_events { + EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */ + EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */ + EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */ +}; + #endif /* EC_GOOGLE_WILCO_COMMANDS_H */ diff --git a/src/ec/google/wilco/smihandler.c b/src/ec/google/wilco/smihandler.c index 60ad813..e127434 100644 --- a/src/ec/google/wilco/smihandler.c +++ b/src/ec/google/wilco/smihandler.c @@ -26,6 +26,8 @@ switch (slp_type) { case ACPI_S3: wilco_ec_send_noargs(KB_SAVE); + wilco_ec_change_wake((EC_ACPI_WAKE_PWRB|EC_ACPI_WAKE_LID), + WAKE_ON); wilco_ec_slp_en(); break; case ACPI_S5: -- To view, visit https://review.coreboot.org/c/coreboot/+/30824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Gerrit-Change-Number: 30824 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: ec/google/wilco: Turn on wake up from lid
by Duncan Laurie (Code Review) 24 Jan '19

24 Jan '19

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30824 ) Change subject: ec/google/wilco: Turn on wake up from lid ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Gerrit-Change-Number: 30824 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 22:03:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/*/*/devicetree.cb: Move the ioapic device out of the PCI domain
by Arthur Heymans (Code Review) 24 Jan '19

24 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31041 Change subject: mb/*/*/devicetree.cb: Move the ioapic device out of the PCI domain ...................................................................... mb/*/*/devicetree.cb: Move the ioapic device out of the PCI domain While the ioapic is physically on the southbridge chip, it is not visible in the topology. This fixes spurious lines "child IOAPIC: 02 not a PCI device" and IOAPIC as leftover device. Change-Id: Id8010c84c45f0859508e7564c0eaa501904b7043 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb 3 files changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/31041/1 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 5945869..327104d 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -22,6 +22,15 @@ end end + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "(void *)0xfec00000" + device ioapic 2 on end + end + + register "pci_mmio_size" = "2048" device domain 0 on @@ -76,14 +85,6 @@ register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" - register "enable_virtual_wire" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 2 on end - end - device pci 19.0 on end # LAN device pci 1a.0 on # UHCI subsystemid 0x17aa 0x20f0 diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index b74f25a..49d619f 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -27,6 +27,14 @@ end end + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "(void *)0xfec00000" + device ioapic 2 on end + end + register "pci_mmio_size" = "2048" device domain 0 on @@ -80,14 +88,6 @@ register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" - register "enable_virtual_wire" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 2 on end - end - device pci 19.0 on end # LAN device pci 1a.0 on # UHCI subsystemid 0x17aa 0x20f0 diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 690c2a5..535e476 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -19,6 +19,14 @@ end end + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "(void *)0xfec00000" + device ioapic 2 on end + end + register "pci_mmio_size" = "2048" device domain 0 on @@ -67,14 +75,6 @@ # Maybe we should set less for Mini PCIe. register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" - register "enable_virtual_wire" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 2 on end - end - device pci 19.0 off end # LAN device pci 1a.0 on # UHCI ioapic_irq 2 INTA 0x10 -- To view, visit https://review.coreboot.org/c/coreboot/+/31041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8010c84c45f0859508e7564c0eaa501904b7043 Gerrit-Change-Number: 31041 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/smbios: Add CPU_SOCKET_TYPE
by Nico Huber (Code Review) 24 Jan '19

24 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29529 ) Change subject: arch/x86/smbios: Add CPU_SOCKET_TYPE ...................................................................... Patch Set 10: I like the idea but the changes for AMD are rather irrita- ting. If they followed a different numbering scheme before, this might confuse ppl. So why reuse the existing Kconfig symbol name in the first place? -- To view, visit https://review.coreboot.org/c/coreboot/+/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 24 Jan 2019 21:42:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Kilian Neuner (Code Review) 24 Jan '19

24 Jan '19

Kilian Neuner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: > Patch Set 6: > > > Patch Set 6: > > > > > Patch Set 6: -Code-Review > > > > > > > On the device with FHD-mod booting works as well, but graphical output of coreboot, seabios and grub is only visible if an additional external monitor is attached via VGA or DP. The internal FHD panel becomes active as soon as the linux kernel takes over. Right now I am unsure if this is due to misconfiguration on my part or if coreboot/libgfxinit needs to be told to use eDP1 for output on modded devices. Hints for further tests appreciated. > > > > > > Can you test revision 5 of the patch? I haven't looked into libgfxinit, so it might be that GFX_GMA_INTERNAL_IS_LVDS is used to determine which backlight interface to use > > > > I have tried reversion 5 without success > > After reading Documentation/gfx/libgfxinit.md I also tried explicitly declaring FX_GMA_INTERNAL_IS_EDP (which should not be necessary since it is the default) > > I also tried moving DP3 to the top of the list of ports to probe in src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads but that did not change anything either > > > > any other ideas? > > How did you download revision 5? git reset origin/master --hard git pull git fetch https://review.coreboot.org/coreboot refs/changes/50/28950/5 && git cherry-pick FETCH_HEAD -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 21:36:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add GPIO IRQ APIs
by build bot (Jenkins) (Code Review) 24 Jan '19

24 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30003 ) Change subject: sdm845: Add GPIO IRQ APIs ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/30003/11/src/soc/qualcomm/sdm845/gpio.c File src/soc/qualcomm/sdm845/gpio.c: https://review.coreboot.org/#/c/30003/11/src/soc/qualcomm/sdm845/gpio.c@92 PS11, Line 92: << GPIO_INTR_RAW_STATUS_EN_SHIFT); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/30003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f34e7bba17d9baad1db2bf025ba2db4afdfb58 Gerrit-Change-Number: 30003 Gerrit-PatchSet: 11 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 21:10:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by T.Michael Turney (Code Review) 24 Jan '19

24 Jan '19

Hello mturney mturney, Mukesh Savaliya, Vin Kamath, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27483 to look at the new patch set (#44). Change subject: sdm845: Add SPI QUP driver ...................................................................... sdm845: Add SPI QUP driver This implements the SPI driver for the Qualcomm Universal Peripheral (QUP) core. Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Signed-off-by: Mukesh Savaliya <msavaliy(a)codeaurora.org> Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> --- M src/mainboard/google/cheza/bootblock.c M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/qualcomm/sdm845/bootblock.c M src/soc/qualcomm/sdm845/include/soc/addressmap.h A src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h A src/soc/qualcomm/sdm845/include/soc/spi_qup_qcom.h A src/soc/qualcomm/sdm845/qcom_qup_se.c M src/soc/qualcomm/sdm845/spi.c A src/soc/qualcomm/sdm845/spi_qup.c 9 files changed, 937 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/27483/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 44 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2019