coreboot-gerrit January 2019

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Change in ...coreboot[master]: Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib"
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31071 Change subject: Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib" ...................................................................... Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib" This reverts commit ab1227226ebd78b40783cb200e60711b900352f0. There were significant changes around soc_reset_tco_status() that this code needs to be adapted to. Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c 4 files changed, 184 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31071/1 diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index f6c56cf..32d8a76 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -41,6 +41,18 @@ struct chipset_power_state *fill_power_state(void); /* Power Management Utility Functions. */ +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 344f8b9..ccf0d95 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -19,12 +19,29 @@ #include <arch/io.h> #include <console/console.h> -#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> -const char *const *soc_smi_sts_array(size_t *a) +static void print_num_status_bits(int num_bits, uint32_t status, + const char *const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static uint32_t print_smi_status(uint32_t smi_sts) { static const char *const smi_sts_bits[] = { [2] = "BIOS", @@ -50,11 +67,93 @@ [31] = "LEGACY_USB3", }; - *a = ARRAY_SIZE(smi_sts_bits); - return smi_sts_bits; + if (!smi_sts) + return 0; + + printk(BIOS_DEBUG, "SMI_STS: "); + print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return smi_sts; } -const char *const *soc_tco_sts_array(size_t *a) +static uint32_t reset_smi_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS)); + outl(smi_sts, (uint16_t)(pmbase + SMI_STS)); + return smi_sts; +} + +uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); } + +void enable_smi(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); + smi_en |= mask; + outl(smi_en, (uint16_t)(pmbase + SMI_EN)); +} + +void disable_smi(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); + smi_en &= ~mask; + outl(smi_en, (uint16_t)(pmbase + SMI_EN)); +} + +void enable_pm1_control(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); + pm1_cnt |= mask; + outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); +} + +void disable_pm1_control(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); + pm1_cnt &= ~mask; + outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); +} + +static uint16_t reset_pm1_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS)); + outw(pm1_sts, (uint16_t)(pmbase + PM1_STS)); + return pm1_sts; +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char *const pm1_sts_bits[] = { + [0] = "TMROF", [4] = "BM", [5] = "GBL", + [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_SPEW, "PM1_STS: "); + print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); + printk(BIOS_SPEW, "\n"); + + return pm1_sts; +} + +uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); } + +void enable_pm1(uint16_t events) +{ + uint16_t pmbase = get_pmbase(); + outw(events, (uint16_t)(pmbase + PM1_EN)); +} + +static uint32_t print_tco_status(uint32_t tco_sts) { static const char *const tco_sts_bits[] = { [0] = "NMI2SMI", [1] = "OS_TCO_SMI", @@ -65,11 +164,17 @@ [17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI", }; - *a = ARRAY_SIZE(tco_sts_bits); - return tco_sts_bits; + if (!tco_sts) + return 0; + + printk(BIOS_DEBUG, "TCO_STS: "); + print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return tco_sts; } -uint32_t soc_reset_tco_status(void) +static uint32_t reset_tco_status(void) { uint16_t tcobase = get_tcobase(); uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS)); @@ -79,7 +184,35 @@ return tco_sts & tco_en; } -const char *const *soc_std_gpe_sts_array(size_t *a) +uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); } + +void enable_gpe(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); + gpe0_en |= mask; + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); +} + +void disable_gpe(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); + gpe0_en &= ~mask; + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); +} + +void disable_all_gpe(void) { disable_gpe(~0); } + +static uint32_t reset_gpe_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); + outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); + return gpe_sts; +} + +static uint32_t print_gpe_sts(uint32_t gpe_sts) { static const char *const gpe_sts_bits[] = { [0] = "GPIO_0", [1] = "GPIO_1", @@ -100,8 +233,16 @@ [30] = "GPIO_30", [31] = "GPIO_31", }; - *a = ARRAY_SIZE(gpe_sts_bits); - return gpe_sts_bits; + if (!gpe_sts) + return gpe_sts; + + printk(BIOS_DEBUG, "GPE0a_STS: "); + print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return gpe_sts; } +uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); } + void clear_pmc_status(void) { /* TODO */ } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index e1e7bc4..85f99d7 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -25,7 +25,6 @@ #include <device/pci_def.h> #include <elog.h> #include <intelblocks/fast_spi.h> -#include <intelblocks/pmclib.h> #include <spi-generic.h> #include <soc/iomap.h> #include <soc/soc_util.h> @@ -53,7 +52,7 @@ return 0; } -void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); } +void southbridge_smi_set_eos(void) { enable_smi(EOS); } global_nvs_t *smm_get_gnvs(void) { return gnvs; } @@ -99,7 +98,7 @@ uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ - pmc_disable_smi(SLP_SMI_EN); + disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); @@ -132,7 +131,7 @@ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ - pmc_disable_all_gpe(); + disable_all_gpe(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -146,7 +145,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - pmc_enable_pm1_control(SLP_EN); + enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) @@ -159,7 +158,7 @@ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - pmc_disable_pm1_control(SLP_EN | SLP_TYP); + disable_pm1_control(SLP_EN | SLP_TYP); } } @@ -238,11 +237,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - pmc_disable_pm1_control(SCI_EN); + disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - pmc_enable_pm1_control(SCI_EN); + enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_FINALIZE: @@ -269,23 +268,23 @@ static void southbridge_smi_pm1(void) { - uint16_t pm1_sts = pmc_clear_pm1_status(); + uint16_t pm1_sts = clear_pm1_status(); /* While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { // power button pressed - pmc_disable_pm1_control(-1UL); - pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + disable_pm1_control(-1UL); + enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); } +static void southbridge_smi_gpe0(void) { clear_gpe_status(); } static void southbridge_smi_tco(void) { - uint32_t tco_sts = pmc_clear_tco_status(); + uint32_t tco_sts = clear_tco_status(); /* Any TCO event? */ if (!tco_sts) @@ -355,7 +354,7 @@ /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = pmc_clear_smi_status(); + smi_sts = clear_smi_status(); /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 65d2499..9d3fa75 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -23,7 +23,6 @@ #include <cpu/x86/smm.h> #include <string.h> -#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> @@ -49,10 +48,10 @@ } /* Dump and clear status registers */ - pmc_clear_smi_status(); - pmc_clear_pm1_status(); - pmc_clear_tco_status(); - pmc_clear_all_gpe_status(); + clear_smi_status(); + clear_pm1_status(); + clear_tco_status(); + clear_gpe_status(); clear_pmc_status(); } @@ -61,8 +60,8 @@ printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable pcie wake. */ - pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - pmc_disable_std_gpe(PME_B0_EN); + enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + disable_gpe(PME_B0_EN); /* Enable SMI generation: * - on APMC writes (io 0xb2) @@ -72,7 +71,7 @@ * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -- To view, visit https://review.coreboot.org/c/coreboot/+/31071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889 Gerrit-Change-Number: 31071 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by build bot (Jenkins) (Code Review) 24 Jan '19

24 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/25442/10/src/soc/intel/denverton_ns/lpc.c File src/soc/intel/denverton_ns/lpc.c: https://review.coreboot.org/#/c/25442/10/src/soc/intel/denverton_ns/lpc.c@4… PS10, Line 418: if(!relax_security) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 15:08:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton_ns: Remove soc_reset_tco_status()
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31070 Change subject: soc/intel/denverton_ns: Remove soc_reset_tco_status() ...................................................................... soc/intel/denverton_ns: Remove soc_reset_tco_status() Before commit ab1227226eb landed, that function was obsoleted and now the compiler complains. Change-Id: I1a612e59c81f742dd4ea1a9c02842ddf17341eb0 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/denverton_ns/pmutil.c 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31070/1 diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 344f8b9..e75feb1 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -69,16 +69,6 @@ return tco_sts_bits; } -uint32_t soc_reset_tco_status(void) -{ - uint16_t tcobase = get_tcobase(); - uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS)); - uint32_t tco_en = inl((uint16_t)(tcobase + TCO1_CNT)); - - outl(tco_sts, (uint16_t)(tcobase + TCO1_STS)); - return tco_sts & tco_en; -} - const char *const *soc_std_gpe_sts_array(size_t *a) { static const char *const gpe_sts_bits[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a612e59c81f742dd4ea1a9c02842ddf17341eb0 Gerrit-Change-Number: 31070 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants: Set tcc offset value
by Sumeet R Pawnikar (Code Review) 24 Jan '19

24 Jan '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31037 Change subject: mb/google/sarien/variants: Set tcc offset value ...................................................................... mb/google/sarien/variants: Set tcc offset value Set tcc offset value to 5 degree celsius for Sarien system. BRANCH=None BUG=b:122636962 TEST=Built and tested on Sarien system Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/31037/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ff26cbf..98009f0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -65,6 +65,9 @@ #| I2C1 | Touchpad | #| I2C4 | H1 TPM | #+-------------------+---------------------------+ + + register "tcc_offset" = "5" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 59f1f30..76e5db7 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -75,7 +75,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+ - register "tcc_offset" = "3" + register "tcc_offset" = "5" register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, -- To view, visit https://review.coreboot.org/c/coreboot/+/31037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Gerrit-Change-Number: 31037 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by build bot (Jenkins) (Code Review) 24 Jan '19

24 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/25442/9/src/soc/intel/denverton_ns/lpc.c File src/soc/intel/denverton_ns/lpc.c: https://review.coreboot.org/#/c/25442/9/src/soc/intel/denverton_ns/lpc.c@418 PS9, Line 418: if(!relax_security) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 9 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 14:21:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: FSP 2.0: Add fsp_relax_security
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has uploaded a new patch set (#9) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25437 ) Change subject: FSP 2.0: Add fsp_relax_security ...................................................................... FSP 2.0: Add fsp_relax_security The rationale is that for some hardware testing tools to work properly some register must not be locked, adding this hook allows the platform to define its way of disabling the locks. The implementation is to not call the final FSP notify stage that does the locking. Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/notify.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/25437/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/25437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I972e7387c2612ee0053df21afb55b0b264961174 Gerrit-Change-Number: 25437 Gerrit-PatchSet: 9 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Enable ACPI using intelblock
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has uploaded a new patch set (#8) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25428 ) Change subject: soc/intel/denverton_ns: Enable ACPI using intelblock ...................................................................... soc/intel/denverton_ns: Enable ACPI using intelblock - Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/harcuvar/fadt.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h 11 files changed, 96 insertions(+), 172 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/25428/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/25428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Gerrit-Change-Number: 25428 Gerrit-PatchSet: 8 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dg <dg1979ie(a)yahoo.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Configure MCA
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25433 ) Change subject: soc/intel/denverton_ns: Configure MCA ...................................................................... soc/intel/denverton_ns: Configure MCA Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/25433 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b3a12c5..ce6df68 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -35,12 +35,41 @@ static struct smm_relocation_attrs relo_attrs; +static void dnv_configure_mca(void) +{ + msr_t msr; + int num_banks; + struct cpuid_result cpuid_regs; + + /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE + * and CPUID.(EAX=1):EDX[14]==1 MCA*/ + cpuid_regs = cpuid(1); + if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) + return; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK; + if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { + /* Enable all error logging */ + msr.lo = msr.hi = 0xffffffff; + wrmsr(IA32_MCG_CTL, msr); + } + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + of these banks are core vs package scope. For now every CPU clears + every bank. */ + mca_configure(NULL); +} + static void denverton_core_init(struct device *cpu) { msr_t msr; printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Clear out pending MCEs */ + dnv_configure_mca(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 825d4cf..1b27eef 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -25,6 +25,11 @@ #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c +#define IA32_MCG_CAP 0x179 +#define IA32_MCG_CAP_COUNT_MASK 0xff +#define IA32_MCG_CAP_CTL_P_BIT 8 +#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) +#define IA32_MCG_CTL 0x17b #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -- To view, visit https://review.coreboot.org/c/coreboot/+/25433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Gerrit-Change-Number: 25433 Gerrit-PatchSet: 8 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/denverton_ns: Configure MCA
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25433 ) Change subject: soc/intel/denverton_ns: Configure MCA ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Gerrit-Change-Number: 25433 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 14:05:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton_ns: Use cpulib in cpu.c
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25432 ) Change subject: soc/intel/denverton_ns: Use cpulib in cpu.c ...................................................................... soc/intel/denverton_ns: Use cpulib in cpu.c Also remove duplicate code Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/25432 Reviewed-by: Vanny E <vanessa.f.eusebio(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott(a)sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 1 insertion(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Vanny E: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Jay Talbott: Looks good to me, but someone else must approve David Guckian: Looks good to me, but someone else must approve diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index f954411..b3a12c5 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -24,6 +24,7 @@ #include <cpu/intel/turbo.h> #include <device/device.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <reg_script.h> #include <soc/msr.h> @@ -175,15 +176,6 @@ return num_cpus; } -static int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - static void set_max_turbo_freq(void) { msr_t msr, perf_ctl; -- To view, visit https://review.coreboot.org/c/coreboot/+/25432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Gerrit-Change-Number: 25432 Gerrit-PatchSet: 8 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2019