coreboot-gerrit January 2019

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Change in ...coreboot[master]: util/kconfig: Add `toada` Ada spec generation tool
by Nico Huber (Code Review) 24 Jan '19

24 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31053 Change subject: util/kconfig: Add `toada` Ada spec generation tool ...................................................................... util/kconfig: Add `toada` Ada spec generation tool Converts `auto.conf` to an Ada spec file. Write to $(obj)/cb-config.ads and set the package name to `CB.Config`. Change-Id: I97c060d8a613c74a82a18aff9524ad4b01f9df56 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile M util/kconfig/Makefile A util/kconfig/toada.c 3 files changed, 159 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31053/1 diff --git a/Makefile b/Makefile index f12b616..13b73ff 100644 --- a/Makefile +++ b/Makefile @@ -44,6 +44,7 @@ DOTCONFIG ?= $(top)/.config KCONFIG_CONFIG = $(DOTCONFIG) +KCONFIG_AUTOADS := $(obj)/cb-config.ads KCONFIG_AUTOHEADER := $(obj)/config.h KCONFIG_AUTOCONFIG := $(obj)/auto.conf KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd @@ -51,10 +52,12 @@ KCONFIG_TRISTATE := $(obj)/tristate.conf KCONFIG_NEGATIVES := 1 KCONFIG_STRICT := 1 +KCONFIG_PACKAGE := CB.Config COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT +COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE # directory containing the toplevel Makefile.inc TOPLEVEL := . @@ -179,6 +182,12 @@ $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf +$(MAKE) oldconfig +$(KCONFIG_AUTOCONFIG): $(KCONFIG_AUTOHEADER) + true + +$(KCONFIG_AUTOADS): $(KCONFIG_AUTOCONFIG) $(objutil)/kconfig/toada + $(objutil)/kconfig/toada CB.Config <$< >$@ + # Add a new class of source/object files to the build system add-class= \ $(eval $(1)-srcs:=) \ diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index 3b00da3..a79229d 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -344,6 +344,8 @@ $(HOSTCC) $(HOSTCFLAGS) -o $@ $^ $(HOSTLOADLIBES_nconf) $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs)) $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ +$(objk)/toada: $(objk)/toada.o + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(objk)/mconf.o: $(srck)/mconf.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $< @@ -382,5 +384,8 @@ $(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@ +$(objk)/toada.o: $(srck)/toada.c + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $< + $(objk)/%.o: HOSTCFLAGS+=-I$(srck) -I$(objk) $(objk)/%.o: HOSTCXXFLAGS+=-I$(srck) -I$(objk) diff --git a/util/kconfig/toada.c b/util/kconfig/toada.c new file mode 100644 index 0000000..9a11b04 --- /dev/null +++ b/util/kconfig/toada.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ctype.h> +#include <stdio.h> +#include <string.h> +#include <stdbool.h> + +static void print_bool(const char *const name, const bool val) +{ + printf(" %-46s : constant boolean := %s;\n", + name, val ? "true" : "false"); +} + +static void print_hex(const char *const name, const char *val) +{ + unsigned int hexlen; + + printf(" %-46s : constant := 16#", name); + for (hexlen = strlen(val); hexlen > 0;) { + const unsigned int len = hexlen % 4 ? : 4; + char quad[] = "0000"; + unsigned int i; + + for (i = 0; i < len; ++i) + quad[4 - len + i] = val[i]; + printf("%s", quad); + + val += len; + hexlen -= len; + if (hexlen > 0) + printf("_"); + } + printf ("#;\n"); +} + +static void print_dec(const char *const name, const char *const val) +{ + printf(" %-46s : constant := %s;\n", name, val); +} + +static void print_string(const char *const name, const char *const val) +{ + printf(" %-46s : constant string := \"%s\";\n", name, val); +} + +int main(int argc, char *argv[]) +{ + char unset_fmt[256], string_fmt[256], set_fmt[256], line[256]; + char *prefix = "CONFIG", *package = "KConfig"; + + if (argc > 3) { + fprintf(stderr, + "Usage: %s [<package name> [<config prefix>]]\n\n", + argv[0]); + return 1; + } + if (argc > 2) + prefix = argv[2]; + if (argc > 1) + package = argv[1]; + + snprintf(set_fmt, sizeof(set_fmt), "%s_%%255[^=]=%%255s", prefix); + snprintf(string_fmt, sizeof(string_fmt), + "%s_%%255[^=]=\"%%255[^\"]\"", prefix); + snprintf(unset_fmt, sizeof(unset_fmt), + "# %s_%%255s is not set", prefix); + + printf("package %s is\n\n", package); + + while (fgets(line, sizeof(line), stdin)) { + char name[256], val[256]; + + if (line[strlen(line) - 1] != '\n') { + fprintf(stderr, + "Line longer than %zu chars, skipping...\n", + sizeof(line) - 1); + while (fgets(line, sizeof(line), stdin)) { + if (line[strlen(line) - 1] == '\n') + break; + } + continue; + } + + if (sscanf(line, unset_fmt, name) == 1) { + print_bool(name, false); + continue; + } + + if (sscanf(line, string_fmt, name, val) == 2) { + print_string(name, val); + continue; + } + + switch (sscanf(line, set_fmt, name, val)) { + case 1: + /* ignore for now, our Kconfig is full of these atm */ + /* fprintf(stderr, "unset non-bool: %s=\n", name); */ + continue; + case 2: + if (strcmp(val, "\"\"") == 0) { + print_string(name, ""); + } else if (strcmp(val, "y") == 0) { + print_bool(name, true); + } else if (strncmp(val, "0x", 2) == 0) { + print_hex(name, val + 2); + } else if (isdigit(val[0])) { + print_dec(name, val); + } else { + fprintf(stderr, + "couldn't parse value '%s' for '%s'\n", + val, name); + } + continue; + default: + break; + } + + unsigned int i = 0; + while (isspace(line[i])) + ++i; + if (line[i] == '#') { + printf(" --%s", line + i + 1); + continue; + } else if (i == strlen(line)) { + continue; + } + + fprintf(stderr, "spurious line:\n%s", line); + } + + printf("\nend %s;\n", package); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97c060d8a613c74a82a18aff9524ad4b01f9df56 Gerrit-Change-Number: 31053 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/x4x: Put stage cache in TSEG
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25606 ) Change subject: nb/intel/x4x: Put stage cache in TSEG ...................................................................... Patch Set 41: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8 Gerrit-Change-Number: 25606 Gerrit-PatchSet: 41 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 13:44:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/pineview: Put stage cache in TSEG
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25605 ) Change subject: nb/intel/pineview: Put stage cache in TSEG ...................................................................... nb/intel/pineview: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Foxconn D41S. Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25605 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc A src/northbridge/intel/pineview/stage_cache.c 3 files changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index b592501..1878cc4 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -32,6 +32,7 @@ select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_NORTHBRIDGE_INIT string @@ -45,4 +46,8 @@ hex default 0xe0000000 +config SMM_RESERVED_SIZE + hex + default 0x80000 + endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 524bcae..90a9f48 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -27,5 +27,8 @@ romstage-y += early_init.c postcar-y += ram_calc.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c endif diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c new file mode 100644 index 0000000..3e2f882 --- /dev/null +++ b/src/northbridge/intel/pineview/stage_cache.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include <cpu/intel/smm/gen1/smi.h> +#include "pineview.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/25605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Gerrit-Change-Number: 25605 Gerrit-PatchSet: 42 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/pineview: Put stage cache in TSEG
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25605 ) Change subject: nb/intel/pineview: Put stage cache in TSEG ...................................................................... Patch Set 41: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Gerrit-Change-Number: 25605 Gerrit-PatchSet: 41 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 13:43:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Put stage cache in TSEG
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25604 ) Change subject: nb/intel/gm45: Put stage cache in TSEG ...................................................................... nb/intel/gm45: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Lenovo thinkpad X200: on cold boot the external stage cache gets created and the cached ramstage gets successfully used on the S3 resume path. Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25604 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc A src/northbridge/intel/gm45/stage_cache.c 3 files changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index ef6b4ef..f1318eb 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -30,6 +30,7 @@ select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config CBFS_SIZE hex @@ -47,4 +48,8 @@ hex default 0xf0000000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index c12bbf1..95b360c 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -38,4 +38,8 @@ postcar-y += ram_calc.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + endif diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/northbridge/intel/gm45/stage_cache.c new file mode 100644 index 0000000..ed3b9d4 --- /dev/null +++ b/src/northbridge/intel/gm45/stage_cache.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include <cpu/intel/smm/gen1/smi.h> +#include "gm45.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/25604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Gerrit-Change-Number: 25604 Gerrit-PatchSet: 43 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/gm45: Put stage cache in TSEG
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25604 ) Change subject: nb/intel/gm45: Put stage cache in TSEG ...................................................................... Patch Set 42: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Gerrit-Change-Number: 25604 Gerrit-PatchSet: 42 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 13:43:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Put stage cache in TSEG
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25603 ) Change subject: nb/intel/i945: Put stage cache in TSEG ...................................................................... nb/intel/i945: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Intel D945GCLF and Lenovo Thinkpad X60, on cold boot the external stage cache gets created and the stage cache gets properly used on S3 resume. Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25603 Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/Makefile.inc A src/northbridge/intel/i945/stage_cache.c 3 files changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, approved diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 996e1d9..2c21420 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -31,6 +31,7 @@ select POSTCAR_CONSOLE select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n @@ -90,4 +91,8 @@ On other boards the check always creates a false positive, effectively making it impossible to resume. +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index ffeabdc..47014bc 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -31,4 +31,8 @@ postcar-y += ram_calc.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + endif diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c new file mode 100644 index 0000000..26d4e7e --- /dev/null +++ b/src/northbridge/intel/i945/stage_cache.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include <cpu/intel/smm/gen1/smi.h> +#include "i945.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/25603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Gerrit-Change-Number: 25603 Gerrit-PatchSet: 42 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/27586 ) Change subject: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR ...................................................................... cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR Some CPUs, (Intel core2 and pineview) have slightly different SMRR MTRR mechanism. The MSR_SMRR_PHYSBASE/MASK MSRs are at a different location, have slightly different semantics and need SMRR enable in a locked down IA32_FEATURE_CONTROL MSR. This change takes away the possibility to (not) lock IA32_FEATURE_CONTROL on these CPUs, as this is needed for SMRR MSR to work. Since sockets cover multiple CPUs of which only some support SMRR, the Kconfig option CONFIG_SET_IA32_FC_LOCK_BIT is kept in place, even though it gets meaningless on those CPUs. Locking that bit was the default anyway. With this patch Intel Netburst CPUs also configure IA32_FEATURE_CONTROL. According to Intel 64 and IA-32 Architectures Software Developer's Manual those CPUs support that MSR so issues are not to be expected. Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27586 Tested-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 5 files changed, 18 insertions(+), 12 deletions(-) Approvals: Patrick Georgi: Verified Martin Roth: Looks good to me, approved diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 275ff70..6068be1 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -287,9 +287,6 @@ /* Initialize the APIC timer */ init_timer(); - /* Set virtualization based on Kconfig option */ - set_vmx_and_lock(); - /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 52e9d3f..ab77859 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -49,8 +49,26 @@ smm_initialize(); } +#define SMRR_SUPPORTED (1 << 11) + static void per_cpu_smm_trigger(void) { + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) { + set_feature_ctrl_vmx(); + msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); + /* We don't care if the lock is already setting + as our smm relocation handler is able to handle + setups where SMRR is not enabled here. */ + if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT)) + printk(BIOS_INFO, + "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); + ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); + wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); + } else { + set_vmx_and_lock(); + } + /* Relocate the SMM handler. */ smm_relocate(); diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 75e1106..e443026 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -88,9 +88,6 @@ /* Enable the local CPU APICs */ setup_lapic(); - /* Set virtualization based on Kconfig option */ - set_vmx_and_lock(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 72a259d..19a22f1 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -125,9 +125,6 @@ /* Enable the local CPU APICs */ setup_lapic(); - /* Set virtualization based on Kconfig option */ - set_vmx_and_lock(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 16ddcc4..4e19896 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -139,9 +139,6 @@ /* Enable the local CPU APICs */ setup_lapic(); - /* Set virtualization based on Kconfig option */ - set_vmx_and_lock(); - /* Configure C States */ configure_c_states(); -- To view, visit https://review.coreboot.org/c/coreboot/+/27586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Gerrit-Change-Number: 27586 Gerrit-PatchSet: 32 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27586 ) Change subject: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR ...................................................................... Patch Set 31: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/27586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Gerrit-Change-Number: 27586 Gerrit-PatchSet: 31 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 13:42:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has uploaded a new patch set (#31) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/27586 ) Change subject: cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR ...................................................................... cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR Some CPUs, (Intel core2 and pineview) have slightly different SMRR MTRR mechanism. The MSR_SMRR_PHYSBASE/MASK MSRs are at a different location, have slightly different semantics and need SMRR enable in a locked down IA32_FEATURE_CONTROL MSR. This change takes away the possibility to (not) lock IA32_FEATURE_CONTROL on these CPUs, as this is needed for SMRR MSR to work. Since sockets cover multiple CPUs of which only some support SMRR, the Kconfig option CONFIG_SET_IA32_FC_LOCK_BIT is kept in place, even though it gets meaningless on those CPUs. Locking that bit was the default anyway. With this patch Intel Netburst CPUs also configure IA32_FEATURE_CONTROL. According to Intel 64 and IA-32 Architectures Software Developer's Manual those CPUs support that MSR so issues are not to be expected. Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 5 files changed, 18 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/27586/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/27586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Gerrit-Change-Number: 27586 Gerrit-PatchSet: 31 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2019