coreboot-gerrit January 2019

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage.
by You-Cheng Syu (Code Review) 24 Jan '19

24 Jan '19

Hello Julius Werner, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Chun-ta Lin, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30331 to look at the new patch set (#11). Change subject: google/kukui: Move some initialization from bootblock to verstage. ...................................................................... google/kukui: Move some initialization from bootblock to verstage. MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c A src/mainboard/google/kukui/early_init.c A src/mainboard/google/kukui/early_init.h M src/mainboard/google/kukui/romstage.c M src/mainboard/google/kukui/verstage.c 6 files changed, 71 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30331/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 11 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
by Patrick Rudolph (Code Review) 24 Jan '19

24 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29668 ) Change subject: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/29668/7/src/northbridge/intel/sandybridge/a… File src/northbridge/intel/sandybridge/acpi.c: https://review.coreboot.org/#/c/29668/7/src/northbridge/intel/sandybridge/a… PS7, Line 101: current += acpi_create_igfx_rmrr(current); what happens on error if acpi_create_igfx_rmrr returns 0 ? Does acpi_dmar_rmrr_fixup handle that properly ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Gerrit-Change-Number: 29668 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 08:32:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage.
by Hung-Te Lin (Code Review) 24 Jan '19

24 Jan '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30331 ) Change subject: google/kukui: Move some initialization from bootblock to verstage. ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/#/c/30331/10/src/mainboard/google/kukui/Makefil… File src/mainboard/google/kukui/Makefile.inc: https://review.coreboot.org/#/c/30331/10/src/mainboard/google/kukui/Makefil… PS10, Line 10: mainboard.c Usually mainboard.c is reserved to ramstage, especially that it contains struct for automatically initialization. I think we should move the init function to something different, for example early_init.c, and leave mainboard.c only for ramstage. https://review.coreboot.org/#/c/30331/10/src/mainboard/google/kukui/mainboa… File src/mainboard/google/kukui/mainboard.c: https://review.coreboot.org/#/c/30331/10/src/mainboard/google/kukui/mainboa… PS10, Line 70: /* Turn on real eMMC. */ : gpio_output(BOOTBLOCK_EN_L, 1); Can we move this to before mt8183_early_init, or at least before setup_chromeos_gpios? And change the comment to /* Turn on real eMMC and allow communication to EC. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 10 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 24 Jan 2019 08:30:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: add support to select the privilege level of the payload running
by Xiang Wang (Code Review) 24 Jan '19

24 Jan '19

Hello ron minnich, Shawn C, Jonathan Neuschäfer, Paul Menzel, build bot (Jenkins), Philipp Hug, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29494 to look at the new patch set (#28). Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... riscv: add support to select the privilege level of the payload running Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/arch/riscv/include/arch/boot.h D src/arch/riscv/payload.S A src/arch/riscv/payload.c 6 files changed, 82 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29494/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 28 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: riscv: save FDT pointer from mscratch to HLS
by Xiang Wang (Code Review) 24 Jan '19

24 Jan '19

Hello ron minnich, Shawn C, Jonathan Neuschäfer, Paul Menzel, build bot (Jenkins), Philipp Hug, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27545 to look at the new patch set (#27). Change subject: riscv: save FDT pointer from mscratch to HLS ...................................................................... riscv: save FDT pointer from mscratch to HLS 1. Save the FDT pointer to HLS (hart-local storage). 2. Don't use mscratch to pass FDT pointer as it is used for exception handling. Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/boot.c M src/arch/riscv/bootblock.S M src/arch/riscv/include/arch/stages.h M src/arch/riscv/include/mcall.h M src/arch/riscv/mcall.c M src/arch/riscv/stages.c 6 files changed, 25 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27545/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/27545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5 Gerrit-Change-Number: 27545 Gerrit-PatchSet: 27 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: google/kukui: Move some initialization from bootblock to verstage.
by You-Cheng Syu (Code Review) 24 Jan '19

24 Jan '19

Hello Julius Werner, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Chun-ta Lin, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30331 to look at the new patch set (#10). Change subject: google/kukui: Move some initialization from bootblock to verstage. ...................................................................... google/kukui: Move some initialization from bootblock to verstage. MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/mainboard.c A src/mainboard/google/kukui/mainboard.h M src/mainboard/google/kukui/romstage.c M src/mainboard/google/kukui/verstage.c 6 files changed, 56 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30331/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/30331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Gerrit-Change-Number: 30331 Gerrit-PatchSet: 10 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Enable Fast Strings
by HAOUAS Elyes (Code Review) 24 Jan '19

24 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25431 ) Change subject: soc/intel/denverton_ns: Enable Fast Strings ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/25431/7/src/soc/intel/denverton_ns/include/… File src/soc/intel/denverton_ns/include/soc/msr.h: https://review.coreboot.org/#/c/25431/7/src/soc/intel/denverton_ns/include/… PS7, Line 95: #define FAST_STRINGS_ENABLE_BIT (1 << 0) : #define SPEED_STEP_ENABLE_BIT (1 << 16) Can we move this to include/cpu/x86/msr.h ? -- To view, visit https://review.coreboot.org/c/coreboot/+/25431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Gerrit-Change-Number: 25431 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Thu, 24 Jan 2019 08:15:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: AGESA fam12/fam14: Drop amdfamX_conf.c file include
by Kyösti Mälkki (Code Review) 24 Jan '19

24 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30951 Change subject: AGESA fam12/fam14: Drop amdfamX_conf.c file include ...................................................................... AGESA fam12/fam14: Drop amdfamX_conf.c file include Quick and uggly approach, just paste the file in place, dropping any __PRE_RAM__ parts. That's the way it was previously done for fam15tn already, refactoring common parts will happen on a later date. Change-Id: I29fd421fb4aef984d117912ac836dee71d3d73ea Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/northbridge/amd/agesa/family12/amdfam12_conf.c M src/northbridge/amd/agesa/family12/northbridge.c D src/northbridge/amd/agesa/family14/amdfam14_conf.c M src/northbridge/amd/agesa/family14/northbridge.c 4 files changed, 146 insertions(+), 266 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/30951/1 diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c deleted file mode 100644 index 9fd6547..0000000 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * No includes in this file because it is included into northbridge.c. - */ - -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - struct dram_base_mask_t d; -#if defined(__PRE_RAM__) - dev = PCI_DEV(0, DEV_CDB, 1); -#else - dev = __f1_dev[0]; -#endif // defined(__PRE_RAM__) - - u32 temp; - temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] - d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too - - temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16] - d.mask |= (temp & 1); // read enable bit - - d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too - - return d; -} - -#if defined(__PRE_RAM__) -static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 io_min, u32 io_max, u32 nodes) -{ - u32 i; - u32 tempreg; - struct device *dev; - - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); - } - tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); - } -} - - -static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 io_min, u32 io_max, u32 nodes) -{ - u32 i; - struct device *dev; - - /* io range allocation */ - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); - pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); - } -} -#endif // defined(__PRE_RAM__) - -#if !defined(__PRE_RAM__) -static u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - - tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); -} - - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -#endif // !defined(__PRE_RAM__) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 21d8fb4..0c325e5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -45,6 +45,68 @@ static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs = 0; +struct dram_base_mask_t { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +}; + +static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + struct device *dev; + struct dram_base_mask_t d; +#if defined(__PRE_RAM__) + dev = PCI_DEV(0, DEV_CDB, 1); +#else + dev = __f1_dev[0]; +#endif // defined(__PRE_RAM__) + + u32 temp; + temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] + d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too + + temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16] + d.mask |= (temp & 1); // read enable bit + + d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too + + return d; +} + +static u32 get_io_addr_index(u32 nodeid, u32 linkn) +{ + return 0; +} + +static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) +{ + return 0; +} + +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit + pci_write_config32(__f1_dev[0], reg+4, tempreg); + + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + pci_write_config32(__f1_dev[0], reg, tempreg); +} + + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit + pci_write_config32(__f1_dev[0], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + pci_write_config32(__f1_dev[0], reg, tempreg); +} + static struct device *get_node_pci(u32 nodeid, u32 fn) { return pcidev_on_root(DEV_CDB + nodeid, fn); @@ -93,8 +155,6 @@ return (dev->path.pci.devfn >> 3) - DEV_CDB; } -#include "amdfam12_conf.c" - static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c deleted file mode 100644 index 9248e6f..0000000 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * No includes in this file because it is included into northbridge.c. - */ - -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - struct dram_base_mask_t d; -#if defined(__PRE_RAM__) - dev = PCI_DEV(0, DEV_CDB, 1); -#else - dev = __f1_dev[0]; -#endif // defined(__PRE_RAM__) - - u32 temp; - temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] - d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too - - temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16] - d.mask |= (temp & 1); // read enable bit - - d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too - - return d; -} - -#if defined(__PRE_RAM__) -static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 io_min, u32 io_max, u32 nodes) -{ - u32 i; - u32 tempreg; - struct device *dev; - - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); - } - tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); - } -} - - -static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 io_min, u32 io_max, u32 nodes) -{ - u32 i; - struct device *dev; - - /* io range allocation */ - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 1); - pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); - pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); - } -} -#endif // defined(__PRE_RAM__) - -#if !defined(__PRE_RAM__) -static u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - return 0; -} - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - - tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); -} - - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -#endif // !defined(__PRE_RAM__) - -/******************************************************************** -* Change the vendor / device IDs to match the generic VBIOS header. -********************************************************************/ -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev = vendev; - - switch (vendev) { - case 0x10029809: - case 0x10029808: - case 0x10029807: - case 0x10029806: - case 0x10029805: - case 0x10029804: - case 0x10029803: - new_vendev = 0x10029802; - break; - } - - return new_vendev; -} diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 296f40a..63bda6b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -42,6 +42,68 @@ static struct device *__f4_dev[FX_DEVS]; static unsigned fx_devs = 0; + +struct dram_base_mask_t { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +}; + +static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + struct device *dev; + struct dram_base_mask_t d; +#if defined(__PRE_RAM__) + dev = PCI_DEV(0, DEV_CDB, 1); +#else + dev = __f1_dev[0]; +#endif // defined(__PRE_RAM__) + + u32 temp; + temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] + d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too + + temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16] + d.mask |= (temp & 1); // read enable bit + + d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too + + return d; +} + +static u32 get_io_addr_index(u32 nodeid, u32 linkn) +{ + return 0; +} + +static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) +{ + return 0; +} + +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit + pci_write_config32(__f1_dev[0], reg+4, tempreg); + + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + pci_write_config32(__f1_dev[0], reg, tempreg); +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit + pci_write_config32(__f1_dev[0], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + pci_write_config32(__f1_dev[0], reg, tempreg); +} + static struct device *get_node_pci(u32 nodeid, u32 fn) { return pcidev_on_root(DEV_CDB + nodeid, fn); @@ -89,8 +151,6 @@ return (dev->path.pci.devfn >> 3) - DEV_CDB; } -#include "amdfam14_conf.c" - static void northbridge_init(struct device *dev) { printk(BIOS_DEBUG, "Northbridge init\n"); @@ -789,3 +849,25 @@ CHIP_NAME("AMD Family 14h Root Complex") .enable_dev = root_complex_enable_dev, }; + +/******************************************************************** +* Change the vendor / device IDs to match the generic VBIOS header. +********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x10029809: + case 0x10029808: + case 0x10029807: + case 0x10029806: + case 0x10029805: + case 0x10029804: + case 0x10029803: + new_vendev = 0x10029802; + break; + } + + return new_vendev; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29fd421fb4aef984d117912ac836dee71d3d73ea Gerrit-Change-Number: 30951 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: [WIP] AGESA: Fix SMM support in ASEG
by mikeb mikeb (Code Review) 24 Jan '19

24 Jan '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21624 ) Change subject: [WIP] AGESA: Fix SMM support in ASEG ...................................................................... Patch Set 4: Code-Review+1 Tested this change alone and it works :) Here is the full cbmem log with Debug Level 8: SPEW - https://pastebin.com/rrTUGidR -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 07:10:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by mikeb mikeb (Code Review) 24 Jan '19

24 Jan '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30348 ) Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... Patch Set 6: After this 30348 change merged now I have ARCH_RISCV_M enabled despite my arch is x86. While it doesn't affect anything at the moment (searched through the sources), this should be fixed somehow │ Symbol: ARCH_RISCV_M [=y] │ │ Type : boolean │ │ Defined at src/arch/riscv/Kconfig:17 │ │ │ │ │ │ Symbol: ARCH_RISCV_M_DISABLED [=n] │ │ Type : boolean │ │ Defined at src/arch/riscv/Kconfig:14 -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 6 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 06:13:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019