coreboot-gerrit January 2019

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Change in ...coreboot[master]: i945,ICH7: Add 'FIXME' comment on R/WO register
by HAOUAS Elyes (Code Review) 23 Jan '19

23 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31005 Change subject: i945,ICH7: Add 'FIXME' comment on R/WO register ...................................................................... i945,ICH7: Add 'FIXME' comment on R/WO register RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop one of them. Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/southbridge/intel/i82801gx/pcie.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31005/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 528f1aa..09a18e3 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -347,6 +347,7 @@ RCBA32(V0CTL) = 0x80000001; RCBA32(V1CAP) = 0x03128010; + /* FIXME: RPFN R/WO register and i82801gx/pcie.c try to rewrite */ RCBA32(RPFN) = 0x00543210; pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index c0f9c12..9d218c7 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -25,6 +25,7 @@ struct root_port_config { /* RPFN is a write-once register so keep a copy until it is written */ + /* FIXME: already written here intel/i945/early_init.c */ u32 orig_rpfn; u32 new_rpfn; int num_ports; -- To view, visit https://review.coreboot.org/c/coreboot/+/31005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Gerrit-Change-Number: 31005 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout
by Daniel Kurtz (Code Review) 23 Jan '19

23 Jan '19

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30998 to review the following change. Change subject: soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout ...................................................................... soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout It is possible to configure debounce, but leave it disabled by specifying a 0 value for the timeout. Add a define for allowing to do so via the PAD_DEBOUNCE() macro. Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> BUG=b:113880780 BRANCH=none TEST=compile Change-Id: I9de61297b0677cc904535a51c16970eecb52021d --- M src/soc/amd/stoneyridge/include/soc/gpio.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30998/1 diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 04eda49..47eae84 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -462,6 +462,7 @@ #define GPIO_TIMEBASE_15560uS (1 << 7) #define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ GPIO_TIMEBASE_15560uS) +#define GPIO_IN_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) #define GPIO_IN_60uS (1 | GPIO_TIMEBASE_61uS) #define GPIO_IN_120uS (2 | GPIO_TIMEBASE_61uS) #define GPIO_IN_200uS (3 | GPIO_TIMEBASE_61uS) -- To view, visit https://review.coreboot.org/c/coreboot/+/30998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9de61297b0677cc904535a51c16970eecb52021d Gerrit-Change-Number: 30998 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Enable dptf functionality
by Patrick Georgi (Code Review) 23 Jan '19

23 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29686 ) Change subject: mb/intel/icelake_rvp: Enable dptf functionality ...................................................................... mb/intel/icelake_rvp: Enable dptf functionality Enable dptf functionality for IceLake based U and Y systems. Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/29686 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 0d2ea76..6d7fad7 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -157,6 +157,9 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 62c7a82..0972c29 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -157,6 +157,9 @@ # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" -- To view, visit https://review.coreboot.org/c/coreboot/+/29686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Gerrit-Change-Number: 29686 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/intel/glkrvp: Fix termination for dual voltage pins
by Shamile Khan (Code Review) 23 Jan '19

23 Jan '19

Shamile Khan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30867 Change subject: mb/intel/glkrvp: Fix termination for dual voltage pins ...................................................................... mb/intel/glkrvp: Fix termination for dual voltage pins These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1 Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> --- M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30867/1 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 94620432..03f2147 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -70,7 +70,7 @@ PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */ PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */ PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, DN_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* DSI_I2C_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SCL */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */ @@ -136,7 +136,7 @@ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, DN_20K, IGNORE, SAME),/*x4 Slot-2 Reset*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx0RxDCRx0, SAME),/*x4 Slot-2 Reset*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/ @@ -159,33 +159,33 @@ PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/ PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/ PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/ - PAD_CFG_NF_IOSSTATE(GPIO_128, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_129, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_130, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ + PAD_CFG_NF_IOSSTATE(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI0_HPD*/ PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI1_HPD*/ PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE),/*HV_EDP_HPD*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, DN_20K, IGNORE, SAME),/*DGPU Power Select*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*DGPU Power Select*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*SATA_GP0 (DC RTD3 need)*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/ PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/ PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/ PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/ - PAD_CFG_GPI_APIC_IOS(GPIO_143, DN_20K, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/ + PAD_CFG_GPI_APIC_IOS(GPIO_143, NONE, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/ PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/ PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/ PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, UP_20K, TxDRxE, ENPD),/*NFC reset*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*NFC reset*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, UP_20K, IGNORE, SAME),/*SD_MODE for spk*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_BCLK*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_WS_SYNC*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, UP_20K, TxDRxE, ENPD),/*Touch Panel Power Enable*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*Touch Panel Power Enable*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_SDO*/ /* AUDIO COMMUNITY GPIOS*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/30867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1 Gerrit-Change-Number: 30867 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/lint: Update non-ascii linter for FreeBSD
by Patrick Georgi (Code Review) 23 Jan '19

23 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28448 ) Change subject: util/lint: Update non-ascii linter for FreeBSD ...................................................................... util/lint: Update non-ascii linter for FreeBSD On FreeBSD, this test was failing with the error: "grep: Argument list too long" - Remove support for testing coreboot not in a git repo. Many of the other linters already don't support this. - Use git grep to find offending files, then xargs to print out the lines. Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd Signed-off-by: Martin Roth <martinr(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/28448 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/lint/lint-stable-016-non-ascii 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/util/lint/lint-stable-016-non-ascii b/util/lint/lint-stable-016-non-ascii index beffd83..3c22900 100755 --- a/util/lint/lint-stable-016-non-ascii +++ b/util/lint/lint-stable-016-non-ascii @@ -21,13 +21,11 @@ EXCLUDED_FILES='to-wiki/towiki\.sh$\|vga/vga_font\|video/font\|PDCurses.*x11' EXCLUDED_PHRASES='Copyright\|Ported to\|Intel®\|°C\|°F\|Athlon™\|Copyright.*©\|A-Za-zÀ-ÿ' -# Use git ls-files if the code is in a git repo, otherwise use find. -if [ -n "$(command -v git)" ] && \ - [ "$(git rev-parse --is-inside-work-tree 2>/dev/null)" = "true" ] +# Exit if git isn't present or the code isn't in a git repo +if [ -z "$(command -v git)" ] || \ + [ "$(git rev-parse --is-inside-work-tree 2>/dev/null)" != "true" ] then - FIND_FILES="git ls-files" -else - FIND_FILES="find . " + exit fi # 1. Get the list of files to parse and send them through grep @@ -36,10 +34,12 @@ # 3. Remove common phrases and names that have been found # 4. Run the result through grep again to highlight the issues that were # found. Without this step, the characters can be difficult to see. -grep -n "[^ -~]" \ - $(${FIND_FILES} | sed 's|^\./||' | sort | \ - grep "$INCLUDED_FILES" | \ - grep -v "$EXCLUDED_DIRS" | \ - grep -v "$EXCLUDED_FILES") | \ - grep -iv "$EXCLUDED_PHRASES" | \ - grep --color='auto' "[^ -~]" +# shellcheck disable=SC2046 +git grep -lP "[^\t-~]" | \ + grep "$INCLUDED_FILES" | \ + grep -v "$EXCLUDED_DIRS" | \ + grep -v "$EXCLUDED_FILES" | \ + xargs -I % \ + grep -n "[^ -~]" % | \ + grep -iv "$EXCLUDED_PHRASES" | \ + grep --color='auto' "[^ -~]" -- To view, visit https://review.coreboot.org/c/coreboot/+/28448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd Gerrit-Change-Number: 28448 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: google/kukui: Revise FMAP layout for larger CBFS
by Hung-Te Lin (Code Review) 23 Jan '19

23 Jan '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31035 Change subject: google/kukui: Revise FMAP layout for larger CBFS ...................................................................... google/kukui: Revise FMAP layout for larger CBFS Kukui with vboot enabled will build with `detachable_ui`, which needs larger space in CBFS for more complicated assets. So we need to revise FMAP sections: - Bootblock only needs <= 32K. - GBB can be much smaller since assets moved from GBB to CBFS. - COREBOOT(CBFS) should take all space left. - FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can get larger continuous space BUG=b:123202015 TEST=Builds and boots on Kukui P1 Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/chromeos.fmd 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31035/1 diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 1602f80..c563e08 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -1,10 +1,10 @@ FLASH@0x0 0x800000 { WP_RO@0x0 0x200000 { RO_SECTION@0x0 0x1f0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0xe0000 - FMAP@0x100000 0x1000 - GBB@0x101000 0xeef00 + BOOTBLOCK@0 32K + FMAP@0x8000 0x1000 + COREBOOT(CBFS)@0x9000 0x1e4000 + GBB@0x1ed000 0x2f00 RO_FRID@0x1eff00 0x100 } RO_VPD@0x1f0000 0x10000 -- To view, visit https://review.coreboot.org/c/coreboot/+/31035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd Gerrit-Change-Number: 31035 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variant/nami: disable unused usb2 ports
by Ren Kuo (Code Review) 23 Jan '19

23 Jan '19

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30986 Change subject: mb/google/poppy/variant/nami: disable unused usb2 ports ...................................................................... mb/google/poppy/variant/nami: disable unused usb2 ports disable unused usb2 ports of bard and ekko skus BUG=none TEST=build a test firmware and run lsusb to check usb ports Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30986/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index c656954..8592cae 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -267,6 +267,10 @@ case SKU_2_EKKO: case SKU_3_EKKO: pl2_id = PL2_ID_BARD_EKKO; + cfg->usb2_ports[5].enable = 0; + cfg->usb2_ports[7].enable = 0; + cfg->usb2_ports[8].enable = 0; + cfg->usb2_ports[9].enable = 0; break; default: break; -- To view, visit https://review.coreboot.org/c/coreboot/+/30986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1 Gerrit-Change-Number: 30986 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: mb/google/arcada: Add settings for noise mitgation
by Casper Chang (Code Review) 23 Jan '19

23 Jan '19

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31034 Change subject: mb/google/arcada: Add settings for noise mitgation ...................................................................... mb/google/arcada: Add settings for noise mitgation Enable acoustic noise mitgation for arcada platform, the slow slew rates are fast time dived by 2. BUG=none BRANCH=none TEST=none Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31034/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ff26cbf..af8fe18 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -36,6 +36,11 @@ register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" register "Device4Enable" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "0" + register "SlowSlewRateForGt" = "0" + register "SlowSlewRateForSa" = "0" + register "SlowSlewRateForFivr" = "0" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port -- To view, visit https://review.coreboot.org/c/coreboot/+/31034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb Gerrit-Change-Number: 31034 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: mb/lenovo/x131e: add VBT
by James (Code Review) 23 Jan '19

23 Jan '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31003 Change subject: mb/lenovo/x131e: add VBT ...................................................................... mb/lenovo/x131e: add VBT Change-Id: Ibedb43852dc9b846850e1070b84f708c847b7dbf Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/x131e/Kconfig A src/mainboard/lenovo/x131e/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31003/1 diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e063a38..2a58020 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -21,6 +21,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select SERIRQ_CONTINUOUS_MODE + select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x131e/data.vbt b/src/mainboard/lenovo/x131e/data.vbt new file mode 100644 index 0000000..30adeaa --- /dev/null +++ b/src/mainboard/lenovo/x131e/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/31003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibedb43852dc9b846850e1070b84f708c847b7dbf Gerrit-Change-Number: 31003 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

6 8

Change in ...coreboot[master]: nb/intel/pineview: Use parallel MP init
by Patrick Georgi (Code Review) 23 Jan '19

23 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25602 ) Change subject: nb/intel/pineview: Use parallel MP init ...................................................................... nb/intel/pineview: Use parallel MP init Remove guards around CPU code on which all platforms use parallel MP init code. This removes the option to disable HT siblings. Tested on Foxconn D41S. Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25602 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/model_106cx/model_106cx_init.c M src/mainboard/foxconn/d41s/cmos.layout M src/mainboard/intel/d510mo/cmos.layout M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/northbridge.c M src/southbridge/intel/i82801gx/lpc.c 6 files changed, 2 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 24a9ad2..75e1106 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -17,12 +17,9 @@ #include <device/device.h> #include <string.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/intel/common/common.h> @@ -84,20 +81,10 @@ /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Update the microcode */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_update_microcode_from_cbfs(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Setup MTRRs */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { - x86_setup_mtrrs(); - x86_mtrr_check(); - } - /* Enable the local CPU APICs */ setup_lapic(); @@ -111,10 +98,6 @@ configure_misc(); /* TODO: PIC thermal sensor control */ - - /* Start up my CPU siblings */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index 9b9a084..b006973 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -44,7 +44,6 @@ 416 512 s 0 boot_devices # coreboot config options: cpu -944 1 e 2 hyper_threading #945 7 r 0 unused # coreboot config options: northbridge diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index 9b9a084..b006973 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -44,7 +44,6 @@ 416 512 s 0 boot_devices # coreboot config options: cpu -944 1 e 2 hyper_threading #945 7 r 0 unused # coreboot config options: northbridge diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 6168305..b592501 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,6 +31,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select PARALLEL_MP config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index ee1efd3..ec2c902 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -151,26 +151,6 @@ pci_write_config8(dev, SMRAM, smram); } -/* - * Really doesn't belong here but will go away with parallel mp init, - * so let it be here for a while... - */ -int cpu_get_apic_id_map(int *apic_id_map) -{ - unsigned int i; - - /* Logical processors (threads) per core */ - const struct cpuid_result cpuid1 = cpuid(1); - /* Read number of cores. */ - const char cores = (cpuid1.ebx >> 16) & 0xf; - - /* TODO in parallel MP cpuid(1).ebx */ - for (i = 0; i < cores; i++) - apic_id_map[i] = i; - - return cores; -} - static void mch_domain_set_resources(struct device *dev) { struct resource *res; @@ -218,7 +198,7 @@ static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 5ad05c7..7497c79 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -350,11 +350,6 @@ printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - smm_lock(); #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/25602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Gerrit-Change-Number: 25602 Gerrit-PatchSet: 41 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2019