coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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1296 discussions

Change in ...coreboot[master]: mb/lenovo/x131e: correct CPU socket
by James (Code Review) 23 Jan '19

23 Jan '19

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31002 Change subject: mb/lenovo/x131e: correct CPU socket ...................................................................... mb/lenovo/x131e: correct CPU socket Change-Id: Ibfcf2f0ebbb24c6c2f7a4f2ca5217c0f38f82dde Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/x131e/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31002/1 diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index ccdff7c..299a470 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -18,7 +18,7 @@ register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0x0 on - chip cpu/intel/socket_rPGA989 + chip cpu/intel/socket_FCBGA1023 device lapic 0x0 on end end chip cpu/intel/model_206ax -- To view, visit https://review.coreboot.org/c/coreboot/+/31002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfcf2f0ebbb24c6c2f7a4f2ca5217c0f38f82dde Gerrit-Change-Number: 31002 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Drop leftover debug function declarations
by Kyösti Mälkki (Code Review) 23 Jan '19

23 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30893 Change subject: Drop leftover debug function declarations ...................................................................... Drop leftover debug function declarations Change-Id: Ib93b816e7ab3146f6f70ad4089327cd6b7bc7c24 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/fsp_rangeley/northbridge.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/intel/denverton_ns/include/soc/bootblock.h M src/soc/intel/fsp_baytrail/include/soc/baytrail.h 6 files changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30893/1 diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index f68d175..e21f540 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -64,14 +64,6 @@ u32 sideband_read(int port, int reg); void sideband_write(int port, int reg, long data); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); -void report_platform_info(void); - #ifndef __SIMPLE_DEVICE__ void northbridge_acpi_fill_ssdt_generator(struct device *device); #endif diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index f67995d..22b9437 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -223,12 +223,6 @@ void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 5756c90..1f686d5 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -272,13 +272,6 @@ void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); -void report_platform_info(void); #endif /* !__SMM__ */ #endif diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index faa9cd90..64fd64a 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -214,13 +214,6 @@ void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); - #endif /* !__SMM__ */ void pch_enable_lpc(void); diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h index 5136ecd..6efedc3 100644 --- a/src/soc/intel/denverton_ns/include/soc/bootblock.h +++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h @@ -22,12 +22,4 @@ //void bootblock_systemagent_early_init(void); void early_uart_init(void); -/* Bootblock post console init programming */ -//void enable_smbus(void); -//void i2c_early_init(void); -//void pch_early_init(void); -//void report_platform_info(void); -//void report_memory_config(void); -//void set_max_freq(void); - #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 82fd0a1..34831b1 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -58,12 +58,6 @@ int soc_silicon_supported(int type, int rev); void soc_enable(struct device *dev); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* __PRE_RAM__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib93b816e7ab3146f6f70ad4089327cd6b7bc7c24 Gerrit-Change-Number: 30893 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: add support move bootblock to CAR/SRAM before exection
by Xiang Wang (Code Review) 23 Jan '19

23 Jan '19

Xiang Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27645 ) Change subject: riscv: add support move bootblock to CAR/SRAM before exection ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1f53a7dbd7db9643bd9aeea6567cd4fae0f310e Gerrit-Change-Number: 27645 Gerrit-PatchSet: 18 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/drivers: Remove needless '&' on function pointers
by HAOUAS Elyes (Code Review) 23 Jan '19

23 Jan '19

Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29868 to look at the new patch set (#4). Change subject: src/drivers: Remove needless '&' on function pointers ...................................................................... src/drivers: Remove needless '&' on function pointers Change-Id: I7a99d0dcbc8ea1362a12a68fa519c49058d30a05 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/generic/generic.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/gpio_regulator/gpio_regulator.c M src/drivers/generic/max98357a/max98357a.c M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/rt5663/rt5663.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/tpm/chip.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/wifi/wifi.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/net/r8168.c M src/drivers/pc80/tpm/tis.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/spi/acpi/acpi.c M src/drivers/usb/acpi/usb_acpi.c 22 files changed, 62 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29868/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a99d0dcbc8ea1362a12a68fa519c49058d30a05 Gerrit-Change-Number: 29868 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: riscv: save FDT pointer from mscratch to HLS
by build bot (Jenkins) (Code Review) 23 Jan '19

23 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27545 ) Change subject: riscv: save FDT pointer from mscratch to HLS ...................................................................... Patch Set 26: (2 comments) https://review.coreboot.org/#/c/27545/26/src/arch/riscv/include/arch/stages… File src/arch/riscv/include/arch/stages.h: https://review.coreboot.org/#/c/27545/26/src/arch/riscv/include/arch/stages… PS26, Line 21: void stage_entry(int hartid, void *fdt) __attribute__((section(".text.stage_entry"))); line over 80 characters https://review.coreboot.org/#/c/27545/26/src/arch/riscv/include/mcall.h File src/arch/riscv/include/mcall.h: https://review.coreboot.org/#/c/27545/26/src/arch/riscv/include/mcall.h@59 PS26, Line 59: _Static_assert(sizeof(hls_t) == HLS_SIZE, "HLS_SIZE must equal to sizeof(hls_t)"); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/27545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24554528969e36c9e98c0ebd733e002e215a52e5 Gerrit-Change-Number: 27545 Gerrit-PatchSet: 26 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn C <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Jan 2019 07:21:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep
by Kane Chen (Code Review) 23 Jan '19

23 Jan '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31021 Change subject: UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep ...................................................................... UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep New emmc DLL values for Meep. BUG=b:120561055 TEST=Boot to OS on 13 systems Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/octopus/variants/meep/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31021/1 diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index f7aeac1..c639b73 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0d" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c2a2a2a" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00171a1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/31021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Gerrit-Change-Number: 31021 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/{amd,intel}: Remove needless '&' on function pointers
by HAOUAS Elyes (Code Review) 23 Jan '19

23 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29862 ) Change subject: soc/{amd,intel}: Remove needless '&' on function pointers ...................................................................... Patch Set 8: > (2 comments) > > Was there a compiler warning or did you do this manually? I did it manually -- To view, visit https://review.coreboot.org/c/coreboot/+/29862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Gerrit-Change-Number: 29862 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Jan 2019 03:36:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/{amd,intel}: Remove needless '&' on function pointers
by HAOUAS Elyes (Code Review) 23 Jan '19

23 Jan '19

Hello Patrick Rudolph, David Guckian, Vanny E, York Yang, Philipp Deppenwiese, build bot (Jenkins), David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29862 to look at the new patch set (#8). Change subject: soc/{amd,intel}: Remove needless '&' on function pointers ...................................................................... soc/{amd,intel}: Remove needless '&' on function pointers Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_broadwell_de/smbus.c M src/soc/intel/quark/lpc.c M src/soc/intel/quark/northcluster.c M src/soc/intel/quark/uart.c 26 files changed, 106 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29862/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Gerrit-Change-Number: 29862 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: superio/nuvoton/nct6776: Fix typo on DMA
by HAOUAS Elyes (Code Review) 23 Jan '19

23 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31040 Change subject: superio/nuvoton/nct6776: Fix typo on DMA ...................................................................... superio/nuvoton/nct6776: Fix typo on DMA Change-Id: I1ae1dc189c35b97aec836c3466ceb5fd2dbc0ec0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/nuvoton/nct6776/acpi/superio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31040/1 diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index abd5562..ad8d38f 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -88,7 +88,7 @@ Offset (0x72), PNP_IRQ1, 8, /* Second IRQ */ Offset (0x74), - PNP_DMA0, 8, /* DRQ */ + PNP_DMA0, 8, /* DMA */ } Method (_CRS) -- To view, visit https://review.coreboot.org/c/coreboot/+/31040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ae1dc189c35b97aec836c3466ceb5fd2dbc0ec0 Gerrit-Change-Number: 31040 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: correct the spd of hynix dimm
by Ren Kuo (Code Review) 23 Jan '19

23 Jan '19

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30909 Change subject: mb/google/poppy/variants/nami: correct the spd of hynix dimm ...................................................................... mb/google/poppy/variants/nami: correct the spd of hynix dimm Correct the P/N of spd data for hynix_dimm_H5AN8G6NCJR-VKC BUG=b:122813741 TEST=emerge-nami coreboot chromeos-bootimage check the memeory data on DUT Change-Id: Ia0f857a072efe60e9569214f4b639d8becf3a7e4 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30909/1 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex index 5050647..060871d 100644 --- a/src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 -36 43 4A 52 36 4E 2D 56 4B 20 20 20 20 00 80 AD +80 AD 01 00 00 00 00 00 00 48 35 41 38 47 36 4E +43 4A 52 2D 56 4B 43 20 20 20 20 20 20 00 80 AD FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/30909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0f857a072efe60e9569214f4b639d8becf3a7e4 Gerrit-Change-Number: 30909 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019