coreboot-gerrit January 2019

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Change in ...coreboot[master]: src/superio: Use FixedIO
by HAOUAS Elyes (Code Review) 22 Jan '19

22 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31038 Change subject: src/superio: Use FixedIO ...................................................................... src/superio: Use FixedIO Change-Id: Iec28593b3cfd1a6061d30c4f7dec1326666b0734 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/acpi/pnp_kbc.asl M src/superio/ite/it8720f/acpi/superio.asl M src/superio/ite/it8772f/acpi/superio.asl M src/superio/ite/it8783ef/acpi/superio.asl M src/superio/nuvoton/nct6776/acpi/superio.asl M src/superio/smsc/mec1308/acpi/superio.asl M src/superio/smsc/sio1007/acpi/superio.asl M src/superio/winbond/w83627dhg/acpi/superio.asl M src/superio/winbond/w83627hf/acpi/superio.asl M src/superio/winbond/w83667hg-a/ps2_controller.asl 10 files changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31038/1 diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl index cbcfd55..7b98590 100644 --- a/src/superio/acpi/pnp_kbc.asl +++ b/src/superio/acpi/pnp_kbc.asl @@ -91,8 +91,8 @@ Name (_PRS, ResourceTemplate () { StartDependentFn (0,0) { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + FixedIO(0x0060, 0x01) + FixedIO(0x0064, 0x01) IRQNoFlags () {1} } EndDependentFn() diff --git a/src/superio/ite/it8720f/acpi/superio.asl b/src/superio/ite/it8720f/acpi/superio.asl index 1e94655..b6dba7c 100644 --- a/src/superio/ite/it8720f/acpi/superio.asl +++ b/src/superio/ite/it8720f/acpi/superio.asl @@ -95,7 +95,7 @@ { /* Announce the used I/O ports to the OS */ Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + FixedIO (SUPERIO_PNP_BASE, 0x02) }) } diff --git a/src/superio/ite/it8772f/acpi/superio.asl b/src/superio/ite/it8772f/acpi/superio.asl index a8a0564..f94fd9a 100644 --- a/src/superio/ite/it8772f/acpi/superio.asl +++ b/src/superio/ite/it8772f/acpi/superio.asl @@ -161,13 +161,13 @@ Name (_CRS, ResourceTemplate () { - IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + FixedIO (SIO_GPIO_IO0, 0x01) IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) }) Name (_PRS, ResourceTemplate () { - IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + FixedIO (SIO_GPIO_IO0, 0x01) IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) }) } @@ -208,15 +208,15 @@ Name (_CRS, ResourceTemplate() { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) IRQNoFlags () {1} }) Name (_PRS, ResourceTemplate() { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) IRQNoFlags () {1} }) } @@ -254,16 +254,16 @@ Name (_CRS, ResourceTemplate() { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + FixedIO (0x03F0, 0x06) + FixedIO (0x03F7, 0x01) IRQNoFlags () {6} DMA (Compatibility, NotBusMaster, Transfer8) {2} }) Name (_PRS, ResourceTemplate() { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + FixedIO (0x03F0, 0x06) + FixedIO (0x03F7, 0x01) IRQNoFlags () {6} DMA (Compatibility, NotBusMaster, Transfer8) {2} }) diff --git a/src/superio/ite/it8783ef/acpi/superio.asl b/src/superio/ite/it8783ef/acpi/superio.asl index d7a320e..90b2991 100644 --- a/src/superio/ite/it8783ef/acpi/superio.asl +++ b/src/superio/ite/it8783ef/acpi/superio.asl @@ -97,7 +97,7 @@ { /* Announce the used i/o ports to the OS */ Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + FixedIO (SUPERIO_PNP_BASE, 0x02) }) } diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index abd5562..acfba5a 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -88,14 +88,14 @@ Offset (0x72), PNP_IRQ1, 8, /* Second IRQ */ Offset (0x74), - PNP_DMA0, 8, /* DRQ */ + PNP_DMA0, 8, /* DMA */ } Method (_CRS) { /* Announce the used I/O ports to the OS */ Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + FixedIO (SUPERIO_PNP_BASE, 0x02) }) } diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl index cc174f9..5fa5e42 100644 --- a/src/superio/smsc/mec1308/acpi/superio.asl +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -199,15 +199,15 @@ Name (_CRS, ResourceTemplate() { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) IRQNoFlags () {1} }) Name (_PRS, ResourceTemplate() { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) IRQNoFlags () {1} }) } @@ -246,12 +246,12 @@ Name (_CRS, ResourceTemplate() { - IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x01, 0x34) + FixedIO (SIO_SMBX_IO0, 0x34) }) Name (_PRS, ResourceTemplate() { - IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x01, 0x34) + FixedIO (SIO_SMBX_IO0, 0x34) }) } #endif diff --git a/src/superio/smsc/sio1007/acpi/superio.asl b/src/superio/smsc/sio1007/acpi/superio.asl index a8a0564..f94fd9a 100644 --- a/src/superio/smsc/sio1007/acpi/superio.asl +++ b/src/superio/smsc/sio1007/acpi/superio.asl @@ -161,13 +161,13 @@ Name (_CRS, ResourceTemplate () { - IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + FixedIO (SIO_GPIO_IO0, 0x01) IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) }) Name (_PRS, ResourceTemplate () { - IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + FixedIO (SIO_GPIO_IO0, 0x01) IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) }) } @@ -208,15 +208,15 @@ Name (_CRS, ResourceTemplate() { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) IRQNoFlags () {1} }) Name (_PRS, ResourceTemplate() { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) IRQNoFlags () {1} }) } @@ -254,16 +254,16 @@ Name (_CRS, ResourceTemplate() { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + FixedIO (0x03F0, 0x06) + FixedIO (0x03F7, 0x01) IRQNoFlags () {6} DMA (Compatibility, NotBusMaster, Transfer8) {2} }) Name (_PRS, ResourceTemplate() { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + FixedIO (0x03F0, 0x06) + FixedIO (0x03F7, 0x01) IRQNoFlags () {6} DMA (Compatibility, NotBusMaster, Transfer8) {2} }) diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index 301ee94..70366d8 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -106,7 +106,7 @@ { /* Announce the used i/o ports to the OS */ Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + FixedIO (SUPERIO_PNP_BASE, 0x02) }) } diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index ef4504c..3000b87 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -1134,8 +1134,8 @@ { StartDependentFn (0,0) { IRQNoFlags () {1} - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + FixedIO(0x0060, 0x01) + FixedIO(0x0064, 0x01) } EndDependentFn() }) diff --git a/src/superio/winbond/w83667hg-a/ps2_controller.asl b/src/superio/winbond/w83667hg-a/ps2_controller.asl index c3b5c75..55f9febe 100644 --- a/src/superio/winbond/w83667hg-a/ps2_controller.asl +++ b/src/superio/winbond/w83667hg-a/ps2_controller.asl @@ -38,8 +38,8 @@ Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 }) -- To view, visit https://review.coreboot.org/c/coreboot/+/31038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28593b3cfd1a6061d30c4f7dec1326666b0734 Gerrit-Change-Number: 31038 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common: SMBus setup_command()
by Arthur Heymans (Code Review) 22 Jan '19

22 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21118 ) Change subject: sb/intel/common: SMBus setup_command() ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/21118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Gerrit-Change-Number: 21118 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Jan 2019 17:41:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by Patrick Georgi (Code Review) 22 Jan '19

22 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/29968/9/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/9/src/soc/qualcomm/qcs405/spi.c@512 PS9, Line 512: unsigned int read_len = 3; //bytes; hack for now That looks incomplete. Might that be related to the issues we see when communicating with the TPM? -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 9 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 22 Jan 2019 17:06:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/smbios: Add CPU_SOCKET_TYPE
by HAOUAS Elyes (Code Review) 22 Jan '19

22 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29529 ) Change subject: arch/x86/smbios: Add CPU_SOCKET_TYPE ...................................................................... Patch Set 9: > I don't think this would be useful considering CB:31032 and > CB:31031 yes, it needs a rebase on #31032 -- To view, visit https://review.coreboot.org/c/coreboot/+/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 22 Jan 2019 16:45:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/smbios: Add CPU_SOCKET_TYPE
by Angel Pons (Code Review) 22 Jan '19

22 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29529 ) Change subject: arch/x86/smbios: Add CPU_SOCKET_TYPE ...................................................................... Patch Set 9: I don't think this would be useful considering CB:31032 and CB:31031 -- To view, visit https://review.coreboot.org/c/coreboot/+/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 22 Jan 2019 16:39:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/gm45: Use parallel MP init
by Angel Pons (Code Review) 22 Jan '19

22 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23434 ) Change subject: nb/intel/gm45: Use parallel MP init ...................................................................... Patch Set 50: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/23434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac416f671407246ee223075eee1aff511e612889 Gerrit-Change-Number: 23434 Gerrit-PatchSet: 50 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Jan 2019 16:38:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/lenovo/h8: Enable battery thresholds for more platforms, add bound...
by Patrick Rudolph (Code Review) 22 Jan '19

22 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23177 ) Change subject: ec/lenovo/h8: Enable battery thresholds for more platforms, add boundary checks ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/23177/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/23177/1//COMMIT_MSG@7 PS1, Line 7: ec/lenovo/h8: Enable battery thresholds for more platforms, add boundary checks why do you add boundary checks ? Is there an OS that sets out of bounds values ? https://review.coreboot.org/#/c/23177/1/src/ec/lenovo/h8/acpi/tp_acpi_bat_b… File src/ec/lenovo/h8/acpi/tp_acpi_bat_b0.asl: https://review.coreboot.org/#/c/23177/1/src/ec/lenovo/h8/acpi/tp_acpi_bat_b… PS1, Line 41: if (Arg1 <= 100) { use tabs instead of space -- To view, visit https://review.coreboot.org/c/coreboot/+/23177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie785819c73df1fe1600c99a0c997f3c24081964b Gerrit-Change-Number: 23177 Gerrit-PatchSet: 1 Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Jan 2019 14:40:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: SMBus setup_command()
by Kyösti Mälkki (Code Review) 22 Jan '19

22 Jan '19

Hello Patrick Rudolph, Arthur Heymans, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/21118 to look at the new patch set (#10). Change subject: sb/intel/common: SMBus setup_command() ...................................................................... sb/intel/common: SMBus setup_command() Implements the common parts of any SMBus transaction with a stub to log and recover (TBD) from timeout errors. Bits in SMBHSTCTL register are no longer preserved between transactions. Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/smbus.c 1 file changed, 84 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/21118/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/21118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Gerrit-Change-Number: 21118 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP] AGESA/binaryPI: Add NULL pointers check
by Kyösti Mälkki (Code Review) 22 Jan '19

22 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31026 Change subject: [WIP] AGESA/binaryPI: Add NULL pointers check ...................................................................... [WIP] AGESA/binaryPI: Add NULL pointers check Previously used call dev_find_slot() returned pointers to PCI device nodes that were actually not present in the hardware at all. Register reads would come back with invalid (0xff) values and writes ignored. After change to pcidev_on_root(), attempting to do register operations with non-present PCI hardware immediately halts with error get_pbus: dev is NULL! Change-Id: I785350c171a642207c5fab884a953d45a3bfe592 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31026/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 2579d37..4066d12 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -787,14 +787,18 @@ struct device *dev; u32 value; dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + if (dev != NULL) { + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + } /* disable No Snoop */ dev = pcidev_on_root(1, 1); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); + if (dev != NULL) { + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + } } struct chip_operations northbridge_amd_pi_00730F01_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I785350c171a642207c5fab884a953d45a3bfe592 Gerrit-Change-Number: 31026 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
by Paul Menzel (Code Review) 22 Jan '19

22 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23178 ) Change subject: ec/lenovo/h8: Implement ACPI methods to set battery thresholds ...................................................................... Patch Set 25: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/23178/24//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/23178/24//COMMIT_MSG@9 PS24, Line 9: There are two known (yet) different ways to manage battery thresholds. : This patch implements them and adds a way to enable them for : different mainboards. > No, it's all reverse engineered AFAIK. Could you please mention that in the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/23178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Gerrit-Change-Number: 23178 Gerrit-PatchSet: 25 Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 22 Jan 2019 13:31:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Evgeny Zinoviev <me(a)ch1p.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit January 2019