coreboot-gerrit January 2019

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Change in ...coreboot[master]: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
by Evgeny Zinoviev (Code Review) 22 Jan '19

22 Jan '19

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23178 ) Change subject: ec/lenovo/h8: Implement ACPI methods to set battery thresholds ...................................................................... Patch Set 25: (3 comments) https://review.coreboot.org/#/c/23178/24//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/23178/24//COMMIT_MSG@9 PS24, Line 9: There are two known (yet) different ways to manage battery thresholds. : This patch implements them and adds a way to enable them for : different mainboards. > Are those methods documented somewhere? Is there a specification? No, it's all reverse engineered AFAIK. https://review.coreboot.org/#/c/23178/24//COMMIT_MSG@22 PS24, Line 22: > What do the `_24` and `_b0` in the filename mean? 24 and b0 are EC registers used to control thresholds. We don't have a meaningful names for them as they were reverse-engineered. https://review.coreboot.org/#/c/23178/24//COMMIT_MSG@26 PS24, Line 26: Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 > Please put this right above the Signed-off-by lines. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/23178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Gerrit-Change-Number: 23178 Gerrit-PatchSet: 25 Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 22 Jan 2019 13:08:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
by Evgeny Zinoviev (Code Review) 22 Jan '19

22 Jan '19

Evgeny Zinoviev has uploaded a new patch set (#25) to the change originally created by Alexey Derlaft. ( https://review.coreboot.org/c/coreboot/+/23178 ) Change subject: ec/lenovo/h8: Implement ACPI methods to set battery thresholds ...................................................................... ec/lenovo/h8: Implement ACPI methods to set battery thresholds There are two known (yet) different ways to manage battery thresholds. This patch implements them and adds a way to enable them for different mainboards. Tested on W530 with 4.18.3-gentoo kernel. Works fine with new Linux userspace API for controlling battery thresholds, available since 4.17. (/sys/class/power_supply/BAT0/charge_(start|stop)_threshold). The new API is supported by TLP (you might need to set NATACPI_ENABLE=1 in /etc/tlp.conf). tpacpi-bat works fine too. Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Signed-off-by: Alexey Kharlamov <der(a)2-47.ru> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/acpi/thinkpad.asl A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/acpi/ec.asl M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/acpi/ec.asl M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t420s/acpi/ec.asl M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/acpi/ec.asl M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t530/acpi/ec.asl M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/acpi/ec.asl M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/acpi/ec.asl M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x220/acpi/ec.asl M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x230/acpi/ec.asl 29 files changed, 461 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/23178/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/23178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Gerrit-Change-Number: 23178 Gerrit-PatchSet: 25 Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Felix Held (Code Review) 22 Jan '19

22 Jan '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: Code-Review+1 looks good to me, but should be tested again before i give a +2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Tue, 22 Jan 2019 12:35:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/model_206ax: Use parallel MP init
by Arthur Heymans (Code Review) 22 Jan '19

22 Jan '19

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25618 ) Change subject: cpu/intel/model_206ax: Use parallel MP init ...................................................................... cpu/intel/model_206ax: Use parallel MP init This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25618 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/gen1/smi.h M src/cpu/intel/smm/gen1/smmrelocate.c M src/northbridge/intel/sandybridge/northbridge.c M src/southbridge/intel/common/smi.c 8 files changed, 193 insertions(+), 88 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 11d86cd..1e6a311 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -77,7 +77,6 @@ /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void smm_relocate(void); #endif #endif diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index b30cfa1..cb09d23 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -23,6 +23,7 @@ select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select PARALLEL_MP config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 2bf9d32..f4c5d93 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -22,6 +22,7 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 +#define CORE_THREAD_COUNT_MSR 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) @@ -109,7 +110,6 @@ /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void smm_relocate(void); #endif int get_platform_id(void); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 58aabdb..33ad1e7 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <console/console.h> #include <device/device.h> #include <string.h> @@ -24,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -426,83 +428,6 @@ wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -int cpu_get_apic_id_map(int *apic_id_map) -{ - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core, i, shift = 0; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - if (threads_per_core == 1) - shift++; - - for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; i++) - apic_id_map[i] = i << shift; - - return threads_per_package; -} - -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(struct device *cpu) -{ - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct device_path cpu_path; - struct device *new; - - /* Build the CPU device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads_per_core == 1) - cpu_path.apic.apic_id <<= 1; - - /* Allocate the new CPU device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - - /* Start the new CPU */ - if (is_smp_boot() && !start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } - } -} - static void model_206ax_report(void) { static const char *const mode[] = {"NOT ", ""}; @@ -536,18 +461,12 @@ /* Turn on caching if we haven't already */ x86_enable_cache(); - intel_update_microcode_from_cbfs(); - /* Clear out pending MCEs */ configure_mca(); /* Print infos */ model_206ax_report(); - /* Setup MTRRs based on physical address size */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT @@ -578,9 +497,75 @@ /* Enable Turbo */ enable_turbo(); +} - /* Start up extra cores */ - intel_cores_init(cpu); +/* MP initialization support. */ +static const void *microcode_patch; + +static void pre_mp_init(void) +{ + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + msr_t msr; + int num_threads; + int num_cores; + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_threads = (msr.lo >> 0) & 0xffff; + num_cores = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", + num_cores, num_threads); + + return num_threads; +} + +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} + +static void post_mp_init(void) +{ + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + southbridge_smm_init(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void bsp_init_and_start_aps(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index cc6811f..6d08bb3 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -11,6 +11,10 @@ * GNU General Public License for more details. */ +#include <device/device.h> + +void bsp_init_and_start_aps(struct bus *cpu_bus); + /* These helpers are for performing SMM relocation. */ void southbridge_smm_init(void); void southbridge_trigger_smi(void); @@ -21,3 +25,12 @@ void northbridge_write_smram(u8 smram); bool cpu_has_alternative_smrr(void); + +/* parallel MP helper functions */ +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); +void smm_initialize(void); +void southbridge_smm_clear_state(void); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase); +void smm_relocate(void); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 105b9a4..4b824a5 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -22,10 +22,12 @@ #include <device/device.h> #include <device/pci.h> #include <cpu/x86/cache.h> +#include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <console/console.h> +#include <smp/node.h> #include "smi.h" #define SMRR_SUPPORTED (1 << 11) @@ -349,3 +351,82 @@ northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); } + +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + if (CONFIG_IED_REGION_SIZE != 0) + setup_ied_area(&smm_reloc_params); + + *perm_smbase = smm_reloc_params.smram_base; + *perm_smsize = smm_reloc_params.smram_size; + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +void smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + southbridge_smm_clear_state(); + + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ + smm_initiate_relocation(); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = &smm_reloc_params; + em64t101_smm_state_save_area_t *save_state; + u32 smbase = staggered_smbase; + u32 iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + + /* Make appropriate changes to the save state map. */ + if (CONFIG_IED_REGION_SIZE != 0) + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", + smbase, iedbase); + else + printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", + smbase); + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); + save_state->smbase = smbase; + save_state->iedbase = iedbase; + + /* Write EMRR and SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0) + write_smrr(relo_params); +} + +/* + * The default SMM entry can happen in parallel or serially. If the + * default SMM entry is done in parallel the BSP has already setup + * the saving state to each CPU's MSRs. At least one save state size + * is required for the initial SMM entry for the BSP to determine if + * parallel SMM relocation is even feasible. + */ +void smm_relocate(void) +{ + /* + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation + * shall take place. Run the relocation handler a second time on the + * BSP to do the final move. For APs, a relocation handler always + * needs to be run. + */ + if (!boot_cpu()) + smm_initiate_relocation(); +} diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4a8419a..0d644ca 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -530,7 +530,7 @@ static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index af9dd5d..40f5412 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -154,3 +154,29 @@ "d" (APM_CNT) ); } + +void southbridge_smm_clear_state(void) +{ + u32 smi_en; + + if (IS_ENABLED(CONFIG_ELOG)) + /* Log events from chipset before clearing */ + pch_log_state(); + + printk(BIOS_DEBUG, "Initializing Southbridge SMI...\n"); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); + + smi_en = inl(get_pmbase() + SMI_EN); + if (smi_en & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + printk(BIOS_DEBUG, "\n"); + + /* Dump and clear status registers */ + reset_smi_status(); + reset_pm1_status(); + reset_tco_status(); + reset_gpe0_status(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/25618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Gerrit-Change-Number: 25618 Gerrit-PatchSet: 39 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's
by Arthur Heymans (Code Review) 22 Jan '19

22 Jan '19

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30868 ) Change subject: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's ...................................................................... cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's Intel pineview has the same alternative SMRR MSR and IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for that before enabling this feature. This also exposes a function to fetch whether alternative SMRR MSR's ought to be used. Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30868 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/smm/gen1/smi.h M src/cpu/intel/smm/gen1/smmrelocate.c 2 files changed, 23 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index f4cbbc3..cc6811f 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -19,3 +19,5 @@ u32 northbridge_get_tseg_size(void); int cpu_get_apic_id_map(int *apic_id_map); void northbridge_write_smram(u8 smram); + +bool cpu_has_alternative_smrr(void); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 5667648..105b9a4 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -56,17 +56,31 @@ static struct smm_relocation_params smm_reloc_params; static void *default_smm_area = NULL; -static void write_smrr(struct smm_relocation_params *relo_params) +/* On model_6fx, model_1067x and model_106cx SMRR functions slightly + differently. The MSR are at different location from the rest + and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ +bool cpu_has_alternative_smrr(void) { struct cpuinfo_x86 c; + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return false; + switch (c.x86_model) { + case 0xf: + case 0x17: /* core2 */ + case 0x1c: /* Bonnell */ + return true; + default: + return false; + } +} +static void write_smrr(struct smm_relocation_params *relo_params) +{ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - /* Both model_6fx and model_1067x SMRR function slightly differently - from the rest. The MSR are at different location from the rest - and need to be explicitly enabled. */ - get_fms(&c, cpuid_eax(1)); - if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) { + + if (cpu_has_alternative_smrr()) { msr_t msr; msr = rdmsr(IA32_FEATURE_CONTROL); /* SMRR enabled and feature locked */ @@ -171,7 +185,7 @@ /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */ get_fms(&c, cpuid_eax(1)); - if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) + if (cpu_has_alternative_smrr()) params->smrr_base.lo = (params->smram_base & rmask); else params->smrr_base.lo = (params->smram_base & rmask) -- To view, visit https://review.coreboot.org/c/coreboot/+/30868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa Gerrit-Change-Number: 30868 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/common/smi.c: Remove unused functions
by Paul Menzel (Code Review) 22 Jan '19

22 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30019 ) Change subject: sb/intel/common/smi.c: Remove unused functions ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Gerrit-Change-Number: 30019 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Jan 2019 12:02:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/model_2065x: Put stage cache in TSEG
by Paul Menzel (Code Review) 22 Jan '19

22 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26298 ) Change subject: cpu/intel/model_2065x: Put stage cache in TSEG ...................................................................... Patch Set 41: Has this been tested? -- To view, visit https://review.coreboot.org/c/coreboot/+/26298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Gerrit-Change-Number: 26298 Gerrit-PatchSet: 41 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Jan 2019 12:01:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
by Paul Menzel (Code Review) 22 Jan '19

22 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23178 ) Change subject: ec/lenovo/h8: Implement ACPI methods to set battery thresholds ...................................................................... Patch Set 24: (9 comments) https://review.coreboot.org/#/c/23178/24//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/23178/24//COMMIT_MSG@9 PS24, Line 9: There are two known (yet) different ways to manage battery thresholds. : This patch implements them and adds a way to enable them for : different mainboards. Are those methods documented somewhere? Is there a specification? https://review.coreboot.org/#/c/23178/24//COMMIT_MSG@22 PS24, Line 22: What do the `_24` and `_b0` in the filename mean? https://review.coreboot.org/#/c/23178/24//COMMIT_MSG@26 PS24, Line 26: Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Please put this right above the Signed-off-by lines. https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad.asl File src/ec/lenovo/h8/acpi/thinkpad.asl: https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad.asl… PS24, Line 321: #if IS_ENABLED(CONFIG_H8_HAS_BAT_TRESHOLDS_IMPL) Does this work with the indentation? https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad_bat… File src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl: https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad_bat… PS24, Line 23: /* SetBatteryCharge Start/Stop Capacity Threshold Please add a blank comment line. /* * SetBatteryCharge … https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad_bat… PS24, Line 40: * Bit 31: Error status Align *Error* with *Reserved*? https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad_bat… PS24, Line 137: Bit 8:Batterycharge Add space after colon (:)? https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad_bat… PS24, Line 143: * Bit 31: Error status Align? https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad_bat… File src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl: https://review.coreboot.org/#/c/23178/24/src/ec/lenovo/h8/acpi/thinkpad_bat… PS24, Line 116: Return (TSH1 & ~0x80) Does this also need to be conditioned on the Kconfig option with bit 7? -- To view, visit https://review.coreboot.org/c/coreboot/+/23178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Gerrit-Change-Number: 23178 Gerrit-PatchSet: 24 Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexey Derlaft <derlafff(a)ya.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 22 Jan 2019 11:28:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Angel Pons (Code Review) 22 Jan '19

22 Jan '19

Angel Pons has uploaded a new patch set (#6) to the change originally created by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... lenovo/x230: introduce FHD variant There is a modification for the x230 which uses the 2nd DP from the dock as the integrated panel's connection, which allows using a Full HD (FHD) eDP panel instead of the stock LVDS display. To make this work with coreboot, the internal LVDS connector should be disabled in libgfxinit. The VBT has been modified as well, which allows brightness controls to work out of the box. The modifications done to the VBT are: - Remove the LVDS port entry. - Move the DP-3 (which is the 2nd DP on the dock) entry to the first position on the list. - Set the DP-3 as internally connected. This has been reported to work with panel LP125WF2 SPB4. Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x230/Kconfig.name M src/mainboard/lenovo/x230/Makefile.inc R src/mainboard/lenovo/x230/variants/x230/data.vbt R src/mainboard/lenovo/x230/variants/x230/gma-mainboard.ads A src/mainboard/lenovo/x230/variants/x230_fhd/data.vbt A src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads 7 files changed, 45 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28950/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Angel Pons (Code Review) 22 Jan '19

22 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 5: (1 comment) I was wondering whether GFX_GMA_INTERNAL_IS_EDP would be needed, but I don't think that is the case since "internal" does not exist on nitrocaster. https://review.coreboot.org/#/c/28950/5/src/mainboard/lenovo/x230/Kconfig File src/mainboard/lenovo/x230/Kconfig: https://review.coreboot.org/#/c/28950/5/src/mainboard/lenovo/x230/Kconfig@23 PS5, Line 23: GFX_GMA_INTERNAL_IS_LVDS > only for BOARD_LENOVO_X230 and not for BOARD_LENOVO_X230_FHD Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Tue, 22 Jan 2019 10:07:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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