coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

1 participants
1296 discussions

Change in ...coreboot[master]: soc/intel/denverton_ns: Enable Fast Strings
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25431 ) Change subject: soc/intel/denverton_ns: Enable Fast Strings ...................................................................... soc/intel/denverton_ns: Enable Fast Strings Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/25431 Reviewed-by: Vanny E <vanessa.f.eusebio(a)intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott(a)sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Vanny E: Looks good to me, but someone else must approve Jay Talbott: Looks good to me, but someone else must approve David Guckian: Looks good to me, but someone else must approve diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 676fab7..f954411 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2018 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +40,11 @@ printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Enable Fast Strings */ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= FAST_STRINGS_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 165856f..825d4cf 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -92,6 +92,7 @@ #define PRMRR_SUPPORTED (1 << 12) /* IA32_MISC_ENABLE bits */ +#define FAST_STRINGS_ENABLE_BIT (1 << 0) #define SPEED_STEP_ENABLE_BIT (1 << 16) /* Read BCLK from MSR */ -- To view, visit https://review.coreboot.org/c/coreboot/+/25431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Gerrit-Change-Number: 25431 Gerrit-PatchSet: 8 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/denverton_ns: Add ACPI T-States and P-States
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25430 ) Change subject: soc/intel/denverton_ns: Add ACPI T-States and P-States ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Gerrit-Change-Number: 25430 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 14:01:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/denverton_ns: Enable ACPI using intelblock
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25428 ) Change subject: soc/intel/denverton_ns: Enable ACPI using intelblock ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Gerrit-Change-Number: 25428 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dg <dg1979ie(a)yahoo.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 24 Jan 2019 14:01:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25427 ) Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib ...................................................................... soc/intel/denverton_ns: Rewrite pmutil using pmclib Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/25427 Reviewed-by: David Guckian Reviewed-by: King Sumo <kingsumos(a)gmail.com> Reviewed-by: Vanny E <vanessa.f.eusebio(a)intel.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c 4 files changed, 33 insertions(+), 184 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Vanny E: Looks good to me, but someone else must approve King Sumo: Looks good to me, but someone else must approve David Guckian: Looks good to me, but someone else must approve diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 32d8a76..f6c56cf 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -41,18 +41,6 @@ struct chipset_power_state *fill_power_state(void); /* Power Management Utility Functions. */ -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index ccf0d95..344f8b9 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -19,29 +19,12 @@ #include <arch/io.h> #include <console/console.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> -static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static uint32_t print_smi_status(uint32_t smi_sts) +const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { [2] = "BIOS", @@ -67,93 +50,11 @@ [31] = "LEGACY_USB3", }; - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; } -static uint32_t reset_smi_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS)); - outl(smi_sts, (uint16_t)(pmbase + SMI_STS)); - return smi_sts; -} - -uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); } - -void enable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en |= mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void disable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en &= ~mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void enable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt |= mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -void disable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt &= ~mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -static uint16_t reset_pm1_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS)); - outw(pm1_sts, (uint16_t)(pmbase + PM1_STS)); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char *const pm1_sts_bits[] = { - [0] = "TMROF", [4] = "BM", [5] = "GBL", - [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); } - -void enable_pm1(uint16_t events) -{ - uint16_t pmbase = get_pmbase(); - outw(events, (uint16_t)(pmbase + PM1_EN)); -} - -static uint32_t print_tco_status(uint32_t tco_sts) +const char *const *soc_tco_sts_array(size_t *a) { static const char *const tco_sts_bits[] = { [0] = "NMI2SMI", [1] = "OS_TCO_SMI", @@ -164,17 +65,11 @@ [17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI", }; - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; } -static uint32_t reset_tco_status(void) +uint32_t soc_reset_tco_status(void) { uint16_t tcobase = get_tcobase(); uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS)); @@ -184,35 +79,7 @@ return tco_sts & tco_en; } -uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); } - -void enable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_all_gpe(void) { disable_gpe(~0); } - -static uint32_t reset_gpe_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); - return gpe_sts; -} - -static uint32_t print_gpe_sts(uint32_t gpe_sts) +const char *const *soc_std_gpe_sts_array(size_t *a) { static const char *const gpe_sts_bits[] = { [0] = "GPIO_0", [1] = "GPIO_1", @@ -233,16 +100,8 @@ [30] = "GPIO_30", [31] = "GPIO_31", }; - if (!gpe_sts) - return gpe_sts; - - printk(BIOS_DEBUG, "GPE0a_STS: "); - print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return gpe_sts; + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; } -uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); } - void clear_pmc_status(void) { /* TODO */ } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 85f99d7..e1e7bc4 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <elog.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/pmclib.h> #include <spi-generic.h> #include <soc/iomap.h> #include <soc/soc_util.h> @@ -52,7 +53,7 @@ return 0; } -void southbridge_smi_set_eos(void) { enable_smi(EOS); } +void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); } global_nvs_t *smm_get_gnvs(void) { return gnvs; } @@ -98,7 +99,7 @@ uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); + pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); @@ -131,7 +132,7 @@ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ - disable_all_gpe(); + pmc_disable_all_gpe(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -145,7 +146,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - enable_pm1_control(SLP_EN); + pmc_enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) @@ -158,7 +159,7 @@ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); + pmc_disable_pm1_control(SLP_EN | SLP_TYP); } } @@ -237,11 +238,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); + pmc_disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); + pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_FINALIZE: @@ -268,23 +269,23 @@ static void southbridge_smi_pm1(void) { - uint16_t pm1_sts = clear_pm1_status(); + uint16_t pm1_sts = pmc_clear_pm1_status(); /* While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { // power button pressed - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + pmc_disable_pm1_control(-1UL); + pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -static void southbridge_smi_gpe0(void) { clear_gpe_status(); } +static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); } static void southbridge_smi_tco(void) { - uint32_t tco_sts = clear_tco_status(); + uint32_t tco_sts = pmc_clear_tco_status(); /* Any TCO event? */ if (!tco_sts) @@ -354,7 +355,7 @@ /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = clear_smi_status(); + smi_sts = pmc_clear_smi_status(); /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 9d3fa75..65d2499 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -23,6 +23,7 @@ #include <cpu/x86/smm.h> #include <string.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> @@ -48,10 +49,10 @@ } /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); + pmc_clear_smi_status(); + pmc_clear_pm1_status(); + pmc_clear_tco_status(); + pmc_clear_all_gpe_status(); clear_pmc_status(); } @@ -60,8 +61,8 @@ printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable pcie wake. */ - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - disable_gpe(PME_B0_EN); + pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + pmc_disable_std_gpe(PME_B0_EN); /* Enable SMI generation: * - on APMC writes (io 0xb2) @@ -71,7 +72,7 @@ * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -- To view, visit https://review.coreboot.org/c/coreboot/+/25427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Gerrit-Change-Number: 25427 Gerrit-PatchSet: 8 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25427 ) Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Gerrit-Change-Number: 25427 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 13:59:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/common/block/acpi: fix P-States extra entry
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25429 ) Change subject: soc/intel/common/block/acpi: fix P-States extra entry ...................................................................... soc/intel/common/block/acpi: fix P-States extra entry The ratio_max step is appearing twice when (ratio_max - ratio_min) is evenly divisible by the ratio step. This is because in this case there are no rounding down of ratio_max in the for loop. Thanks Jay Talbott for the step calculation algorithm. Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/25429 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 16 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 0ea6cb9..21d877b 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -299,11 +299,13 @@ int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, num_entries; int ratio, power, clock, clock_max; + bool turbo; coord_type = cpu_get_coord_type(); ratio_min = cpu_get_min_ratio(); ratio_max = cpu_get_max_ratio(); clock_max = (ratio_max * cpu_get_bus_clock()) / KHz; + turbo = (get_turbo_state() == TURBO_ENABLED); /* Calculate CPU TDP in mW */ power_max = cpu_get_power_max(); @@ -321,16 +323,21 @@ /* Determine ratio points */ ratio_step = PSS_RATIO_STEP; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - if (num_entries > PSS_MAX_ENTRIES) { - ratio_step += 1; + do { num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - } + if (((ratio_max - ratio_min) % ratio_step) > 0) + num_entries += 1; + if (turbo) + num_entries += 1; + if (num_entries > PSS_MAX_ENTRIES) + ratio_step += 1; + } while (num_entries > PSS_MAX_ENTRIES); + + /* _PSS package count depends on Turbo */ + acpigen_write_package(num_entries); /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); + if (turbo) { ratio_turbo = cpu_get_max_turbo_ratio(); /* Add entry for Turbo ratio */ @@ -340,9 +347,7 @@ PSS_LATENCY_BUSMASTER,/* lat2 */ ratio_turbo << 8, /* control */ ratio_turbo << 8); /* status */ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); + num_entries -= 1; } /* First regular entry is max non-turbo ratio */ @@ -352,6 +357,7 @@ PSS_LATENCY_BUSMASTER,/* lat2 */ ratio_max << 8, /* control */ ratio_max << 8); /* status */ + num_entries -= 1; /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); -- To view, visit https://review.coreboot.org/c/coreboot/+/25429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Gerrit-Change-Number: 25429 Gerrit-PatchSet: 10 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/common/block/acpi: fix P-States extra entry
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25429 ) Change subject: soc/intel/common/block/acpi: fix P-States extra entry ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Gerrit-Change-Number: 25429 Gerrit-PatchSet: 9 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Jan 2019 13:58:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: ec/kontron: Add support for Kontron kempld
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29476 ) Change subject: ec/kontron: Add support for Kontron kempld ...................................................................... ec/kontron: Add support for Kontron kempld A programmable logic device used by Kontron as EC on their COM express modules. The name `kempld` is taken from Linux kernel sources, as is the I2C driver. The meaning of the acronym is unclear, probably: Kontron Embedded Module PLD. Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/29476 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- A src/ec/kontron/kempld/Kconfig A src/ec/kontron/kempld/Makefile.inc A src/ec/kontron/kempld/chip.h A src/ec/kontron/kempld/early_kempld.c A src/ec/kontron/kempld/kempld.c A src/ec/kontron/kempld/kempld.h A src/ec/kontron/kempld/kempld_i2c.c A src/ec/kontron/kempld/kempld_internal.h 8 files changed, 605 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/src/ec/kontron/kempld/Kconfig b/src/ec/kontron/kempld/Kconfig new file mode 100644 index 0000000..647bd12 --- /dev/null +++ b/src/ec/kontron/kempld/Kconfig @@ -0,0 +1,5 @@ +config EC_KONTRON_KEMPLD + bool + help + Driver for Kontron's express module programmable logic device used + on their COMexpress modules. diff --git a/src/ec/kontron/kempld/Makefile.inc b/src/ec/kontron/kempld/Makefile.inc new file mode 100644 index 0000000..0d59886 --- /dev/null +++ b/src/ec/kontron/kempld/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-$(CONFIG_EC_KONTRON_KEMPLD) += early_kempld.c +ramstage-$(CONFIG_EC_KONTRON_KEMPLD) += early_kempld.c +ramstage-$(CONFIG_EC_KONTRON_KEMPLD) += kempld.c +ramstage-$(CONFIG_EC_KONTRON_KEMPLD) += kempld_i2c.c diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h new file mode 100644 index 0000000..7f06937 --- /dev/null +++ b/src/ec/kontron/kempld/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_KONTRON_KEMPLD_CHIP_H +#define EC_KONTRON_KEMPLD_CHIP_H + +#define KEMPLD_NUM_UARTS 2 + +enum kempld_uart_io { + KEMPLD_UART_3F8 = 0, + KEMPLD_UART_2F8 = 1, + KEMPLD_UART_3E8 = 2, + KEMPLD_UART_2E8 = 3, +}; + +struct kempld_uart { + enum kempld_uart_io io; + unsigned int irq; +}; + +struct ec_kontron_kempld_config { + struct kempld_uart uart[KEMPLD_NUM_UARTS]; +}; + +#endif /* EC_KONTRON_KEMPLD_CHIP_H */ diff --git a/src/ec/kontron/kempld/early_kempld.c b/src/ec/kontron/kempld/early_kempld.c new file mode 100644 index 0000000..773b8b6 --- /dev/null +++ b/src/ec/kontron/kempld/early_kempld.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <delay.h> + +#include "chip.h" +#include "kempld.h" +#include "kempld_internal.h" + +void kempld_write8(const uint8_t addr, const uint8_t data) +{ + outb(addr, KEMPLD_IDX); + outb(data, KEMPLD_DAT); +} + +uint8_t kempld_read8(const uint8_t addr) +{ + outb(addr, KEMPLD_IDX); + return inb(KEMPLD_DAT); +} + +int kempld_get_mutex(int timeout_ms) +{ + while (inb(KEMPLD_IDX) & KEMPLD_MUTEX_KEY && timeout_ms--) + mdelay(1); + return timeout_ms; +} + +void kempld_release_mutex(void) +{ + outb(KEMPLD_MUTEX_KEY, KEMPLD_IDX); +} + +void kempld_enable_uart_for_console(void) +{ + if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + return; + + if (kempld_get_mutex(100) < 0) + return; + + switch (CONFIG_UART_FOR_CONSOLE) { + case 0: + kempld_write8(KEMPLD_UART_0, + KEMPLD_UART_ENABLE | + KEMPLD_UART_3F8 << KEMPLD_UART_IO_SHIFT); + break; + case 1: + kempld_write8(KEMPLD_UART_1, + KEMPLD_UART_ENABLE | + KEMPLD_UART_2F8 << KEMPLD_UART_IO_SHIFT); + break; + default: + break; + } + + kempld_release_mutex(); +} diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c new file mode 100644 index 0000000..19c1880 --- /dev/null +++ b/src/ec/kontron/kempld/kempld.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> + +#include "chip.h" +#include "kempld.h" +#include "kempld_internal.h" + +static void kempld_uart_read_resources(struct device *dev) +{ + static const unsigned int io_addr[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; + + const struct ec_kontron_kempld_config *const config = dev->chip_info; + + struct resource *const res_io = new_resource(dev, 0); + struct resource *const res_irq = new_resource(dev, 1); + const unsigned int uart = dev->path.generic.subid; + if (!config || !res_io || !res_irq || uart >= KEMPLD_NUM_UARTS) + return; + + const enum kempld_uart_io io = config->uart[uart].io; + if (io >= ARRAY_SIZE(io_addr)) { + printk(BIOS_ERR, "KEMPLD: Bad io value '%d' for UART#%u\n.", + io, uart); + dev->enabled = false; + return; + } + + const int irq = config->uart[uart].irq; + if (irq >= 16) { + printk(BIOS_ERR, "KEMPLD: Bad irq value '%d' for UART#%u\n.", + irq, uart); + dev->enabled = false; + return; + } + + res_io->base = io_addr[io]; + res_io->size = 8; + res_io->flags = IORESOURCE_IO | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + res_irq->base = irq; + res_irq->size = 1; + res_irq->flags = IORESOURCE_IO | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + if (kempld_get_mutex(100) < 0) + return; + + const uint8_t reg = uart ? KEMPLD_UART_1 : KEMPLD_UART_0; + const uint8_t val = kempld_read8(reg); + kempld_write8(reg, (val & ~(KEMPLD_UART_IO_MASK | KEMPLD_UART_IRQ_MASK)) + | io << KEMPLD_UART_IO_SHIFT + | irq << KEMPLD_UART_IRQ_SHIFT); + + kempld_release_mutex(); +} + +static void kempld_uart_enable_resources(struct device *dev) +{ + if (kempld_get_mutex(100) < 0) + return; + + const unsigned int uart = dev->path.generic.subid; + const uint8_t reg = uart ? KEMPLD_UART_1 : KEMPLD_UART_0; + kempld_write8(reg, kempld_read8(reg) | KEMPLD_UART_ENABLE); + + kempld_release_mutex(); +} + +static struct device_operations kempld_uart_ops = { + .read_resources = kempld_uart_read_resources, + .enable_resources = kempld_uart_enable_resources, +}; + +static void kempld_enable_dev(struct device *const dev) +{ + if (dev->path.type == DEVICE_PATH_GENERIC) { + switch (dev->path.generic.id) { + case 0: + if (dev->path.generic.subid < KEMPLD_NUM_UARTS) { + dev->ops = &kempld_uart_ops; + break; + } + case 1: + if (dev->path.generic.subid == 0) { + kempld_i2c_device_init(dev); + break; + } + default: + printk(BIOS_WARNING, + "KEMPLD: Spurious device %s.\n", + dev_path(dev)); + break; + } + } +} + +struct chip_operations ec_kontron_kempld_ops = { + CHIP_NAME("Kontron KEMPLD") + .enable_dev = kempld_enable_dev, +}; diff --git a/src/ec/kontron/kempld/kempld.h b/src/ec/kontron/kempld/kempld.h new file mode 100644 index 0000000..fe5f54f --- /dev/null +++ b/src/ec/kontron/kempld/kempld.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_KONTRON_KEMPLD_H +#define EC_KONTRON_KEMPLD_H + +#include <stdint.h> + +void kempld_write8(uint8_t addr, uint8_t data); +uint8_t kempld_read8(uint8_t addr); + +int kempld_get_mutex(int timeout_ms); +void kempld_release_mutex(void); + +void kempld_enable_uart_for_console(void); + +#endif /* EC_KONTRON_KEMPLD_H */ diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c new file mode 100644 index 0000000..fdc0b50 --- /dev/null +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -0,0 +1,296 @@ +/* + * I2C bus driver for Kontron COM modules + * + * Copyright (C) 2017 secunet Security Networks AG + * + * Based on the similar driver in Linux: + * + * Copyright (c) 2010-2013 Kontron Europe GmbH + * Author: Michael Brunner <michael.brunner(a)kontron.com> + * + * The driver is based on the i2c-ocores driver by Peter Korsgaard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_bus.h> +#include <timer.h> +#include <delay.h> + +#include "kempld.h" +#include "kempld_internal.h" + +#define KEMPLD_I2C_PRELOW 0x0b +#define KEMPLD_I2C_PREHIGH 0x0c +#define KEMPLD_I2C_DATA 0x0e + +#define KEMPLD_I2C_CTRL 0x0d +#define I2C_CTRL_IEN 0x40 +#define I2C_CTRL_EN 0x80 + +#define KEMPLD_I2C_STAT 0x0f +#define I2C_STAT_IF 0x01 +#define I2C_STAT_TIP 0x02 +#define I2C_STAT_ARBLOST 0x20 +#define I2C_STAT_BUSY 0x40 +#define I2C_STAT_NACK 0x80 + +#define KEMPLD_I2C_CMD 0x0f +#define I2C_CMD_START 0x91 +#define I2C_CMD_STOP 0x41 +#define I2C_CMD_READ 0x21 +#define I2C_CMD_WRITE 0x11 +#define I2C_CMD_READ_ACK 0x21 +#define I2C_CMD_READ_NACK 0x29 +#define I2C_CMD_IACK 0x01 + +#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ +#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ + +#define EIO 5 +#define ENXIO 6 +#define EAGAIN 11 +#define EBUSY 16 +#define ETIMEDOUT 110 + +enum kempld_i2c_state { + STATE_DONE = 0, + STATE_INIT, + STATE_ADDR, + STATE_ADDR10, + STATE_START, + STATE_WRITE, + STATE_READ, + STATE_ERROR, +}; + +struct kempld_i2c_data { + const struct i2c_msg *msg; + size_t pos; + size_t nmsgs; + enum kempld_i2c_state state; +}; + +/* + * kempld_get_mutex must be called prior to calling this function. + */ +static int kempld_i2c_process(struct kempld_i2c_data *const i2c) +{ + u8 stat = kempld_read8(KEMPLD_I2C_STAT); + const struct i2c_msg *msg = i2c->msg; + u8 addr; + + /* Ready? */ + if (stat & I2C_STAT_TIP) + return -EBUSY; + + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { + /* Stop has been sent */ + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_IACK); + if (i2c->state == STATE_ERROR) + return -EIO; + return 0; + } + + /* Error? */ + if (stat & I2C_STAT_ARBLOST) { + i2c->state = STATE_ERROR; + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + return -EAGAIN; + } + + if (i2c->state == STATE_INIT) { + if (stat & I2C_STAT_BUSY) + return -EBUSY; + + i2c->state = STATE_ADDR; + } + + if (i2c->state == STATE_ADDR) { + /* 10 bit address? */ + if (i2c->msg->flags & I2C_M_TEN) { + addr = 0xf0 | ((i2c->msg->slave >> 7) & 0x6); + i2c->state = STATE_ADDR10; + } else { + addr = (i2c->msg->slave << 1); + i2c->state = STATE_START; + } + + /* Set read bit if necessary */ + addr |= (i2c->msg->flags & I2C_M_RD) ? 1 : 0; + + kempld_write8(KEMPLD_I2C_DATA, addr); + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_START); + + return 0; + } + + /* Second part of 10 bit addressing */ + if (i2c->state == STATE_ADDR10) { + kempld_write8(KEMPLD_I2C_DATA, i2c->msg->slave & 0xff); + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_WRITE); + + i2c->state = STATE_START; + return 0; + } + + if (i2c->state == STATE_START || i2c->state == STATE_WRITE) { + i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; + + if (stat & I2C_STAT_NACK) { + i2c->state = STATE_ERROR; + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + return -ENXIO; + } + } else { + msg->buf[i2c->pos++] = kempld_read8(KEMPLD_I2C_DATA); + } + + if (i2c->pos >= msg->len) { + i2c->nmsgs--; + i2c->msg++; + i2c->pos = 0; + msg = i2c->msg; + + if (i2c->nmsgs) { + if (!(msg->flags & I2C_M_NOSTART)) { + i2c->state = STATE_ADDR; + return 0; + } else { + i2c->state = (msg->flags & I2C_M_RD) + ? STATE_READ : STATE_WRITE; + } + } else { + i2c->state = STATE_DONE; + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + return 0; + } + } + + if (i2c->state == STATE_READ) { + kempld_write8(KEMPLD_I2C_CMD, i2c->pos == (msg->len - 1) ? + I2C_CMD_READ_NACK : I2C_CMD_READ_ACK); + } else { + kempld_write8(KEMPLD_I2C_DATA, msg->buf[i2c->pos++]); + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_WRITE); + } + + return 0; +} + +static int kempld_i2c_xfer(struct device *const dev, + const struct i2c_msg *const msgs, + const size_t num) +{ + struct kempld_i2c_data i2c; + struct stopwatch sw; + int ret; + + if (kempld_get_mutex(100) < 0) + return -ENXIO; + + i2c.msg = msgs; + i2c.pos = 0; + i2c.nmsgs = num; + i2c.state = STATE_INIT; + + /* Handle the transfer */ + stopwatch_init_msecs_expire(&sw, 1000); + while (!stopwatch_expired(&sw)) { + ret = kempld_i2c_process(&i2c); + + if (i2c.state == STATE_DONE || i2c.state == STATE_ERROR) { + if (i2c.state == STATE_DONE) { + printk(BIOS_SPEW, "kempld_i2c: Processed %zu segments.\n", num); + ret = 0; + } else { + printk(BIOS_INFO, "kempld_i2c: Transfer failed.\n"); + } + goto _release; + } + + if (ret == 0) + stopwatch_init_msecs_expire(&sw, 1000); + + udelay(10); + } + + i2c.state = STATE_ERROR; + ret = -ETIMEDOUT; + printk(BIOS_INFO, "kempld_i2c: Transfer failed.\n"); + +_release: + kempld_release_mutex(); + return ret; +} + +static const struct i2c_bus_operations kempld_i2c_bus_ops = { + .transfer = kempld_i2c_xfer, +}; + +static struct device_operations kempld_i2c_dev_ops = { + .scan_bus = &scan_smbus, + .ops_i2c_bus = &kempld_i2c_bus_ops, +}; + +void kempld_i2c_device_init(struct device *const dev) +{ + u16 prescale_corr; + long prescale; + u8 ctrl; + u8 stat; + u8 cfg; + + if (kempld_get_mutex(100) < 0) + return; + + /* Make sure the device is disabled */ + ctrl = kempld_read8(KEMPLD_I2C_CTRL); + ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); + kempld_write8(KEMPLD_I2C_CTRL, ctrl); + + const u8 spec_major = KEMPLD_SPEC_GET_MAJOR(kempld_read8(KEMPLD_SPEC)); + if (spec_major == 1) + prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 5) - 1000; + else + prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 4) - 3000; + + if (prescale < 0) + prescale = 0; + + /* Round to the best matching value */ + prescale_corr = prescale / 1000; + if (prescale % 1000 >= 500) + prescale_corr++; + + kempld_write8(KEMPLD_I2C_PRELOW, prescale_corr & 0xff); + kempld_write8(KEMPLD_I2C_PREHIGH, prescale_corr >> 8); + + /* Disable I2C bus output on GPIO pins */ + cfg = kempld_read8(KEMPLD_CFG); + cfg &= ~KEMPLD_CFG_GPIO_I2C_MUX; + kempld_write8(KEMPLD_CFG, cfg); + + /* Enable the device */ + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_IACK); + ctrl |= I2C_CTRL_EN; + kempld_write8(KEMPLD_I2C_CTRL, ctrl); + + stat = kempld_read8(KEMPLD_I2C_STAT); + if (stat & I2C_STAT_BUSY) + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + + dev->ops = &kempld_i2c_dev_ops; + + kempld_release_mutex(); +} diff --git a/src/ec/kontron/kempld/kempld_internal.h b/src/ec/kontron/kempld/kempld_internal.h new file mode 100644 index 0000000..93351ce --- /dev/null +++ b/src/ec/kontron/kempld/kempld_internal.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_KONTRON_KEMPLD_INTERNAL_H +#define EC_KONTRON_KEMPLD_INTERNAL_H + +#include <device/device.h> + +/* i/o ports */ +#define KEMPLD_IDX 0xa80 +#define KEMPLD_MUTEX_KEY 0x80 +#define KEMPLD_DAT 0xa81 + +/* indexed registers */ +#define KEMPLD_SPEC 0x06 +#define KEMPLD_SPEC_GET_MINOR(x) (x & 0x0f) +#define KEMPLD_SPEC_GET_MAJOR(x) (x >> 4 & 0x0f) + +#define KEMPLD_CFG 0x37 +#define KEMPLD_CFG_GPIO_I2C_MUX (1 << 0) + +#define KEMPLD_UART_0 0x30 +#define KEMPLD_UART_1 0x31 +#define KEMPLD_UART_IRQ_SHIFT 0 +#define KEMPLD_UART_IRQ_MASK (0xf << KEMPLD_UART_IRQ_SHIFT) +#define KEMPLD_UART_IO_SHIFT 4 +#define KEMPLD_UART_IO_MASK (0x3 << KEMPLD_UART_IO_SHIFT) +#define KEMPLD_UART_ENABLE 0x80 + +#define KEMPLD_CLK 33333333 /* 33MHz */ + +void kempld_i2c_device_init(struct device *const dev); + +#endif /* EC_KONTRON_KEMPLD_INTERNAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36 Gerrit-Change-Number: 29476 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/google/sarien: Fix recovery mode detection
by Duncan Laurie (Code Review) 24 Jan '19

24 Jan '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31043 Change subject: mb/google/sarien: Fix recovery mode detection ...................................................................... mb/google/sarien: Fix recovery mode detection In order to support the physical recovery GPIO on sarien it needs to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO number in the coreboot table appropriately so that depthcharge can correctly determine the GPIO number. The same is done for the write protect GPIO in this table. Additionally since we are reading a recovery request from H1 it needs to cache the result since H1 will only return true on the first request. All subsequent queries to H1 will not indicate recovery. Add a CAR global here to keep track of the state and only read it from H1 the first time. BUG=b:121380403 TEST=test_that DUT firmware_DevMode Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/chromeos.c 2 files changed, 32 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/31043/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index ff2f678..f93910f 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -100,5 +100,6 @@ select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH + select VBOOT_PHYSICAL_REC_SWITCH endif # BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 8b2090e..0ea237a 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -14,6 +14,7 @@ */ #include <arch/acpi.h> +#include <arch/early_variables.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> @@ -21,12 +22,20 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +enum rec_mode_state { + REC_MODE_UNINITIALIZED, + REC_MODE_NOT_REQUESTED, + REC_MODE_REQUESTED, +}; +static enum rec_mode_state saved_rec_mode CAR_GLOBAL; void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, + {GPIO_REC_MODE, ACTIVE_LOW, get_recovery_mode_switch(), + "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, @@ -72,16 +81,30 @@ int get_recovery_mode_switch(void) { - uint8_t recovery_button_state; - int recovery_mode_switch = 0; + enum rec_mode_state state = car_get_var(saved_rec_mode); + uint8_t recovery_button_state = 0; + /* Check the global variable first. */ + if (state == REC_MODE_NOT_REQUESTED) + return 0; + else if (state == REC_MODE_REQUESTED) + return 1; + + state = REC_MODE_NOT_REQUESTED; + + /* Read state from the GPIO controlled by servo. */ if (cros_get_gpio_value(CROS_GPIO_REC)) - recovery_mode_switch = 1; + state = REC_MODE_REQUESTED; + /* Read one-time recovery request from cr50. */ else if (tlcl_cr50_get_recovery_button(&recovery_button_state) - == TPM_SUCCESS) - recovery_mode_switch = recovery_button_state; + == TPM_SUCCESS) + state = recovery_button_state ? + REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; - return recovery_mode_switch; + /* Store the state in case this is called again in verstage. */ + car_set_var(saved_rec_mode, state); + + return state == REC_MODE_REQUESTED; } int get_lid_switch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421 Gerrit-Change-Number: 31043 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mb/google/octopus/bobba: Add support to handle PEN_EJECT event
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30108 ) Change subject: mb/google/octopus/bobba: Add support to handle PEN_EJECT event ...................................................................... mb/google/octopus/bobba: Add support to handle PEN_EJECT event Enable gpio_keys driver for bobba and add required configuration in the device tree to handle the pen eject event. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder. Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/30108 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bobba/overridetree.cb 3 files changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index a237741..50e96a6 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -3,6 +3,7 @@ def_bool n select SOC_INTEL_GLK select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index d23774d..5326118 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -210,7 +210,8 @@ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ /* GPIO_144 -- PEN_EJECT(wake) */ - PAD_CFG_GPI_SCI_HIGH(GPIO_144, UP_20K, DEEP, LEVEL), + PAD_CFG_GPI_SCI_HIGH_DEBEN(GPIO_144, UP_20K, DEEP, EDGE_SINGLE, + DEBOUNCE_256_RTC), /* GPIO_145 -- PEN_EJECT(notifications) */ PAD_CFG_GPI_GPIO_DRIVER(GPIO_145, UP_20K, DEEP), PAD_NC(GPIO_146, UP_20K),/* GPIO_146 -- unused */ diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 04dc768..cd26fab 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -97,6 +97,18 @@ register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_145)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.is_wakeup_source" = "1" + register "key.wake" = "GPE0_DW2_04" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + device generic 0 on end + end end # - I2C 0 device pci 17.1 on chip drivers/i2c/da7219 -- To view, visit https://review.coreboot.org/c/coreboot/+/30108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d Gerrit-Change-Number: 30108 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2019