coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: sdm845: Add UART support
by T.Michael Turney (Code Review) 24 Jan '19

24 Jan '19

Hello mturney mturney, Mukesh Savaliya, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25373 to look at the new patch set (#64). Change subject: sdm845: Add UART support ...................................................................... sdm845: Add UART support TEST=build & run Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1 Signed-off-by: Mukesh Savaliya <msavaliy(a)codeaurora.org> --- M src/mainboard/google/cheza/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/qualcomm/sdm845/Makefile.inc A src/soc/qualcomm/sdm845/uart.c 4 files changed, 275 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/25373/64 -- To view, visit https://review.coreboot.org/c/coreboot/+/25373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1 Gerrit-Change-Number: 25373 Gerrit-PatchSet: 64 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: HACK sdm845 soc/qualcomm/clocks
by T.Michael Turney (Code Review) 24 Jan '19

24 Jan '19

Hello mturney mturney, Julius Werner, David Dai, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29489 to look at the new patch set (#22). Change subject: HACK sdm845 soc/qualcomm/clocks ...................................................................... HACK sdm845 soc/qualcomm/clocks Hack patch to enable qup clock branches Change-Id: If34415ccc35f6e66a5c313890c9d062d7bb51f6b Signed-off-by: David Dai <daidavid1(a)codeaurora.org> --- M src/soc/qualcomm/sdm845/clock.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/29489/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/29489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34415ccc35f6e66a5c313890c9d062d7bb51f6b Gerrit-Change-Number: 29489 Gerrit-PatchSet: 22 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: David Dai <daidavid1(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform DDR init
by T.Michael Turney (Code Review) 24 Jan '19

24 Jan '19

Hello mturney mturney, Julius Werner, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25208 to look at the new patch set (#69). Change subject: sdm845: Add QCLib to RomStage to perform DDR init ...................................................................... sdm845: Add QCLib to RomStage to perform DDR init CB acts as I/O handler for QCLib (e.g. DDR training data) This interface allows bi-directional data flow between CB and QCLib Tested and working interfaces: DDR Training data QCLib serial console output DDR Information (base & size) limits cfg data TEST=build & run Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/mainboard/google/cheza/chromeos.fmd M src/mainboard/google/cheza/romstage.c M src/soc/qualcomm/sdm845/Kconfig M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/mmu.h A src/soc/qualcomm/sdm845/include/soc/qclib.h M src/soc/qualcomm/sdm845/include/soc/symbols.h M src/soc/qualcomm/sdm845/mmu.c A src/soc/qualcomm/sdm845/qclib_execute.c M src/soc/qualcomm/sdm845/soc.c 11 files changed, 460 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/25208/69 -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 69 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: util/kconfig: Implement Ada spec generation
by Nico Huber (Code Review) 24 Jan '19

24 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30583 Change subject: util/kconfig: Implement Ada spec generation ...................................................................... util/kconfig: Implement Ada spec generation Write Kconfig values into an Ada spec file alongside the usual C header. Change-Id: Ic58e4e81179214ef66c26a8a8614fbb5794c6a9c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/kconfig/confdata.c 1 file changed, 129 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30583/1 diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index fc4a07a..a4c602c 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -634,6 +634,99 @@ }; /* + * Ada spec printer + */ +static void +spec_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg) +{ + switch (sym->type) { + case S_BOOLEAN: + case S_TRISTATE: + switch (*value) { + case 'n': + if (getenv("KCONFIG_NEGATIVES")) { + fprintf(fp, + " %-37s : constant boolean := false;\n", + sym->name); + } + break; + case 'm': + fprintf(fp, " %s_MODULE : constant boolean := true;\n", + sym->name); + break; + default: + fprintf(fp, " %-37s : constant boolean := true;\n", + sym->name); + break; + } + break; + case S_HEX: { + unsigned int hexlen; + + if (!value || (value[0] == '\0')) + value = "0"; + else if (value[0] == '0' && (value[1] == 'x' || value[1] == 'X')) + value += 2; + + fprintf(fp, " %-37s : constant := 16#", + sym->name); + for (hexlen = strlen(value); hexlen > 0;) { + const unsigned int len = hexlen % 4 ? : 4; + char quad[] = "0000"; + unsigned int i; + + for (i = 0; i < len; ++i) + quad[4 - len + i] = value[i]; + fprintf(fp, "%s", quad); + + value += len; + hexlen -= len; + if (hexlen > 0) + fprintf(fp, "_"); + } + fprintf(fp, "#;\n"); + break; + } + case S_INT: + if (!value || (value[0] == '\0')) + value = "0"; + fprintf(fp, " %-37s : constant := %s;\n", sym->name, value); + break; + case S_STRING: + fprintf(fp, " %-37s : constant string := %s;\n", sym->name, value); + break; + default: + break; + } +} + +static void +spec_print_comment(FILE *fp, const char *value, void *arg) +{ + const char *p = value; + size_t l; + + for (;;) { + l = strcspn(p, "\n"); + fprintf(fp, "--"); + if (l) { + fprintf(fp, " "); + xfwrite(p, l, 1, fp); + p += l; + } + fprintf(fp, "\n"); + if (*p++ == '\0') + break; + } +} + +static struct conf_printer spec_printer_cb = +{ + .print_symbol = spec_print_symbol, + .print_comment = spec_print_comment, +}; + +/* * Tristate printer * * This printer is used when generating the `include/config/tristate.conf' file. @@ -985,7 +1078,7 @@ { struct symbol *sym; const char *name; - FILE *out, *tristate, *out_h; + FILE *out, *tristate, *out_h, *out_ads; int i; int print_negatives; @@ -1045,12 +1138,36 @@ return 1; } + char *tmpconfig_ads = malloc(PATH_MAX); + if (getenv("COREBOOT_BUILD_DIR")) { + sprintf(tmpconfig_ads, "%s/.tmpconfig_tristate.XXXXXX", + getenv("COREBOOT_BUILD_DIR")); + } else { + sprintf(tmpconfig_ads, ".tmpconfig_tristate.XXXXXX"); + } + if ((i = mkstemp(tmpconfig_ads)) == -1) + return 1; + out_ads = fdopen(i, "w"); + if (!out_ads) { + fclose(out_h); + fclose(out); + fclose(tristate); + return 1; + } + conf_write_heading(out, &kconfig_printer_cb, NULL); conf_write_heading(tristate, &tristate_printer_cb, NULL); conf_write_heading(out_h, &header_printer_cb, NULL); + conf_write_heading(out_ads, &spec_printer_cb, NULL); + + const char *package = getenv("KCONFIG_PACKAGE"); + if (!package) + package = "KConfig"; + fprintf(out_ads, "\npackage %s is\n\n", package); + for_all_symbols(i, sym) { sym_calc_value(sym); if (!sym->name) @@ -1072,11 +1189,22 @@ conf_write_symbol(tristate, sym, &tristate_printer_cb, print_negatives?NULL:(void *)1); conf_write_symbol(out_h, sym, &header_printer_cb, NULL); + + conf_write_symbol(out_ads, sym, &spec_printer_cb, NULL); } + + fprintf(out_ads, "\nend %s;\n", package); + fclose(out); fclose(tristate); fclose(out_h); + fclose(out_ads); + name = getenv("KCONFIG_AUTOADS"); + if (!name) + name = "include/generated/autoconf.ads"; + if (rename(tmpconfig_ads, name)) + return 1; name = getenv("KCONFIG_AUTOHEADER"); if (!name) name = "include/generated/autoconf.h"; -- To view, visit https://review.coreboot.org/c/coreboot/+/30583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic58e4e81179214ef66c26a8a8614fbb5794c6a9c Gerrit-Change-Number: 30583 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Angel Pons (Code Review) 24 Jan '19

24 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: > Patch Set 6: > > > Patch Set 6: -Code-Review > > > > > On the device with FHD-mod booting works as well, but graphical output of coreboot, seabios and grub is only visible if an additional external monitor is attached via VGA or DP. The internal FHD panel becomes active as soon as the linux kernel takes over. Right now I am unsure if this is due to misconfiguration on my part or if coreboot/libgfxinit needs to be told to use eDP1 for output on modded devices. Hints for further tests appreciated. > > > > Can you test revision 5 of the patch? I haven't looked into libgfxinit, so it might be that GFX_GMA_INTERNAL_IS_LVDS is used to determine which backlight interface to use > > I have tried reversion 5 without success > After reading Documentation/gfx/libgfxinit.md I also tried explicitly declaring FX_GMA_INTERNAL_IS_EDP (which should not be necessary since it is the default) > I also tried moving DP3 to the top of the list of ports to probe in src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads but that did not change anything either > > any other ideas? How did you download revision 5? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 20:42:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs
by Daniel Kurtz (Code Review) 24 Jan '19

24 Jan '19

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30999 to review the following change. Change subject: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs ...................................................................... mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs FT4 has a strange property where whenever the debounce registers for any one gpio are changed, the FT4 disables interrupt propagation for ALL gpio irqs for ~4ms. In other words, if an edge interrupt of one gpio happens exactly during this debounce-irq-off window immediately following the configuration of another gpio, the interrupt will be lost. It is quite difficult to deal with this in the kernel, since during kernel boot time, drivers & devices are probed asynchronously, meaning it may happen that an already loaded driver may miss an interrupt when some later driver is being probed and configuring its gpio interrupt. To eliminate this possibility, we pre-configure the debounce registers in ram stage for all gpios that will be used as irqs later by the kernel using the same configuration as used by the kernel, as per this table: IRQ Debounce Edge Remove Glitch Level High Preserve Low Glitch Level Low Preserve High Glitch Note that for GPIO9 we re-configure debounce in RAM section, since this GPIO was originally configured without debounce in bootblock, which is not changeable for devices with WP RO BIOS. So the setting must also be reconfigured in RAM to ensure it happens in RW BIOS. Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: Ic1bd269c196ca9b48157e177fd5834e2f5d5703a --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30999/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index e9ae28c..19dbc41 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -35,6 +35,7 @@ /* GPIO_9 - H1_PCH_INT_ODL, SCI */ PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), + PAD_DEBOUNCE(GPIO_9, REMOVE_GLITCH, DEBOUNCE_DISABLED), /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), @@ -110,6 +111,7 @@ /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW), + PAD_DEBOUNCE(GPIO_5, PRESERVE_HIGH_GLITCH, DEBOUNCE_DISABLED), /* GPIO_7 - APU_PWROK_OD (currently not used) */ PAD_GPI(GPIO_7, PULL_UP), @@ -117,11 +119,15 @@ /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ PAD_GPI(GPIO_8, PULL_UP), + /* GPIO_9 - H1_PCH_INT_ODL, SCI */ + PAD_DEBOUNCE(GPIO_9, REMOVE_GLITCH, DEBOUNCE_DISABLED), + /* GPIO_10 - SLP_S0_L (currently not used) */ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ PAD_SCI(GPIO_11, PULL_UP, EDGE_LOW), + PAD_DEBOUNCE(GPIO_11, REMOVE_GLITCH, DEBOUNCE_DISABLED), /* GPIO_12 - EN_PP3300_TRACKPAD */ PAD_GPO(GPIO_12, HIGH), @@ -131,6 +137,7 @@ /* GPIO_14 - APU_HP_INT_ODL, SCI */ PAD_SCI(GPIO_14, PULL_UP, EDGE_LOW), + PAD_DEBOUNCE(GPIO_14, REMOVE_GLITCH, DEBOUNCE_DISABLED), /* GPIO_16 - USB_C0_OC_L */ PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), -- To view, visit https://review.coreboot.org/c/coreboot/+/30999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bd269c196ca9b48157e177fd5834e2f5d5703a Gerrit-Change-Number: 30999 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs
by Daniel Kurtz (Code Review) 24 Jan '19

24 Jan '19

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31000 to review the following change. Change subject: soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs ...................................................................... soc/amd/stoneyridge/gpio: Disable mask_sts when configuring GPIOs Disable mask_sts and GPIO interrupt enable when confiuring GPIOs. The mask_sts bits control a feature that temporarily disables GPIO interrupt delivery for ALL GPIOs whenever the debounce registers of any one GPIO are changed. This feature is supposed to eliminate the possibility of spurious interrupts when changing debounce. The period for which interrupts are disabled is about 4 ms. This feature is not needed when configuring GPIOs in coreboot for we do not expect to have any active GPIO interrupt sources at this point. Furthermore, we also disable IRQ interrupts to elimintate the possibility of a spurious event while mask_sts is disabled. Together this allows us to safely and quickly configure the gpio debounce registers while configuring GPIOs. Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: I9cd1f809687e7933ffbf7a83b69d603104d66bee --- M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31000/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 955cc6a..fc7ed67 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -227,6 +227,23 @@ uint32_t mask, bit_edge, bit_level; uint8_t mux, index, gpio; int gevent_num; + uint32_t *gpio_xfc; + uint32_t gpio_xfc_init; + + /* + * Disable hardware "irq disable on debounce write" feature while + * configuring GPIOs. This avoids needing to wait 4 ms after + * configuring the debounce registers on any gpio. If we don't do this + * then modifying debounce registers would cause irq enable bits to + * read as 0, potentially permanently disabling irqs during RMW + * operations. This is safe to do here, since no GPIO interrupts are + * disabled at this point (and we explicitly disable them to avoid any + * spurious IRQs due to changing debounce settings). + */ + gpio_xfc = (uint32_t *)(uintptr_t)GPIO_WAKE_INTER_MASTER_SWITCH; + gpio_xfc_init = read32(gpio_xfc); + write32(gpio_xfc, + gpio_xfc_init & ~(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN)); direction = 0; edge_level = 0; @@ -297,6 +314,8 @@ /* Set all SCI trigger level (edge/level) */ mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_LEVEL), edge_level, mask); + + write32(gpio_xfc, gpio_xfc_init); } /* diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 47eae84..c9e9b16 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -182,6 +182,11 @@ #define GPIO_147 147 #define GPIO_148 148 +/* GPIOxFC GPIO_Wake_Inter_Master Switch */ +#define GPIO_WAKE_INTER_MASTER_SWITCH (AMD_SB_ACPI_MMIO_ADDR + 0x15fc) +# define GPIO_INTERRUPT_EN (1 << 30) +# define GPIO_MASK_STS_EN (1 << 28) + #define I2C0_SCL_PIN GPIO_145 #define I2C1_SCL_PIN GPIO_147 #define I2C2_SCL_PIN GPIO_113 -- To view, visit https://review.coreboot.org/c/coreboot/+/31000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cd1f809687e7933ffbf7a83b69d603104d66bee Gerrit-Change-Number: 31000 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Felix Held (Code Review) 24 Jan '19

24 Jan '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: > I have tried reversion 5 without success > After reading Documentation/gfx/libgfxinit.md I also tried explicitly declaring FX_GMA_INTERNAL_IS_EDP (which should not be necessary since it is the default) > I also tried moving DP3 to the top of the list of ports to probe in src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads but that did not change anything either > > any other ideas? I'm out of ideas what the problem might be then tbh. Let's hope that someone who knows more about that area of coreboot will chime in and find a solution to this problem -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 16:23:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Kilian Neuner (Code Review) 24 Jan '19

24 Jan '19

Kilian Neuner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 6: > Patch Set 6: -Code-Review > > > On the device with FHD-mod booting works as well, but graphical output of coreboot, seabios and grub is only visible if an additional external monitor is attached via VGA or DP. The internal FHD panel becomes active as soon as the linux kernel takes over. Right now I am unsure if this is due to misconfiguration on my part or if coreboot/libgfxinit needs to be told to use eDP1 for output on modded devices. Hints for further tests appreciated. > > Can you test revision 5 of the patch? I haven't looked into libgfxinit, so it might be that GFX_GMA_INTERNAL_IS_LVDS is used to determine which backlight interface to use I have tried reversion 5 without success After reading Documentation/gfx/libgfxinit.md I also tried explicitly declaring FX_GMA_INTERNAL_IS_EDP (which should not be necessary since it is the default) I also tried moving DP3 to the top of the list of ports to probe in src/mainboard/lenovo/x230/variants/x230_fhd/gma-mainboard.ads but that did not change anything either any other ideas? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Jan 2019 15:52:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton_ns: Enable ACPI using intelblock
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25428 ) Change subject: soc/intel/denverton_ns: Enable ACPI using intelblock ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Gerrit-Change-Number: 25428 Gerrit-PatchSet: 9 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dg <dg1979ie(a)yahoo.com> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 24 Jan 2019 15:35:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2019