coreboot-gerrit January 2019

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Change in ...coreboot[master]: drivers/generic/gpio_keys: Add trigger for wakeup event action
by Karthik Ramasubramanian (Code Review) 24 Jan '19

24 Jan '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30451 to review the following change. Change subject: drivers/generic/gpio_keys: Add trigger for wakeup event action ...................................................................... drivers/generic/gpio_keys: Add trigger for wakeup event action Currently without any trigger the wakeup event is generated on both the rising and falling edges of the GPIO input. Add support to specify the trigger explicitly so that the configuration can be passed to the kernel. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder and ejected from its holder. Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> --- M src/drivers/generic/gpio_keys/chip.h M src/drivers/generic/gpio_keys/gpio_keys.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/30451/1 diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 818f14c..88a3b35 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -30,6 +30,13 @@ SW_PEN_INSERTED = 0xf, }; +/* Trigger for wakeup event action */ +enum { + EV_ACT_ANY, + EV_ACT_ASSERTED, + EV_ACT_DEASSERTED, +}; + /* Details of the child node defining key */ struct key_info { /* Device name of the child node - Mandatory */ @@ -47,6 +54,8 @@ bool is_wakeup_source; /* Wake GPE */ unsigned int wake; + /* Trigger for Wakeup Event Action */ + unsigned int wakeup_event_action; /* Can this key be disabled? */ bool can_be_disabled; /* Debounce interval time in milliseconds */ diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index 5ecb63e..63f53fe 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -45,6 +45,10 @@ key->is_wakeup_source); if (key->wake) acpigen_write_PRW(key->wake, 3); + if (key->wakeup_event_action) + acpi_dp_add_integer(dsd, "wakeup-event-action", + key->wakeup_event_action); + if (key->can_be_disabled) acpi_dp_add_integer(dsd, "linux,can-disable", key->can_be_disabled); -- To view, visit https://review.coreboot.org/c/coreboot/+/30451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb Gerrit-Change-Number: 30451 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/gpio: Enable configuring GPIO debounce duration
by Karthik Ramasubramanian (Code Review) 24 Jan '19

24 Jan '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30450 to review the following change. Change subject: soc/intel/gpio: Enable configuring GPIO debounce duration ...................................................................... soc/intel/gpio: Enable configuring GPIO debounce duration Add new helper functions to enable configuring debounce duration for a GPIO input. Also ensure that the debounce configuration is not masked out. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce duration is configured as expected. Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30450/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index c3b0ebf..294218c 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -46,7 +46,7 @@ PAD_CFG1_IOSSTATE_MASK) #endif -#define PAD_DW2_MASK (0) +#define PAD_DW2_MASK (PAD_CFG2_DEBOUNCE_MASK) #define PAD_DW3_MASK (0) #define MISCCFG_GPE0_DW0_SHIFT 8 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 153a9da..4d02ecb 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -108,6 +108,22 @@ #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ #define PAD_CFG2_NONE 0 +#define PAD_CFG2_DEBEN 1 +/* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */ +#define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1) +#define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1) +#define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1) +#define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1) +#define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1) +#define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1) +#define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1) +#define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1) +#define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1) +#define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1) +#define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1) +#define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1) +#define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1) +#define PAD_CFG2_DEBOUNCE_MASK 0x1f /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) @@ -352,6 +368,18 @@ #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) +#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) + +#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) + +#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) + /* General purpose input, routed to NMI */ #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/30450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Gerrit-Change-Number: 30450 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register
by Karthik Ramasubramanian (Code Review) 24 Jan '19

24 Jan '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30449 to review the following change. Change subject: soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register ...................................................................... soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register Currently all the helpers support configuring GPIO_DW0/1 registers. In some architectures there is an additional configuration GPIO_DW2 register that can be used to configure debounce duration etc. Update the helpers to enable configuring GPIO_DW2 pad register. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the current configuration is not disturbed by turning on the GPIO_DEBUG option and verifying the debug output before and after the change. Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 42 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30449/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 418b6ab..153a9da 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -107,6 +107,8 @@ #define PAD_CFG1_IOSSTATE_MASK 0 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ +#define PAD_CFG2_NONE 0 + /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) #define PAD_CFG1_TOL_MASK (0x1 << 25) @@ -138,17 +140,27 @@ PAD_CFG0_RX_POL_##inv) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ -#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ +#if GPIO_NUM_PAD_CFG_REGS > 2 +#define _PAD_CFG_STRUCT(__pad, __config0, __config1, __config2) \ + { \ + .pad = __pad, \ + .pad_config[0] = __config0, \ + .pad_config[1] = __config1, \ + .pad_config[2] = __config2, \ + } +#else +#define _PAD_CFG_STRUCT(__pad, __config0, __config1, __config2) \ { \ .pad = __pad, \ .pad_config[0] = __config0, \ .pad_config[1] = __config1, \ } +#endif /* Native function configuration */ #define PAD_CFG_NF(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) + PAD_IOSSTATE(TxLASTRxE), PAD_CFG2_NONE) #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S @@ -156,55 +168,57 @@ */ #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ - PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) + PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8, PAD_CFG2_NONE) #endif /* Native function configuration for standby state */ #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) + PAD_IOSSTATE(iosstate), PAD_CFG2_NONE) /* Native function configuration for standby state, also configuring iostandby as masked */ #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(IGNORE)) + PAD_IOSSTATE(IGNORE), PAD_CFG2_NONE) /* Native function configuration for standby state, also configuring iosstate and iosterm */ #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) + PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), PAD_CFG2_NONE) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE), PAD_CFG2_NONE) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ + PAD_CFG1_GPIO_DRIVER, PAD_CFG2_NONE) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm), \ + PAD_CFG2_NONE) /* General purpose input */ #define PAD_CFG_GPI(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. @@ -212,27 +226,29 @@ #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE), \ + PAD_CFG2_NONE) #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_CFG0_RX_DISABLE, \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) /* GPIO Interrupt */ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE), \ + PAD_CFG2_NONE) /* No Connect configuration for unused pad. * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term @@ -244,12 +260,13 @@ #define PAD_CFG_GPI_APIC(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull)) + PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull), PAD_CFG2_NONE) #define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull)) + PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull), \ + PAD_CFG2_NONE) #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) @@ -271,7 +288,7 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) #endif /* General purpose input, routed to APIC - with IOStandby Config*/ @@ -279,7 +296,7 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) /* * The following APIC macros assume the APIC will handle the filtering @@ -300,14 +317,14 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) /* General purpose input, routed to SMI */ #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) @@ -320,14 +337,14 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) /* General purpose input, routed to SCI */ #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm), PAD_CFG2_NONE) #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) @@ -340,14 +357,14 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxDRxE)) + PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ - PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), PAD_CFG2_NONE) #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) -- To view, visit https://review.coreboot.org/c/coreboot/+/30449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Gerrit-Change-Number: 30449 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]cbmem_top: Fix comment and remove upper limit
by Patrick Rudolph (Code Review) 24 Jan '19

24 Jan '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30609 Change subject: [WIP]cbmem_top: Fix comment and remove upper limit ...................................................................... [WIP]cbmem_top: Fix comment and remove upper limit There's no such limit on 64bit coreboot builds. * Fix comment * Remove 4 GiB limit on Cavium SoCs Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/cbmem.h M src/soc/cavium/cn81xx/cbmem.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30609/1 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ad48e35..66a8fbe 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -71,7 +71,8 @@ /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be - * below 4GiB. + * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no + * upper limit. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ void *cbmem_top(void); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd26..9a52de3 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -22,6 +22,5 @@ void *cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, - 4ULL * GiB); + return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Gerrit-Change-Number: 30609 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/cavium/cn81xx: Replace uses of dev_find_slot()
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30517 ) Change subject: soc/cavium/cn81xx: Replace uses of dev_find_slot() ...................................................................... soc/cavium/cn81xx: Replace uses of dev_find_slot() Change-Id: I9f176caff3b6423121676eb895f5f68a5b926de4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30517 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/cavium/cn81xx/ecam0.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index cff2507..6747fa6 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -273,7 +273,7 @@ u32 reg32; printk(BIOS_INFO, "ECAM0: init\n"); - const struct device *bridge = dev_find_slot(0, PCI_DEVFN(1, 0)); + const struct device *bridge = pcidev_on_root(1, 0); if (!bridge) { printk(BIOS_INFO, "ECAM0: ERROR: PCI 00:01.0 not found.\n"); return; @@ -287,7 +287,7 @@ /* Program secure ARI capability on bus 1 */ child_last = NULL; for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = dev_find_slot(bridge->link_list->secondary, i); + child = pcidev_path_behind(bridge->link_list, i); if (!child || !child->enabled) continue; @@ -306,7 +306,7 @@ /* Program insecure ARI capability on bus 1 */ child_last = NULL; for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = dev_find_slot(bridge->link_list->secondary, i); + child = pcidev_path_behind(bridge->link_list, i); if (!child) continue; config = child->chip_info; @@ -327,7 +327,7 @@ /* Enable / disable devices on bus 0 */ for (i = 0; i <= 0x1f; i++) { - child = dev_find_slot(0, PCI_DEVFN(i, 0)); + child = pcidev_on_root(i, 0); config = child ? child->chip_info : NULL; if (child && child->enabled && config && !config->secure) enable_device(i); @@ -337,7 +337,7 @@ /* Enable / disable devices and functions on bus 1 */ for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { - child = dev_find_slot(bridge->link_list->secondary, i); + child = pcidev_path_behind(bridge->link_list, i); config = child ? child->chip_info : NULL; if (child && child->enabled && ((config && !config->secure) || !config)) @@ -349,7 +349,7 @@ /* Apply IRQ on PCI devices */ /* UUA */ for (i = 0; i < 4; i++) { - child = dev_find_slot(bridge->link_list->secondary, + child = pcidev_path_behind(bridge->link_list, PCI_DEVFN(8, i)); if (!child) continue; -- To view, visit https://review.coreboot.org/c/coreboot/+/30517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f176caff3b6423121676eb895f5f68a5b926de4 Gerrit-Change-Number: 30517 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mediatek/mt8183: Add option MT8183_MINIMIZE_BOOTBLOCK
by You-Cheng Syu (Code Review) 24 Jan '19

24 Jan '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31024 Change subject: mediatek/mt8183: Add option MT8183_MINIMIZE_BOOTBLOCK ...................................................................... mediatek/mt8183: Add option MT8183_MINIMIZE_BOOTBLOCK MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL adds a new option MT8183_MINIMIZE_BOOTBLOCK in Kconfig. When enabled, initializations that be can postponed in bootblock will be removed. Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/bootblock.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31024/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index 6582e4e..b8c4dc0 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -28,4 +28,8 @@ bool default y +config MT8183_MINIMIZE_BOOTBLOCK + bool + default n + endif diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c index d7d5c2d..809826f 100644 --- a/src/soc/mediatek/mt8183/bootblock.c +++ b/src/soc/mediatek/mt8183/bootblock.c @@ -20,5 +20,7 @@ void bootblock_soc_init(void) { mt_pll_init(); - mtk_wdt_init(); + if (!IS_ENABLED(CONFIG_MT8183_MINIMIZE_BOOTBLOCK)) { + mtk_wdt_init(); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a Gerrit-Change-Number: 31024 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: cr50: Add probe command to poll Cr50 until DID VID is valid
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30295 ) Change subject: cr50: Add probe command to poll Cr50 until DID VID is valid ...................................................................... cr50: Add probe command to poll Cr50 until DID VID is valid Added new routine cr50_i2c_probe() which ensures that communication with the Cr50 over I2C is good prior to attempting other initialization of the Cr50 and TPM state. This avoids a race condition when the Cr50 is first booting that it may reset it's I2C slave interface during the first few I2C transactions initiated from coreboot. BUG=b:120009037 BRANCH=none TEST=Run the Cr50 factory update against Careena board. Confirm that I2C reads are retried until the DID VID is valid. Tested against debug Cr50 firmware that forced failure of cr50_i2c_probe() and verfied that coreboot shows recovery screen. Change-Id: I47c59a32378ad00336277e111e81ba8d2d63e69a Signed-off-by: Keith Short <keithshort(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/30295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Daniel Kurtz <djkurtz(a)google.com> --- M src/drivers/i2c/tpm/cr50.c 1 file changed, 39 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Daniel Kurtz: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index b0d3b29..19c8f6b 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -456,10 +456,44 @@ return 0; } +static int cr50_i2c_probe(struct tpm_chip *chip, uint32_t *did_vid) +{ + int retries; + + /* + * 150 ms should be enough to synchronize with the TPM even under the + * worst nested reset request conditions. In vast majority of cases + * there would be no wait at all. + */ + printk(BIOS_INFO, "Probing TPM I2C: "); + + for (retries = 15; retries > 0; retries--) { + int rc; + + rc = cr50_i2c_read(chip, TPM_DID_VID(0), (uint8_t *)did_vid, 4); + + /* Exit once DID and VID verified */ + if (!rc && (*did_vid == CR50_DID_VID)) { + printk(BIOS_INFO, "done! DID_VID 0x%08x\n", *did_vid); + return 0; + } + + /* TPM might be resetting, let's retry in a bit. */ + mdelay(10); + printk(BIOS_INFO, "."); + } + + /* + * I2C reads failed, or the DID and VID didn't match + */ + printk(BIOS_ERR, "DID_VID 0x%08x not recognized\n", *did_vid); + return -1; +} + int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) { struct tpm_inf_dev *tpm_dev = car_get_var_ptr(&g_tpm_dev); - uint32_t vendor; + uint32_t did_vid = 0; if (dev_addr == 0) { printk(BIOS_ERR, "%s: missing device address\n", __func__); @@ -471,6 +505,9 @@ cr50_vendor_init(chip); + if (cr50_i2c_probe(chip, &did_vid)) + return -1; + if (ENV_VERSTAGE || ENV_BOOTBLOCK) if (process_reset(chip)) return -1; @@ -478,17 +515,8 @@ if (claim_locality(chip)) return -1; - /* Read four bytes from DID_VID register */ - if (cr50_i2c_read(chip, TPM_DID_VID(0), (uint8_t *)&vendor, 4) < 0) - return -1; - - if (vendor != CR50_DID_VID) { - printk(BIOS_DEBUG, "Vendor ID 0x%08x not recognized\n", vendor); - return -1; - } - printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id 0x%x)\n", - bus, dev_addr, vendor >> 16); + bus, dev_addr, did_vid >> 16); chip->is_open = 1; return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47c59a32378ad00336277e111e81ba8d2d63e69a Gerrit-Change-Number: 30295 Gerrit-PatchSet: 5 Gerrit-Owner: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/google/hatch: Enable support for WWAN
by Maulik V Vaghela (Code Review) 24 Jan '19

24 Jan '19

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30678 Change subject: mb/google/hatch: Enable support for WWAN ...................................................................... mb/google/hatch: Enable support for WWAN This patch enables relevant GPIOs to enable WWAN. WWAN also requires to enable USB 2 port 6 and USB3 port 5 which is already enabled in device tree related changes. BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30678/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index d40c020..5c0231e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -23,6 +23,10 @@ PAD_NC(GPP_A16, DN_20K), /* EN_PP3300_SD_DX */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* WWAN_RADIO_DISABLE_1V8_ODL */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), /* TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), /* SRCCLKREQ1 */ @@ -47,6 +51,8 @@ PAD_NC(GPP_C11, DN_20K), /* BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), + /* WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), /* PCH_I2C_TRACKPAD_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TRACKPAD_SCL */ @@ -63,6 +69,14 @@ PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* WWAN_CONFIG_0 */ + PAD_CFG_GPI(GPP_D5, NONE, DEEP), + /* WWAN_CONFIG_1 */ + PAD_CFG_GPI(GPP_D6, NONE, DEEP), + /* WWAN_CONFIG_2 */ + PAD_CFG_GPI(GPP_D7, NONE, DEEP), + /* WWAN_CONFIG_3 */ + PAD_CFG_GPI(GPP_D8, NONE, DEEP), /* TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TOUCHSCREEN_INT_L */ @@ -95,6 +109,8 @@ PAD_NC(GPP_E22, DN_20K), /* GPIO_WWAN_WLAN_COEX3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* WWAN_RESET_1V8_ODL */ + PAD_CFG_GPO(GPP_F1, 0, DEEP), /* UART_WWANTX_WLANRX_COEX1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* UART_WWANRX_WLANTX_COEX2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07 Gerrit-Change-Number: 30678 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

4 14

Change in ...coreboot[master]: mb/google/hatch: Enable PCIe WLAN and BT
by Maulik V Vaghela (Code Review) 24 Jan '19

24 Jan '19

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30467 Change subject: mb/google/hatch: Enable PCIe WLAN and BT ...................................................................... mb/google/hatch: Enable PCIe WLAN and BT Enable PCIe WLAN for hatch 1. Enable PCI Rp#13 for PCIe WLAN 2. Enable PCI clock source 3 for PCI port 13 3. GPIO pad config for WLAN and BT USB port for BT has already been enabled so not included in this patch BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30467/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0e80ab3..1ad5589 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,7 +49,6 @@ register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" - # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" # RP 9 uses CLK SRC 1 @@ -57,6 +56,12 @@ # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + # PCIe port 13 for M.2 E-key WLAN + register "PcieRpEnable[13]" = "1" + # RP 13 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcClkReq[3]" = "3" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -119,7 +124,12 @@ device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 (x4) + device pci 1d.4 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW1_01" + device pci 00.0 on end + end + end # PCI Express Port 13 (x4) device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index ce78bb5..4a6341f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -23,6 +23,8 @@ PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), /* SRCCLKREQ1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* PCIE_14_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK */ @@ -31,12 +33,16 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* PCIE_14_WLAN_WAKE_ODL */ + PAD_CFG_GPI(GPP_C1, NONE, PLTRST), /* TOUCHSCREEN_DIS_L */ PAD_CFG_GPO(GPP_C4, 1, DEEP), /* GPP_C10_TP */ PAD_NC(GPP_C10, DN_20K), /* GPP_C11_TP */ PAD_NC(GPP_C11, DN_20K), + /* BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 1, DEEP), /* PCH_I2C_TRACKPAD_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TRACKPAD_SCL */ @@ -45,12 +51,14 @@ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), /* TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TOUCHSCREEN_INT_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Gerrit-Change-Number: 30467 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: util/lint: update non-ascii linter checking rules
by Patrick Georgi (Code Review) 24 Jan '19

24 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28449 ) Change subject: util/lint: update non-ascii linter checking rules ...................................................................... util/lint: update non-ascii linter checking rules - Check non-external payloads - Remove directories that aren't in the coreboot git repo. - Remove non-phrase rule from list of excluded phrases Change-Id: I9e056e8b43af567f102dfc0db76f60328aa1ed04 Signed-off-by: Martin Roth <martinr(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/28449 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/lint/lint-stable-016-non-ascii 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve diff --git a/util/lint/lint-stable-016-non-ascii b/util/lint/lint-stable-016-non-ascii index 3c22900..fbb830d 100755 --- a/util/lint/lint-stable-016-non-ascii +++ b/util/lint/lint-stable-016-non-ascii @@ -17,9 +17,9 @@ LC_ALL=C export LC_ALL INCLUDED_FILES='\.[chsS]$\|\.asl$\|\.cb$\|\.inc$\|Kconfig\|\.ld$|\.txt\|\.hex' -EXCLUDED_DIRS='^payloads/\|^src/vendorcode/\|^Documentation/\|^build/\|^3rdparty/\|^\.git/\|^coreboot-builds/\|^util/nvidia/cbootimage' +EXCLUDED_DIRS='^payloads/external/\|^src/vendorcode/\|^Documentation/' EXCLUDED_FILES='to-wiki/towiki\.sh$\|vga/vga_font\|video/font\|PDCurses.*x11' -EXCLUDED_PHRASES='Copyright\|Ported to\|Intel®\|°C\|°F\|Athlon™\|Copyright.*©\|A-Za-zÀ-ÿ' +EXCLUDED_PHRASES='Copyright\|Ported to\|Intel®\|°C\|°F\|Athlon™\|Copyright.*©' # Exit if git isn't present or the code isn't in a git repo if [ -z "$(command -v git)" ] || \ -- To view, visit https://review.coreboot.org/c/coreboot/+/28449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e056e8b43af567f102dfc0db76f60328aa1ed04 Gerrit-Change-Number: 28449 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-MessageType: merged

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