coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: arch/x86/smbios(type4): Write processor_upgrade field
by Nico Huber (Code Review) 27 Jan '19

27 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29529 ) Change subject: arch/x86/smbios(type4): Write processor_upgrade field ...................................................................... Patch Set 12: > I don't think this would be useful considering CB:31032 and CB:31031 Obviously this is a valid use case for the socket information. Should the Kconfig symbols of these two changes be reverted? -- To view, visit https://review.coreboot.org/c/coreboot/+/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 12 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sun, 27 Jan 2019 11:21:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/skylake: Fix the warning "type 'hex' are always defined"
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31050 Change subject: soc/intel/skylake: Fix the warning "type 'hex' are always defined" ...................................................................... soc/intel/skylake: Fix the warning "type 'hex' are always defined" This is spoted using "./util/lint/kconfig_lint" Change-Id: Icfda267936a23d9d14832116d67571f42f685906 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/skylake/chip_fsp20.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31050/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 18c2aef..3ade8d7 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -391,14 +391,16 @@ params->SpiFlashCfgLockDown = 0; } /* only replacing preexisting subsys ID defaults when non-zero */ -#if defined(CONFIG_SUBSYSTEM_VENDOR_ID) && CONFIG_SUBSYSTEM_VENDOR_ID - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; -#endif -#if defined(CONFIG_SUBSYSTEM_DEVICE_ID) && CONFIG_SUBSYSTEM_DEVICE_ID - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; -#endif + if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { + params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; + params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; + } + + if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { + params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; + params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; + } + params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchPmDeepSxPol = config->PmConfigDeepSxPol; -- To view, visit https://review.coreboot.org/c/coreboot/+/31050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfda267936a23d9d14832116d67571f42f685906 Gerrit-Change-Number: 31050 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Fix typo on DMIBAR32(0x334)
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31063 Change subject: nb/intel/i945: Fix typo on DMIBAR32(0x334) ...................................................................... nb/intel/i945: Fix typo on DMIBAR32(0x334) Change-Id: Ib894c24bc787c6c211da26dca78bcd330ded6681 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31063/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f11e612..cc7b1ef 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -513,7 +513,7 @@ DMIBAR32(0x314) = DMIBAR32(0x314); DMIBAR32(0x324) = DMIBAR32(0x324); DMIBAR32(0x328) = DMIBAR32(0x328); - DMIBAR32(0x338) = DMIBAR32(0x334); + DMIBAR32(0x334) = DMIBAR32(0x334); DMIBAR32(0x338) = DMIBAR32(0x338); if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & (1 << 5))) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib894c24bc787c6c211da26dca78bcd330ded6681 Gerrit-Change-Number: 31063 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Remove stuff done at bootblock
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31107 Change subject: nb/intel/i945: Remove stuff done at bootblock ...................................................................... nb/intel/i945: Remove stuff done at bootblock Upper 128bytes of CMOS and RCBA are already enabled at bootblock. Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31107/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index cc7b1ef..81874ab 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -157,7 +157,6 @@ /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ @@ -174,9 +173,6 @@ outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n"); - /* Enable upper 128bytes of CMOS */ - RCBA32(RC) = (1 << 2); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..f3c3df6 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2414,9 +2414,6 @@ { MCHBAR32(REPC) |= (1 << 0); - /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { sdram_recover_receive_enable(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928 Gerrit-Change-Number: 31107 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init
by HAOUAS Elyes (Code Review) 27 Jan '19

27 Jan '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27558 ) Change subject: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init ...................................................................... Abandoned merged with Change 25565 -- To view, visit https://review.coreboot.org/c/coreboot/+/27558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62eedf2e6f1fd79fa3bf4e173e5317a7c775cdef Gerrit-Change-Number: 27558 Gerrit-PatchSet: 13 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/intel/icelake: Enable RTC support
by Lijian Zhao (Code Review) 27 Jan '19

27 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31103 Change subject: soc/intel/icelake: Enable RTC support ...................................................................... soc/intel/icelake: Enable RTC support Turn on RTC support in coreboot stage. BUG=N/A TEST=N/A Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I77c8ba968f2c240673deed1a65b6568e4a26e5b6 --- M src/soc/intel/icelake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31103/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 34af339..258a91c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -37,6 +37,7 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT + select RTC select SMM_TSEG select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT @@ -49,6 +50,7 @@ select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM -- To view, visit https://review.coreboot.org/c/coreboot/+/31103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c8ba968f2c240673deed1a65b6568e4a26e5b6 Gerrit-Change-Number: 31103 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/cnl/chip.h: Fix preprocessor condition
by Rizwan Qureshi (Code Review) 27 Jan '19

27 Jan '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31095 ) Change subject: src/soc/intel/cnl/chip.h: Fix preprocessor condition ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005 Gerrit-Change-Number: 31095 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 27 Jan 2019 04:29:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Increse BIOS region size to 28MB
by Lijian Zhao (Code Review) 27 Jan '19

27 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31054 Change subject: mb/google/sarien: Increse BIOS region size to 28MB ...................................................................... mb/google/sarien: Increse BIOS region size to 28MB Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for upcoming payloads. BUG=b:121169122 TEST=Build and boot up fine into OS on sarien and arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 --- M src/mainboard/google/sarien/chromeos.fmd 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31054/1 diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index ba42a6f..2408a30 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -1,27 +1,27 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1000000 { + SI_ALL@0x0 0x400000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 SI_GBE@0x101000 0x2000 - SI_ME@0x103000 0xef9000 - SI_PDR@0xffc000 0x4000 + SI_ME@0x103000 0x2f9000 + SI_PDR@0x3fc000 0x4000 } - SI_BIOS@0x1000000 0x1000000 { - RW_DIAG@0x0 0x6d0000 { + SI_BIOS@0x400000 0x1c00000 { + RW_DIAG@0x0 0x12d0000 { DIAG_NVRAM@0x0 0x10000 - RW_LEGACY(CBFS)@0x10000 0x6c0000 + RW_LEGACY(CBFS)@0x10000 0x12c0000 } - RW_SECTION_A@0x6d0000 0x280000 { + RW_SECTION_A@0x12d0000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x950000 0x280000 { + RW_SECTION_B@0x1550000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0xbd0000 0x30000 { + RW_MISC@0x17d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -34,7 +34,7 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - WP_RO@0xc00000 0x400000 { + WP_RO@0x1800000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/31054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 Gerrit-Change-Number: 31054 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Configure miscellaneous features
by Ronak Kanabar (Code Review) 26 Jan '19

26 Jan '19

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30774 Change subject: mb/google/hatch: Configure miscellaneous features ...................................................................... mb/google/hatch: Configure miscellaneous features set SaGv = 3 , To set System Agent dynamic frequency support as FixedHigh set HeciEnabled = 1, To Enable heci communication set VmxEnable = 1, To Enable Virtual-Machine Extension support set speed_shift_enable = 1 To Enable Speed Shift Technology support set s0ix_enable = 0, To Disable active idle state support. Will make it Enable when platform will be in stable stage set dptf_enable = 0, To Disable Dynamic Platform Thermal Framework support. Will make it Enable when platform will be in stable stage set dmipwroptimize = 1 , To Enable DMI Power Optimizer on PCH side Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30774/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 45e8421..7104fd4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,6 +49,13 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" + register "SaGv" = "3" + register "HeciEnabled" = "1" + register "VmxEnable" = "1" + register "speed_shift_enable" = "1" + register "s0ix_enable" = "0" + register "dptf_enable" = "0" + register "dmipwroptimize" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Gerrit-Change-Number: 30774 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/bincfg: Fix building
by Arthur Heymans (Code Review) 26 Jan '19

26 Jan '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31106 Change subject: util/bincfg: Fix building ...................................................................... util/bincfg: Fix building 48c24ce "util/bincfg: code cleanup: convert sym_table to a local variable" used non existing types in function declarations. Change-Id: I862659c008488f609be14486722dc008919285e5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/bincfg/bincfg.h M util/bincfg/bincfg.l M util/bincfg/bincfg.y 3 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/31106/1 diff --git a/util/bincfg/bincfg.h b/util/bincfg/bincfg.h index c0e1242..25476ec 100644 --- a/util/bincfg/bincfg.h +++ b/util/bincfg/bincfg.h @@ -37,9 +37,9 @@ unsigned int lenactualblob; }; -static struct field *putsym(field_ptr_t, char const *, unsigned int); -static struct field *getsym(field_ptr_t, char const *); -static void yyerror(FILE *, field_ptr_t, char const *); +static struct field *putsym(struct field **, char const *, unsigned int); +static struct field *getsym(struct field **, char const *); +static void yyerror(FILE *, struct field **, char const *); int yylex(void); static struct blob *binary; diff --git a/util/bincfg/bincfg.l b/util/bincfg/bincfg.l index f9e880f..c6f7171 100644 --- a/util/bincfg/bincfg.l +++ b/util/bincfg/bincfg.l @@ -17,10 +17,9 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> +#include "bincfg.h" #include "bincfg.tab.h" -extern struct blob binary; - unsigned int parsehex (char *s) { unsigned int i, nib, val = 0; diff --git a/util/bincfg/bincfg.y b/util/bincfg/bincfg.y index ac65d0f..854c539 100644 --- a/util/bincfg/bincfg.y +++ b/util/bincfg/bincfg.y @@ -124,14 +124,14 @@ sym_name); return 0; } - struct field *ptr = (field_t ) malloc (sizeof (struct field)); + struct field *ptr = (struct field *) malloc (sizeof (struct field)); check_pointer(ptr); ptr->name = (char *) malloc (strlen (sym_name) + 1); check_pointer(ptr->name); strcpy (ptr->name, sym_name); ptr->width = w; ptr->value = 0; - ptr->next = (field_t)0; + ptr->next = (struct field *)NULL; if (sym_table_tail) { sym_table_tail->next = ptr; } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/31106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862659c008488f609be14486722dc008919285e5 Gerrit-Change-Number: 31106 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019