coreboot-gerrit September 2018

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Change in coreboot[master]: amd/stoneyridge: Load AOAC and USB gnvs values
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28767 ) Change subject: amd/stoneyridge: Load AOAC and USB gnvs values ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 910: sd = dev_find_slot(0, SD_DEVFN); : Use is_aoac_device_enabled(FCH_AOAC_D3_STATE_SD), declaring FCH_AOAC_D3_STATE_SD = 0x70 https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 912: sata = dev_find_slot(0, SATA_DEVFN); : Use is_aoac_device_enabled(FCH_AOAC_D3_STATE_SATA), declaring FCH_AOAC_D3_STATE_SATA = 0x5E https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 914: 1; Can you be sure it'll be enabled? ESPI is not the same as SPI. Use is_aoac_device_enabled(FCH_AOAC_D3_STATE_ESPI), declaring FCH_AOAC_D3_STATE_ESPI = 0x76 -- To view, visit https://review.coreboot.org/28767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Gerrit-Change-Number: 28767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:41:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Create gnvs entries for AOAC devices
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28765 ) Change subject: amd/stoneyridge: Create gnvs entries for AOAC devices ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 411: UART0 > UART1 ? Yep -- To view, visit https://review.coreboot.org/28765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Gerrit-Change-Number: 28765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:24:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Add USB settings to gnvs
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28766 ) Change subject: amd/stoneyridge: Add USB settings to gnvs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Gerrit-Change-Number: 28766 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:19:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd/stoneyridge: Create gnvs entries for AOAC devices
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28765 ) Change subject: amd/stoneyridge: Create gnvs entries for AOAC devices ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 411: UART0 UART1 ? -- To view, visit https://review.coreboot.org/28765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Gerrit-Change-Number: 28765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:09:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: payloads: Only show supported payloads in menuconfig
by Philipp Hug (Code Review) 27 Sep '18

27 Sep '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/28774 ) Change subject: payloads: Only show supported payloads in menuconfig ...................................................................... Patch Set 1: > Patch Set 1: Code-Review+1 > > AFAIK, SeaBIOS is x86-only as well. Yes, SeaBIOS is already correct: depends on ARCH_X86 -- To view, visit https://review.coreboot.org/28774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Gerrit-Change-Number: 28774 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:08:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl1: Add new mainboard variant mc_apl2
by Werner Zeh (Code Review) 27 Sep '18

27 Sep '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/28735 ) Change subject: siemens/mc_apl1: Add new mainboard variant mc_apl2 ...................................................................... siemens/mc_apl1: Add new mainboard variant mc_apl2 This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/28735 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c 6 files changed, 197 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 97ba66f..783207c 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -17,10 +17,12 @@ config VARIANT_DIR string default "mc_apl1" if BOARD_SIEMENS_MC_APL1 + default "mc_apl2" if BOARD_SIEMENS_MC_APL2 config MAINBOARD_PART_NUMBER string default "MC APL1" if BOARD_SIEMENS_MC_APL1 + default "MC APL2" if BOARD_SIEMENS_MC_APL2 config MAX_CPUS int diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 112bbb3..7f5f263 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -1,3 +1,7 @@ config BOARD_SIEMENS_MC_APL1 - bool "MC APL1" + bool "-> MC APL1" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL2 + bool "-> MC APL2" select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig new file mode 100644 index 0000000..aa90041 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -0,0 +1,14 @@ + +if BOARD_SIEMENS_MC_APL2 + +config BOARD_SIEMENS_MC_APL2_VAR + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVER_SIEMENS_NC_FPGA + +config DEVICETREE + string + default "variants/mc_apl2/devicetree.cb" + +endif # BOARD_SIEMENS_MC_APL2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb new file mode 100644 index 0000000..42c4310 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -0,0 +1,109 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Disable all clkreq of PCIe root ports as SMARC interface do not + # have this pins. + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 on end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c new file mode 100644 index 0000000..0c2418a --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <hwilib.h> +#include <intelblocks/lpc_lib.h> +#include <timer.h> +#include <timestamp.h> +#include <baseboard/variants.h> + +void variant_mainboard_final(void) +{ + struct device *dev; + uint16_t cmd = 0; + + /* Set Master Enable for on-board PCI device. */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); + if (dev) { + cmd = pci_read_config16(dev, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, cmd); + } +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); -- To view, visit https://review.coreboot.org/28735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Gerrit-Change-Number: 28735 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads: Only show supported payloads in menuconfig
by Angel Pons (Code Review) 27 Sep '18

27 Sep '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28774 ) Change subject: payloads: Only show supported payloads in menuconfig ...................................................................... Patch Set 1: Code-Review+1 AFAIK, SeaBIOS is x86-only as well. -- To view, visit https://review.coreboot.org/28774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Gerrit-Change-Number: 28774 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 15:55:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl1: Make the DDR memory swizzle data configurable
by Werner Zeh (Code Review) 27 Sep '18

27 Sep '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/28730 ) Change subject: siemens/mc_apl1: Make the DDR memory swizzle data configurable ...................................................................... siemens/mc_apl1: Make the DDR memory swizzle data configurable In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/28730 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/romstage.c M src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc M src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h A src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c 4 files changed, 142 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index d56c7ee..87e41dc 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -18,39 +18,17 @@ #include <hwilib.h> #include <lib.h> #include <string.h> +#include <soc/meminit.h> #include <soc/romstage.h> #include <fsp/api.h> #include <FspmUpd.h> #include <baseboard/variants.h> -static const uint8_t Ch0_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch1_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch2_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch3_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; + const struct lpddr4_swizzle_cfg *cfg; + const struct lpddr4_chan_swizzle_cfg *chan; uint8_t spd[0x80]; size_t num; @@ -58,7 +36,8 @@ pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); - /* Get DRAM configuration data from hwinfo block. + /* + * Get DRAM configuration data from hwinfo block. * The configuration data from hwinfo block is a one-to-one * representation of the FSPM_UPD data starting with parameter * 'Package' (offset 0x4d) and ending before parameter @@ -80,14 +59,70 @@ (((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)- (&memupd->FspmConfig.Package))); - memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, - sizeof(Ch0_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, - sizeof(Ch1_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, - sizeof(Ch2_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, - sizeof(Ch3_Bit_swizzling)); + /* + * Some of the mc_apl1 boards use LPDDR4 memory. In this case, the + * correct swizzle configuration is necessary. The default settings + * for swizzling are 0, since the baseboard does not use LPDDR4 memory. + */ + cfg = variant_lpddr4_swizzle_config(); + + /* + * CH0_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + chan = &cfg->phys[LP4_PHYS_CH0B]; + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[8], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[16], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[24], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + + /* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. */ + chan = &cfg->phys[LP4_PHYS_CH0A]; + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[0], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[8], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[16], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); + + /* + * CH1_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + chan = &cfg->phys[LP4_PHYS_CH1B]; + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[8], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[16], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[24], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + + /* CH1_DQA byte lanes in the bit swizzle configuration field are 1:1. */ + chan = &cfg->phys[LP4_PHYS_CH1A]; + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[0], &chan->dqs[LP4_DQS0], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[8], &chan->dqs[LP4_DQS1], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[16], &chan->dqs[LP4_DQS2], + (size_t)DQ_BITS_PER_DQS); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3], + (size_t)DQ_BITS_PER_DQS); memupd->FspmConfig.MsgLevelMask = 0x0; memupd->FspmConfig.MrcDataSaving = 0x0; diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc index e3e87ce..07ebf9b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc @@ -1,3 +1,4 @@ romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h index 09153c6..6828ed8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h @@ -26,6 +26,9 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +/* This function provides the swizzle data for the DRAM initialization. */ +const struct lpddr4_swizzle_cfg *variant_lpddr4_swizzle_config(void); + /* The following function performs board specific things. */ void variant_mainboard_final(void); diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c new file mode 100644 index 0000000..13b7ab8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <compiler.h> +#include <soc/meminit.h> + +const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, +}; + +const struct lpddr4_swizzle_cfg * __weak variant_lpddr4_swizzle_config(void) +{ + return &baseboard_lpddr4_swizzle; +} -- To view, visit https://review.coreboot.org/28730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Gerrit-Change-Number: 28730 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/i945: Correct SLP_S4# comment
by Elyes HAOUAS (Code Review) 27 Sep '18

27 Sep '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28395 ) Change subject: nb/intel/i945: Correct SLP_S4# comment ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I86df0df5337397d2c23ca311ecae1c8a38eb32f0 Gerrit-Change-Number: 28395 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/auron/variants: Don't use device_t
by Elyes HAOUAS (Code Review) 27 Sep '18

27 Sep '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28684 ) Change subject: mb/google/auron/variants: Don't use device_t ...................................................................... Abandoned see Change 28642 -- To view, visit https://review.coreboot.org/28684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Iafda1af7639e5f8f43b431794d9da8f8bc20661d Gerrit-Change-Number: 28684 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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