coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amd/stoneyridge: Load AOAC and USB gnvs values
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28767 ) Change subject: amd/stoneyridge: Load AOAC and USB gnvs values ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 914: 1; > No, not certain. This will eventually be used for SD. I'll update the source. Search for "AOACx[7F:41:step2] Device D3 State" in the NDA BKDG (probably also available in the public one), and you'll understand the values of 0x5F, 0x71 and 0x77. The even offsets is for D3 control, the odd ones for D3 state. And yes, procedure is_aoac_device_enabled() was created to use specifically these offsets when checking if a device is enabled (D0) or disabled (D3). -- To view, visit https://review.coreboot.org/28767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Gerrit-Change-Number: 28767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 21:58:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Load AOAC and USB gnvs values
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28767 ) Change subject: amd/stoneyridge: Load AOAC and USB gnvs values ...................................................................... Patch Set 1: (1 comment) > Sorry, 0x71 is the state Sorry, 0x5F is the state Sorry, 0x77 is the state I'm not certain what you're saying. Do you think these are OK as-is? https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 914: 1; > Can you be sure it'll be enabled? ESPI is not the same as SPI. […] No, not certain. This will eventually be used for SD. I'll update the source. -- To view, visit https://review.coreboot.org/28767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Gerrit-Change-Number: 28767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 21:34:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Add ASL for D-states on AOAC devices
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28769 ) Change subject: amd/stoneyridge: Add ASL for D-states on AOAC devices ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci… File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 444: Case(Package() {5, 15, 24}) { : Store(One, PG1A) : } : Case(Package() {6, 7, 8, 11, 12, 18}) { : Store(One, PG2_) : } : > What about Arg0 = 23? These are power groups. xHCI is on its own power, as I read it (AOACxA0[3]). This also mirrors AMD's code. https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 557: * todo Case(15) { STD3()} */ /* SATA * > default? I'd prefer to keep it as close to AMD's code as possible. I'll add a default if static analysis suggests it, but basically I want there to be no default behavior. -- To view, visit https://review.coreboot.org/28769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Gerrit-Change-Number: 28769 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 21:17:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28771 ) Change subject: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28771/1/src/soc/amd/stoneyridge/acpi/sb_pci… File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: https://review.coreboot.org/#/c/28771/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 642: > Not very clear. Apparently this code only executes something (HW wise) if Arg0 is bit5. I agree. I'd meant to go back and figure out what AMD was trying to say, and forgot to. Looks like /* * Helper... * Arg0: bit to set or clear * Arg1: 0: clear bit[Arg0], non-0: set bit[Arg0] */ -- To view, visit https://review.coreboot.org/28771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Gerrit-Change-Number: 28771 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 21:12:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/nocturne: Change IMX319 sensor link freq
by Lijian Zhao (Code Review) 27 Sep '18

27 Sep '18

Hello Rajmohan Mani, Tomasz Figa, Ricky Liang, build bot (Jenkins), Chiranjeevi Rapolu, Bingbu Cao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28736 to look at the new patch set (#3). Change subject: mb/google/nocturne: Change IMX319 sensor link freq ...................................................................... mb/google/nocturne: Change IMX319 sensor link freq Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the changes from kernel driver, the change cause by IMX319 uses single PLL instead of two PLL. Bug=b.116082248 Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28736/3 -- To view, visit https://review.coreboot.org/28736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Gerrit-Change-Number: 28736 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bingbu Cao <bingbu.cao(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Tomasz Figa <tfiga(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd/stoneyridge: Create gnvs entries for AOAC devices
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28765 ) Change subject: amd/stoneyridge: Create gnvs entries for AOAC devices ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/acpi/global… File src/soc/amd/stoneyridge/acpi/globalnvs.asl: https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/acpi/global… PS1, Line 50: , 5, // 0x31 - AOAC Device Enables > Do we want to pad this to a dword boundary? Same thoughts as in the other patch. Except for appearance, I don't think it would do much for us. https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 404: int > uint32_t? Hmm, I seem to recall int is proper for declaring n:m but I could be wrong. I've seen some examples of unsigned on the interwebs. -- To view, visit https://review.coreboot.org/28765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Gerrit-Change-Number: 28765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 20:57:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/whlrvp: Enable HDA controller driver
by Lijian Zhao (Code Review) 27 Sep '18

27 Sep '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28777 Change subject: mb/intel/whlrvp: Enable HDA controller driver ...................................................................... mb/intel/whlrvp: Enable HDA controller driver Enable HDA controller coreboot driver for Whiskey Lake RVP platform on top of common code. Change-Id: I14345ae89dea517761c9de46a3961b780b63216f Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28777/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 311f6d1..651efd6 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -13,6 +13,7 @@ select DRIVERS_I2C_GENERIC select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_MEMCFG_INIT + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/28777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I14345ae89dea517761c9de46a3961b780b63216f Gerrit-Change-Number: 28777 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/nocturne: Change IMX319 sensor link freq
by Chiranjeevi Rapolu (Code Review) 27 Sep '18

27 Sep '18

Chiranjeevi Rapolu has posted comments on this change. ( https://review.coreboot.org/28736 ) Change subject: mb/google/nocturne: Change IMX319 sensor link freq ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/28736/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28736/1//COMMIT_MSG@9 PS1, Line 9: Change link frequency of IMX319 from 360Mhz to 482.4 Mhz > Please also state why this change is needed. Previously two PLL were used in IMX319. Now, with single PLL the link frequency comes to 482.4MHz. -- To view, visit https://review.coreboot.org/28736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Gerrit-Change-Number: 28736 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bingbu Cao <bingbu.cao(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Tomasz Figa <tfiga(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 20:32:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd/stoneyridge: Add USB settings to gnvs
by Martin Roth (Code Review) 27 Sep '18

27 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28766 ) Change subject: amd/stoneyridge: Add USB settings to gnvs ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28766/1/src/soc/amd/stoneyridge/acpi/global… File src/soc/amd/stoneyridge/acpi/globalnvs.asl: https://review.coreboot.org/#/c/28766/1/src/soc/amd/stoneyridge/acpi/global… PS1, Line 68: FW00, 16, If we dword align the above structure, we might group the 2 16-bit fields to keep the others dword aligned as well. -- To view, visit https://review.coreboot.org/28766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Gerrit-Change-Number: 28766 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 20:11:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Create gnvs entries for AOAC devices
by Martin Roth (Code Review) 27 Sep '18

27 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28765 ) Change subject: amd/stoneyridge: Create gnvs entries for AOAC devices ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/acpi/global… File src/soc/amd/stoneyridge/acpi/globalnvs.asl: https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/acpi/global… PS1, Line 50: , 5, // 0x31 - AOAC Device Enables Do we want to pad this to a dword boundary? -- To view, visit https://review.coreboot.org/28765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Gerrit-Change-Number: 28765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 20:07:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018