coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

1 participants
886 discussions

Change in coreboot[master]: amd/stoneyridge: Create gnvs entries for AOAC devices
by Martin Roth (Code Review) 27 Sep '18

27 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28765 ) Change subject: amd/stoneyridge: Create gnvs entries for AOAC devices ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28765/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 404: int uint32_t? -- To view, visit https://review.coreboot.org/28765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Gerrit-Change-Number: 28765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 20:05:59 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: util/abuild: When using blobs, enable 3rdparty/fsp by default
by Patrick Georgi (Code Review) 27 Sep '18

27 Sep '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/28776 Change subject: util/abuild: When using blobs, enable 3rdparty/fsp by default ...................................................................... util/abuild: When using blobs, enable 3rdparty/fsp by default This is a no-op on non-FSP systems, but enables using it when supported Change-Id: I66fe9b8587753ea017e13a752a7728e47287e9a0 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28776/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 3228d09..9afd364 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -696,7 +696,7 @@ shift;; -B|--blobs) shift customizing="${customizing}, blobs" - configoptions="${configoptions}CONFIG_USE_BLOBS=y\n" + configoptions="${configoptions}CONFIG_USE_BLOBS=y\nCONFIG_ADD_FSP_BINARIES=y\nCONFIG_FSP_USE_REPO=y\n" ;; -A|--any-toolchain) shift customizing="${customizing}, any-toolchain" -- To view, visit https://review.coreboot.org/28776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I66fe9b8587753ea017e13a752a7728e47287e9a0 Gerrit-Change-Number: 28776 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

1 0

Change in coreboot[master]: 3rdparty/fsp: update to current master
by Patrick Georgi (Code Review) 27 Sep '18

27 Sep '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/28775 Change subject: 3rdparty/fsp: update to current master ...................................................................... 3rdparty/fsp: update to current master This includes the SplitFspBin.py script Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28775/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 7431e4f..162719b 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 7431e4f3399a5081c956753b5fa3bcd764196723 +Subproject commit 162719b6cb5efc6c50dcb23dfdb378358573e2b6 -- To view, visit https://review.coreboot.org/28775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac Gerrit-Change-Number: 28775 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

1 0

Change in coreboot[master]: google/kahlee: Run FCH PTS and WAK methods
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28773 ) Change subject: google/kahlee: Run FCH PTS and WAK methods ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f Gerrit-Change-Number: 28773 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 17:29:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: amd/stoneyridge: Add USB ASL for D0/D3cold
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28772 ) Change subject: amd/stoneyridge: Add USB ASL for D0/D3cold ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb Gerrit-Change-Number: 28772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 17:27:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28771 ) Change subject: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28771/1/src/soc/amd/stoneyridge/acpi/sb_pci… File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: https://review.coreboot.org/#/c/28771/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 642: Not very clear. Apparently this code only executes something (HW wise) if Arg0 is bit5. -- To view, visit https://review.coreboot.org/28771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Gerrit-Change-Number: 28771 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 17:08:16 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: amd/stoneyridge: Add FCH WAK and PTS methods
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28770 ) Change subject: amd/stoneyridge: Add FCH WAK and PTS methods ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28770/1/src/soc/amd/stoneyridge/acpi/sb_pci… File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: https://review.coreboot.org/#/c/28770/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 597: SATA Why SATA? I thought this was about waking from USB... -- To view, visit https://review.coreboot.org/28770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda Gerrit-Change-Number: 28770 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 17:00:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: amd/stoneyridge: Load AOAC and USB gnvs values
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28767 ) Change subject: amd/stoneyridge: Load AOAC and USB gnvs values ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 910: sd = dev_find_slot(0, SD_DEVFN); : > Use is_aoac_device_enabled(FCH_AOAC_D3_STATE_SD), declaring FCH_AOAC_D3_STATE_SD = 0x70 Sorry, 0x71 is the state https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 912: sata = dev_find_slot(0, SATA_DEVFN); : > Use is_aoac_device_enabled(FCH_AOAC_D3_STATE_SATA), declaring FCH_AOAC_D3_STATE_SATA = 0x5E Sorry, 0x5F is the state https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 914: 1; > Can you be sure it'll be enabled? ESPI is not the same as SPI. […] Sorry, 0x77 is the state -- To view, visit https://review.coreboot.org/28767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Gerrit-Change-Number: 28767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:56:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: amd/stoneyridge: Add ASL for D-states on AOAC devices
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28769 ) Change subject: amd/stoneyridge: Add ASL for D-states on AOAC devices ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci… File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 444: Case(Package() {5, 15, 24}) { : Store(One, PG1A) : } : Case(Package() {6, 7, 8, 11, 12, 18}) { : Store(One, PG2_) : } : What about Arg0 = 23? https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 501: /* todo Case(15) { STD0()} */ /* SATA */ : /* todo Case(18) { U2D0()} */ /* EHCI */ : /* todo Case(23) { U3D0()} */ /* XHCI */ : /* todo Case(24) { SDD0()} */ /* SD */ : shouldn't there be a default statement? https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci… PS1, Line 557: * todo Case(15) { STD3()} */ /* SATA * default? -- To view, visit https://review.coreboot.org/28769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Gerrit-Change-Number: 28769 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:53:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL
by Richard Spiegel (Code Review) 27 Sep '18

27 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28768 ) Change subject: amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Gerrit-Change-Number: 28768 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 16:46:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

← Newer
1
...
8
9
10
11
12
13
14
...
89
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2018