coreboot-gerrit September 2018

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Change in coreboot[master]: HACK: Julius' changes for v15
by Julius Werner (Code Review) 28 Sep '18

28 Sep '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/28783 Change subject: HACK: Julius' changes for v15 ...................................................................... HACK: Julius' changes for v15 Change-Id: I0cd7f0f6f49d5eb2492ba0897b0811713c547649 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/Makefile.inc M src/mainboard/google/cheza/Kconfig M src/mainboard/google/cheza/chromeos.c M src/soc/qualcomm/sdm845/Makefile.inc 4 files changed, 24 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28783/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 5f8b092..6bb7196 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -156,8 +156,6 @@ # Build ARM Trusted Firmware (BL31) ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) -# temporary change, soc makefile process would pack pre-built bl31 -ifneq ($(CONFIG_SOC_QUALCOMM_SDM845),y) ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") @@ -237,8 +235,6 @@ endif # CONFIG_ARM64_USE_SECURE_OS -endif # CONFIG_SOC_QUALCOMM_845 - endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig index 9882b59..6a43c4bc 100644 --- a/src/mainboard/google/cheza/Kconfig +++ b/src/mainboard/google/cheza/Kconfig @@ -8,20 +8,27 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select COMMON_CBFS_SPI_WRAPPER +# select EC_GOOGLE_CHROMEEC +# select EC_GOOGLE_CHROMEEC_RTC +# select EC_GOOGLE_CHROMEEC_SPI +# select RTC select SOC_QUALCOMM_SDM845 select SPI_FLASH select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 config CONSOLE_UART_ADDR hex default 0x00A84000 config VBOOT +# select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_VBNV_FLASH - select VBOOT_MOCK_SECDATA select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC # only for now, makes testing easier config MAINBOARD_DIR @@ -32,6 +39,14 @@ string default "Google" +config DRIVER_TPM_SPI_BUS + hex + default 0x5 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0xa + ########################################################## #### Update below when adding a new derivative board. #### ########################################################## diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 538e46f..99d8654 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -13,9 +13,15 @@ * GNU General Public License for more details. */ +#include <bootmode.h> #include <boot/coreboot_tables.h> void fill_lb_gpios(struct lb_gpios *gpios) { } + +int get_write_protect_state(void) +{ + return 0; /* TODO: implement */ +} diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 527b1b3..2880d66 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -67,6 +67,8 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include +BL31_MAKEARGS += PLAT=sdm845 + SDM845_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sdm845 ################################################################################ @@ -160,17 +162,6 @@ endif ################################################################################ -BL31_FILE := $(SDM845_BLOB)/bl31.elf -bl31_file := $(shell ls $(BL31_FILE)) -ifneq (,$(findstring $(BL31_FILE),$(bl31_file))) - BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 - $(BL31_CBFS)-file := $(BL31_FILE) - $(BL31_CBFS)-type := payload - $(BL31_CBFS)-compression := none - cbfs-files-y += $(BL31_CBFS) -endif - -################################################################################ QC_SEC_FILE := $(SDM845_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) -- To view, visit https://review.coreboot.org/28783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0cd7f0f6f49d5eb2492ba0897b0811713c547649 Gerrit-Change-Number: 28783 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

1 0

Change in coreboot[master]: mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Fleex
by Ivy Jian (Code Review) 28 Sep '18

28 Sep '18

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/28782 Change subject: mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Fleex ...................................................................... mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for Fleex Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT. BUG=b:116721822 TEST=Verified it in Fleex EVT board which rework ram id. Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310 Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28782/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index d245a62..ba1e861 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -117,6 +117,7 @@ default y if BOARD_GOOGLE_PHASER default y if BOARD_GOOGLE_MEEP default y if BOARD_GOOGLE_AMPTON + default y if BOARD_GOOGLE_FLEEX config DRAM_PART_NUM_ALWAYS_IN_CBI bool @@ -129,7 +130,7 @@ default 255 if BOARD_GOOGLE_YORP default 255 if BOARD_GOOGLE_BIP default 2 if BOARD_GOOGLE_PHASER - default 9 if BOARD_GOOGLE_FLEEX + default 2 if BOARD_GOOGLE_FLEEX default 9 if BOARD_GOOGLE_BOBBA default 1 if BOARD_GOOGLE_MEEP default 255 if BOARD_GOOGLE_AMPTON -- To view, visit https://review.coreboot.org/28782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310 Gerrit-Change-Number: 28782 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com>

1 0

Change in coreboot[master]: WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT
by Sathyanarayana Nujella (Code Review) 28 Sep '18

28 Sep '18

Sathyanarayana Nujella has posted comments on this change. ( https://review.coreboot.org/28780 ) Change subject: WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT ...................................................................... Patch Set 1: Code-Review-1 Marking as "-1" as Kernel side we are yet to get it completely working. Need some more time please. -- To view, visit https://review.coreboot.org/28780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iabf1d2329880d7e247efac00d2160606792dab00 Gerrit-Change-Number: 28780 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 Sep 2018 02:00:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/intel/whlrvp: Enable HDA controller driver
by Lijian Zhao (Code Review) 28 Sep '18

28 Sep '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28781 Change subject: mb/intel/whlrvp: Enable HDA controller driver ...................................................................... mb/intel/whlrvp: Enable HDA controller driver Enable HDA controller coreboot driver for Whiskey Lake RVP platform on top of common code. Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79 --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Makefile.inc A src/mainboard/intel/coffeelake_rvp/hda_verb.c A src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h 4 files changed, 740 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28781/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 311f6d1..651efd6 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -13,6 +13,7 @@ select DRIVERS_I2C_GENERIC select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_MEMCFG_INIT + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index 2746453..6a375f4 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -25,6 +25,8 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += hda_verb.c + subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/coffeelake_rvp/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/hda_verb.c new file mode 100644 index 0000000..9ab4778 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/hda_verb.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h new file mode 100644 index 0000000..e258d95 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h @@ -0,0 +1,721 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + + 0x8086280B, + 0x00000000, + 0x00000005, + + /* + * Display Audio Verb Table + * For Gen9, Vendor Node ID is 08h + * Port to be exposed to the inbox driver in the vanilla mode: + * PORT C - BIT[7:6] = 01b + */ + 0x00878140, + /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ + AZALIA_PIN_CFG(0, 0x05, 0x18560010), + /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ + AZALIA_PIN_CFG(0, 0x06, 0x18560020), + /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ + AZALIA_PIN_CFG(0, 0x07, 0x18560030), + /* Disable the third converter and third Pin (NID 08h) */ + 0x00878140, + + /* ALC 700 */ + 0x10EC0700, + 0x00000000, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC10F2), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111F0), + AZALIA_PIN_CFG(0, 0x15, 0x411111F0), + AZALIA_PIN_CFG(0, 0x16, 0x411111F0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + AZALIA_PIN_CFG(0, 0x19, 0x04A11030), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x40622005), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x29, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 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0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/28781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79 Gerrit-Change-Number: 28781 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: WIP: generic: Add generic DMIC driver
by build bot (Jenkins) (Code Review) 28 Sep '18

28 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28778 ) Change subject: WIP: generic: Add generic DMIC driver ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28778/1/src/drivers/generic/dmic/chip.h File src/drivers/generic/dmic/chip.h: https://review.coreboot.org/#/c/28778/1/src/drivers/generic/dmic/chip.h@8 PS1, Line 8: unsigned modeswitch_delay_ms; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28778/1/src/drivers/generic/dmic/dmic.c File src/drivers/generic/dmic/dmic.c: https://review.coreboot.org/#/c/28778/1/src/drivers/generic/dmic/dmic.c@52 PS1, Line 52: acpi_dp_add_integer(dp, "modeswitch_delay_ms", config->modeswitch_delay_ms); line over 80 characters -- To view, visit https://review.coreboot.org/28778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic8c8be1aa04e8d35ad4827d81a37ee54c25dfc63 Gerrit-Change-Number: 28778 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 Sep 2018 01:02:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT
by Sathyanarayana Nujella (Code Review) 28 Sep '18

28 Sep '18

Hello Jairaj Arava, HARSHAPRIYA N, I'd like you to do a code review. Please visit https://review.coreboot.org/28780 to review the following change. Change subject: WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT ...................................................................... WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT DMIC Codec needs minimum clock ON time to function it correctly during switch from sleep-mode to wake-up mode. Hence adding modeswitch_delay_ms as per DMIC spec. BUG=b:112888584 TEST=Verified DT entry has modeswitch_delay_ms Change-Id: Iabf1d2329880d7e247efac00d2160606792dab00 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Signed-off-by: Jairaj Arava <jairaj.arava(a)intel.com> Signed-off-by: Harsha Priya <harshapriya.n(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28780/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 70a379c..6c3e007 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -434,6 +434,10 @@ chip ec/google/chromeec device pnp 0c09.0 on end end + chip drivers/generic/dmic + register "modeswitch_delay_ms" = "35" + device generic 0 on end + end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller -- To view, visit https://review.coreboot.org/28780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iabf1d2329880d7e247efac00d2160606792dab00 Gerrit-Change-Number: 28780 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com>

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Change in coreboot[master]: WIP: mb/google/poppy/Kconfig: add DMIC generic driver dependency
by Sathyanarayana Nujella (Code Review) 28 Sep '18

28 Sep '18

Hello Jairaj Arava, HARSHAPRIYA N, I'd like you to do a code review. Please visit https://review.coreboot.org/28779 to review the following change. Change subject: WIP: mb/google/poppy/Kconfig: add DMIC generic driver dependency ...................................................................... WIP: mb/google/poppy/Kconfig: add DMIC generic driver dependency DMIC generic driver is needed for passing config params. This can be used for all variants of poppy. So, adding dependency to BOARD_GOOGLE_BASEBOARD_POPPY BUG=b:112888584 TEST=Build and make sure DUT boots Change-Id: I8474537e37bd1a19665988cebf4c570da76402f1 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Signed-off-by: Jairaj Arava <jairaj.arava(a)intel.com> Signed-off-by: Harsha Priya <harshapriya.n(a)intel.com> --- M src/mainboard/google/poppy/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/28779/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index df59c5e..ef898fb 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_USES_FSP2_0 select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 + select DRIVERS_GENERIC_DMIC if BOARD_GOOGLE_BASEBOARD_POPPY -- To view, visit https://review.coreboot.org/28779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8474537e37bd1a19665988cebf4c570da76402f1 Gerrit-Change-Number: 28779 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com>

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Change in coreboot[master]: WIP: generic: Add generic DMIC driver
by Sathyanarayana Nujella (Code Review) 28 Sep '18

28 Sep '18

Hello Jairaj Arava, HARSHAPRIYA N, I'd like you to do a code review. Please visit https://review.coreboot.org/28778 to review the following change. Change subject: WIP: generic: Add generic DMIC driver ...................................................................... WIP: generic: Add generic DMIC driver DMIC driver in Kernel needs configurations like modeswitch_delay_ms which is used to adust the minimum clock ON time, etc. DMIC is not an I2S or I2C slave, so adding as a generic driver. BUG=b:112888584 TEST=build coreboot and cross check DUT boots Change-Id: Ic8c8be1aa04e8d35ad4827d81a37ee54c25dfc63 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Signed-off-by: Jairaj Arava <jairaj.arava(a)intel.com> Signed-off-by: Harsha Priya <harshapriya.n(a)intel.com> --- A src/drivers/generic/dmic/Kconfig A src/drivers/generic/dmic/Makefile.inc A src/drivers/generic/dmic/chip.h A src/drivers/generic/dmic/dmic.c 4 files changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/28778/1 diff --git a/src/drivers/generic/dmic/Kconfig b/src/drivers/generic/dmic/Kconfig new file mode 100644 index 0000000..5234eeb --- /dev/null +++ b/src/drivers/generic/dmic/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_DMIC + bool diff --git a/src/drivers/generic/dmic/Makefile.inc b/src/drivers/generic/dmic/Makefile.inc new file mode 100644 index 0000000..52bb984 --- /dev/null +++ b/src/drivers/generic/dmic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_DMIC) += dmic.c diff --git a/src/drivers/generic/dmic/chip.h b/src/drivers/generic/dmic/chip.h new file mode 100644 index 0000000..6cb19bd --- /dev/null +++ b/src/drivers/generic/dmic/chip.h @@ -0,0 +1,11 @@ +#ifndef __DRIVERS_GENERIC_DMIC__ +#define __DRIVERS_GENERIC_DMIC__ + +#include <arch/acpi_device.h> + +struct drivers_generic_dmic_config { + /* SDMODE Delay */ + unsigned modeswitch_delay_ms; +}; + +#endif diff --git a/src/drivers/generic/dmic/dmic.c b/src/drivers/generic/dmic/dmic.c new file mode 100644 index 0000000..e90f475 --- /dev/null +++ b/src/drivers/generic/dmic/dmic.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define DMIC_ACPI_NAME "DMIC" +#define DMIC_ACPI_HID "DMIC" + + +static void dmic_fill_ssdt(struct device *dev) +{ + struct drivers_generic_dmic_config *config = dev->chip_info; + const char *path; + struct acpi_dp *dp; + if (!config) + return; + + /* Device */ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", DMIC_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* _DSD for devicetree properties */ + /* This points to the first pin in the first gpio entry in _CRS */ + path = acpi_device_path(dev); + dp = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dp, "modeswitch_delay_ms", config->modeswitch_delay_ms); + acpi_dp_write(dp); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *dmic_acpi_name(const struct device *dev) +{ + return DMIC_ACPI_NAME; +} +#endif + +static struct device_operations dmic_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &dmic_acpi_name, + .acpi_fill_ssdt_generator = &dmic_fill_ssdt, +#endif +}; + +static void dmic_enable(struct device *dev) +{ + dev->ops = &dmic_ops; +} + +struct chip_operations drivers_generic_dmic_ops = { + CHIP_NAME("DMIC") + .enable_dev = &dmic_enable +}; -- To view, visit https://review.coreboot.org/28778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic8c8be1aa04e8d35ad4827d81a37ee54c25dfc63 Gerrit-Change-Number: 28778 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com>

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Change in coreboot[master]: mb/intel/whlrvp: Enable HDA controller driver
by Lijian Zhao (Code Review) 28 Sep '18

28 Sep '18

Lijian Zhao has abandoned this change. ( https://review.coreboot.org/28777 ) Change subject: mb/intel/whlrvp: Enable HDA controller driver ...................................................................... Abandoned Need Verb Table -- To view, visit https://review.coreboot.org/28777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I14345ae89dea517761c9de46a3961b780b63216f Gerrit-Change-Number: 28777 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd/stoneyridge: Load AOAC and USB gnvs values
by Marshall Dawson (Code Review) 28 Sep '18

28 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28767 ) Change subject: amd/stoneyridge: Load AOAC and USB gnvs values ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/28767/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 914: 1; > Search for "AOACx[7F:41:step2] Device D3 State" in the NDA BKDG (probably also available in the publ […] I'm aware of where the AOAC registers are defined, and I understand the aoac_device_enabled() intent. However, I pref using the device tree settings for these. They're probably more accurate a representation of the proper configuration. -- To view, visit https://review.coreboot.org/28767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Gerrit-Change-Number: 28767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 27 Sep 2018 22:13:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018