coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 01 Sep '18

01 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 29: (2 comments) https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@164 PS29, Line 164: if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) { line over 80 characters https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@189 PS29, Line 189: trailing whitespace -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 29 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Sat, 01 Sep 2018 15:12:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Evgeny Zinoviev (Code Review) 01 Sep '18

01 Sep '18

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/28393 ) Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… File src/mainboard/lenovo/t430s/romstage.c: https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… PS2, Line 72: enum hybrid_graphics_req mode = HYBRID_GRAPHICS_INTEGRATED; > Sorry for the confusion. […] There's a third way. We could move this code (I'm talking about the code that writes to pmh7 registers) to pmh7.c and call it `pmh7_dgpu_enable`, like `pmh7_backlight_enable` and other functions that are already there. This way we will not use hybrid graphics driver for T430s and also not duplicate dGPU on/off code. -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Sep 2018 13:12:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add sku info into smbios table
by Zhuohao Lee (Code Review) 01 Sep '18

01 Sep '18

Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/28426 Change subject: mb/google/poppy/variants/rammus: add sku info into smbios table ...................................................................... mb/google/poppy/variants/rammus: add sku info into smbios table This patch adds the mainboard.c in order to support the sku id in smbios table where the sku id is queried from the eeprom via EC. BUG=b:113714761 BRANCH=master TEST=check the result of 'dmidecode' Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/poppy/variants/rammus/Makefile.inc A src/mainboard/google/poppy/variants/rammus/include/variant/sku.h A src/mainboard/google/poppy/variants/rammus/mainboard.c 3 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/28426/1 diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index eed7c44..9db2c21 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -6,3 +6,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/poppy/variants/rammus/include/variant/sku.h b/src/mainboard/google/poppy/variants/rammus/include/variant/sku.h new file mode 100644 index 0000000..9ed3a0f --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/include/variant/sku.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ + +#define SKU_UNKNOWN 0xFFFFFFFF + +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/poppy/variants/rammus/mainboard.c b/src/mainboard/google/poppy/variants/rammus/mainboard.c new file mode 100644 index 0000000..eb64ddf --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/mainboard.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> +#include <smbios.h> +#include <string.h> +#include <variant/sku.h> + +uint32_t variant_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + uint32_t id; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + if (google_chromeec_cbi_get_sku_id(&id)) + return SKU_UNKNOWN; + sku_id = id; + + return sku_id; +} + +const char *smbios_mainboard_sku(void) +{ + static char sku_str[14]; /* sku{0..4294967295} */ + + snprintf(sku_str, sizeof(sku_str), "sku%u", variant_board_sku()); + + return sku_str; +} -- To view, visit https://review.coreboot.org/28426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Gerrit-Change-Number: 28426 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org>

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Change in coreboot[master]: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
by Jonathan Neuschäfer (Code Review) 01 Sep '18

01 Sep '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28394 ) Change subject: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/28394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Gerrit-Change-Number: 28394 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Sep 2018 09:51:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Patrick Rudolph (Code Review) 01 Sep '18

01 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28393 ) Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… File src/mainboard/lenovo/t430s/romstage.c: https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… PS2, Line 72: enum hybrid_graphics_req mode = HYBRID_GRAPHICS_INTEGRATED; > Well, here https://review.coreboot. […] Sorry for the confusion. Yes there's no hybrid graphics mux. In general it's discouraged to duplicate code. By using the proposed devicetree settings it does the same. I understand your argument of not using the driver as there's no hybrid graphics to avoid confusion. In that case please keep the code, but also rename the CMOS for t430s to something like "enable_dual_graphics". Otherwise end users will wonder why "discrete only" is missing and report it as a bug. -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 2 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Sep 2018 05:51:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
by Furquan Shaikh (Code Review) 01 Sep '18

01 Sep '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28424 ) Change subject: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28424/1/src/soc/intel/skylake/chip.h File src/soc/intel/skylake/chip.h: https://review.coreboot.org/#/c/28424/1/src/soc/intel/skylake/chip.h@157 PS1, Line 157: Enable/disable Just say "Disable" since this config is used to basically disable command tristate? -- To view, visit https://review.coreboot.org/28424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Gerrit-Change-Number: 28424 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Sat, 01 Sep 2018 00:05:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018