coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/drivers/spi/tpm: Fix typo & capitalize TPM and IRQ
by Martin Roth (Code Review) 02 Sep '18

02 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28387 ) Change subject: src/drivers/spi/tpm: Fix typo & capitalize TPM and IRQ ...................................................................... src/drivers/spi/tpm: Fix typo & capitalize TPM and IRQ Change-Id: Ifb1e024821153865dd4a27a100f8a9c61151e0e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28387 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/spi/tpm/tpm.c 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 3206ba1..bdd40a8 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -79,8 +79,8 @@ } /* - * TPM may trigger a irq after finish processing previous transfer. - * Waiting for this irq to sync tpm status. + * TPM may trigger a IRQ after finish processing previous transfer. + * Waiting for this IRQ to sync TPM status. * * Returns 1 on success, 0 on failure (timeout). */ @@ -91,7 +91,7 @@ stopwatch_init_msecs_expire(&sw, 10); while (!tis_plat_irq_status()) { if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, "Timeout wait for tpm irq!\n"); + printk(BIOS_ERR, "Timeout wait for TPM IRQ!\n"); return 0; } } @@ -119,7 +119,7 @@ */ int wakeup_needed = 1; - /* Wait for tpm to finish previous transaction if needed */ + /* Wait for TPM to finish previous transaction if needed */ if (car_get_var(tpm_sync_needed)) { tpm_sync(); /* @@ -430,7 +430,7 @@ memcpy(spi_slave, spi_if, sizeof(*spi_if)); - /* clear any pending irqs */ + /* clear any pending IRQs */ tis_plat_irq_status(); /* @@ -442,12 +442,12 @@ for (retries = 15; retries > 0; retries--) { int i; - /* In case of falure to read div_vid is set to zero. */ + /* In case of failure to read div_vid is set to zero. */ tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid)); for (i = 0; i < ARRAY_SIZE(supported_did_vids); i++) if (did_vid == supported_did_vids[i]) - break; /* Tpm is up and ready. */ + break; /* TPM is up and ready. */ if (i < ARRAY_SIZE(supported_did_vids)) break; @@ -643,7 +643,7 @@ write_tpm_sts(TPM_STS_COMMAND_READY); /* - * Tpm commands and responses written to and read from the FIFO + * TPM commands and responses written to and read from the FIFO * register (0x24) are datagrams of variable size, prepended by a 6 * byte header. * @@ -687,7 +687,7 @@ * TODO(vbendeb): at least drain the FIFO here or somehow let * the TPM know that the response can be dropped. */ - printk(BIOS_ERR, " tpm response too long (%zd bytes)", + printk(BIOS_ERR, " TPM response too long (%zd bytes)", payload_size); return 0; } -- To view, visit https://review.coreboot.org/28387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ifb1e024821153865dd4a27a100f8a9c61151e0e1 Gerrit-Change-Number: 28387 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1
by Martin Roth (Code Review) 02 Sep '18

02 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28400 ) Change subject: mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1 ...................................................................... mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1 This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node. Without DRIVERS_SPI_ACPI, the kernel will popped out the below error: cr50-update[592]: Starting cr50 update cr50_get_name[595]: updater is /usr/sbin/gsctool -s cr50-update[609]: exit status: 3 cr50-update[613]: output: Could not open TPM: No such file or directory cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod' cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state cr50-update[682]: not running cr50-result[782]: Not running normal image. Skip setting Board ID trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory BUG=none BRANCH=master TEST=/dev/tpm0 is created Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/28400 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 1645451..df59c5e 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -196,6 +196,7 @@ select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_I2C_MAX98927 select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_SORAKA -- To view, visit https://review.coreboot.org/28400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Gerrit-Change-Number: 28400 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/kahlee/var/liara: Enable Synaptics touchpad device
by Martin Roth (Code Review) 02 Sep '18

02 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28398 ) Change subject: mainboard/google/kahlee/var/liara: Enable Synaptics touchpad device ...................................................................... mainboard/google/kahlee/var/liara: Enable Synaptics touchpad device Enable Synaptics touchpad device for liara BUG=b:113309346 BRANCH=master TEST=Verify touchpad on liara works with this change Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Signed-off-by: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/variants/liara/devicetree.cb 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index bde91a1..9180906 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -20,6 +20,7 @@ select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index cf6dd5f..9b39b78 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -132,8 +132,18 @@ register "desc" = ""ELAN Touchpad"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "wake" = "7" + register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end device mmio 0xfedc5000 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/28398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Gerrit-Change-Number: 28398 Gerrit-PatchSet: 4 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/lint: update whitespace checking rules
by Martin Roth (Code Review) 02 Sep '18

02 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28431 Change subject: util/lint: update whitespace checking rules ...................................................................... util/lint: update whitespace checking rules - Check payloads, the root Makefiles and toolchain.inc - 3rdparty is already not checked, so remove - The marks around COPYING, LICENSE, and README were not needed - Skip checking .ico files Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2 Signed-off-by: Martin Roth <martinr(a)coreboot.org> --- M util/lint/lint-stable-003-whitespace 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28431/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 1a7dc7b..4a7b661 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,8 +15,8 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -EXCLUDELIST='^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$' -INCLUDELIST="src util" +EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$' +INCLUDELIST="src util payloads Make* toolchain.inc" # shellcheck disable=SC2086,SC2046 if uname | grep -qi "linux"; then -- To view, visit https://review.coreboot.org/28431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2 Gerrit-Change-Number: 28431 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: payloads: Remove/fix trailing whitespace
by Martin Roth (Code Review) 02 Sep '18

02 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28430 Change subject: payloads: Remove/fix trailing whitespace ...................................................................... payloads: Remove/fix trailing whitespace Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1 Signed-off-by: Martin Roth <martinr(a)coreboot.org> --- M payloads/bayou/Doxyfile M payloads/external/tianocore/tools_def.txt M payloads/libpayload/Doxyfile M payloads/libpayload/curses/form/frm_def.c M payloads/libpayload/include/queue.h 5 files changed, 189 insertions(+), 190 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28430/1 diff --git a/payloads/bayou/Doxyfile b/payloads/bayou/Doxyfile index 8aa0729..acab01c 100644 --- a/payloads/bayou/Doxyfile +++ b/payloads/bayou/Doxyfile @@ -800,7 +800,7 @@ HTML_FOOTER = -# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will +# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will # add generated date, project name and doxygen version to HTML footer. HTML_FOOTER_DESCRIPTION= YES diff --git a/payloads/external/tianocore/tools_def.txt b/payloads/external/tianocore/tools_def.txt index c5c9911..fba9b09 100755 --- a/payloads/external/tianocore/tools_def.txt +++ b/payloads/external/tianocore/tools_def.txt @@ -1,184 +1,183 @@ -# -# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved. -# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved. -# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2015, Hewlett-Packard Development Company, L.P. -# (C) Copyright 2016 Hewlett Packard Enterprise Development LP -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# - -#The following has been adapted from the BaseTools/Conf/tools_def.template file -#and is used to direct the Tianocore build to use coreboot's crossgcc toolchain -#rather than the host machine's toolchain - -DEFINE COREBOOT_IA32_PREFIX = ENV(GCC_CC_x86_32) -DEFINE COREBOOT_X64_PREFIX = ENV(GCC_CC_x86_64) -DEFINE COREBOOT_ARM_PREFIX = ENV(GCC_CC_arm) -DEFINE COREBOOT_ARM64_PREFIX = ENV(GCC_CC_arm64) - -DEFINE COREBOOT_IA32_OBJCOPY = ENV(OBJCOPY_x86_32) -DEFINE COREBOOT_X64_OBJCOPY = ENV(OBJCOPY_x86_64) -DEFINE COREBOOT_ARM_OBJCOPY = ENV(OBJCOPY_arm) -DEFINE COREBOOT_ARM64_OBJCOPY = ENV(OBJCOPY_arm64) - -#################################################################################### -# -# COREBOOT - This configuration is used to compile under Linux to produce -# PE/COFF binaries using coreboot's toolchain. -# -################################################################################## - -*_COREBOOT_*_*_FAMILY = GCC - -*_COREBOOT_*_MAKE_PATH = make -*_COREBOOT_*_*_DLL = ENV(GCC5_DLL) -*_COREBOOT_*_ASL_PATH = DEF(UNIX_IASL_BIN) - -*_COREBOOT_*_PP_FLAGS = DEF(GCC_PP_FLAGS) -*_COREBOOT_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) -*_COREBOOT_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -*_COREBOOT_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) -*_COREBOOT_*_APP_FLAGS = -*_COREBOOT_*_ASL_FLAGS = DEF(IASL_FLAGS) -*_COREBOOT_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS) - -################## -# COREBOOT IA32 definitions -################## -*_COREBOOT_IA32_OBJCOPY_PATH = DEF(COREBOOT_IA32_OBJCOPY) -*_COREBOOT_IA32_CC_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_SLINK_PATH = DEF(COREBOOT_IA32_PREFIX)-ar -*_COREBOOT_IA32_DLINK_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASLDLINK_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASM_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_PP_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_VFRPP_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASLCC_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASLPP_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_RC_PATH = DEF(COREBOOT_IA32_OBJCOPY) - -*_COREBOOT_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto -*_COREBOOT_IA32_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 -*_COREBOOT_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386 -*_COREBOOT_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) -*_COREBOOT_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS) -*_COREBOOT_IA32_OBJCOPY_FLAGS = -*_COREBOOT_IA32_NASM_FLAGS = -f elf32 - - DEBUG_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os - DEBUG_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 - -RELEASE_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os -Wno-unused-but-set-variable -RELEASE_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 - - NOOPT_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -O0 - NOOPT_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386 -O0 - -################## -# COREBOOT X64 definitions -################## -*_COREBOOT_X64_OBJCOPY_PATH = DEF(COREBOOT_X64_OBJCOPY) -*_COREBOOT_X64_CC_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_SLINK_PATH = DEF(COREBOOT_X64_PREFIX)-ar -*_COREBOOT_X64_DLINK_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASLDLINK_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASM_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_PP_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_VFRPP_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASLCC_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASLPP_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_RC_PATH = DEF(COREBOOT_X64_OBJCOPY) - -*_COREBOOT_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto -*_COREBOOT_X64_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64 -*_COREBOOT_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64 -*_COREBOOT_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) -*_COREBOOT_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS) -*_COREBOOT_X64_OBJCOPY_FLAGS = -*_COREBOOT_X64_NASM_FLAGS = -f elf64 - - DEBUG_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os - DEBUG_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os - -RELEASE_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable -RELEASE_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os - - NOOPT_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -O0 - NOOPT_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -O0 - -################## -# COREBOOT ARM definitions -################## -*_COREBOOT_ARM_CC_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_SLINK_PATH = ENV(COREBOOT_ARM_PREFIX)-ar -*_COREBOOT_ARM_DLINK_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASLDLINK_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASM_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_PP_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_VFRPP_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASLCC_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASLPP_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_RC_PATH = ENV(COREBOOT_ARM_OBJCOPY) - -*_COREBOOT_ARM_ARCHCC_FLAGS = -mthumb -*_COREBOOT_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -*_COREBOOT_ARM_ASLDLINK_FLAGS = DEF(GCC5_ARM_ASLDLINK_FLAGS) -*_COREBOOT_ARM_ASM_FLAGS = DEF(GCC5_ARM_ASM_FLAGS) -*_COREBOOT_ARM_DLINK2_FLAGS = DEF(GCC5_ARM_DLINK2_FLAGS) -*_COREBOOT_ARM_PLATFORM_FLAGS = -march=armv7-a -*_COREBOOT_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) -*_COREBOOT_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS) -*_COREBOOT_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) -*_COREBOOT_ARM_CC_XIPFLAGS = DEF(GCC5_ARM_CC_XIPFLAGS) - - DEBUG_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 - DEBUG_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) - -RELEASE_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable -RELEASE_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm - - NOOPT_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 - NOOPT_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -O0 - -################## -# COREBOOT AARCH64 definitions -################## -*_COREBOOT_AARCH64_CC_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_SLINK_PATH = ENV(COREBOOT_ARM64_PREFIX)-ar -*_COREBOOT_AARCH64_DLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASLDLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASM_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_PP_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_VFRPP_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASLCC_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASLPP_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_RC_PATH = ENV(COREBOOT_ARM64_OBJCOPY) - -*_COREBOOT_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -*_COREBOOT_AARCH64_ASLDLINK_FLAGS = DEF(GCC5_AARCH64_ASLDLINK_FLAGS) -*_COREBOOT_AARCH64_ASM_FLAGS = DEF(GCC5_AARCH64_ASM_FLAGS) -*_COREBOOT_AARCH64_DLINK2_FLAGS = DEF(GCC5_AARCH64_DLINK2_FLAGS) -*_COREBOOT_AARCH64_PLATFORM_FLAGS = -*_COREBOOT_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) -*_COREBOOT_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) -*_COREBOOT_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) -*_COREBOOT_AARCH64_CC_XIPFLAGS = DEF(GCC5_AARCH64_CC_XIPFLAGS) - - DEBUG_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small - DEBUG_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 - DEBUG_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 - -RELEASE_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -mcmodel=tiny -fomit-frame-pointer -RELEASE_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 - - NOOPT_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small - NOOPT_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 -O0 - NOOPT_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0 - +# +# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved. +# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved. +# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015, Hewlett-Packard Development Company, L.P. +# (C) Copyright 2016 Hewlett Packard Enterprise Development LP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +#The following has been adapted from the BaseTools/Conf/tools_def.template file +#and is used to direct the Tianocore build to use coreboot's crossgcc toolchain +#rather than the host machine's toolchain + +DEFINE COREBOOT_IA32_PREFIX = ENV(GCC_CC_x86_32) +DEFINE COREBOOT_X64_PREFIX = ENV(GCC_CC_x86_64) +DEFINE COREBOOT_ARM_PREFIX = ENV(GCC_CC_arm) +DEFINE COREBOOT_ARM64_PREFIX = ENV(GCC_CC_arm64) + +DEFINE COREBOOT_IA32_OBJCOPY = ENV(OBJCOPY_x86_32) +DEFINE COREBOOT_X64_OBJCOPY = ENV(OBJCOPY_x86_64) +DEFINE COREBOOT_ARM_OBJCOPY = ENV(OBJCOPY_arm) +DEFINE COREBOOT_ARM64_OBJCOPY = ENV(OBJCOPY_arm64) + +#################################################################################### +# +# COREBOOT - This configuration is used to compile under Linux to produce +# PE/COFF binaries using coreboot's toolchain. +# +################################################################################## + +*_COREBOOT_*_*_FAMILY = GCC + +*_COREBOOT_*_MAKE_PATH = make +*_COREBOOT_*_*_DLL = ENV(GCC5_DLL) +*_COREBOOT_*_ASL_PATH = DEF(UNIX_IASL_BIN) + +*_COREBOOT_*_PP_FLAGS = DEF(GCC_PP_FLAGS) +*_COREBOOT_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) +*_COREBOOT_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_*_APP_FLAGS = +*_COREBOOT_*_ASL_FLAGS = DEF(IASL_FLAGS) +*_COREBOOT_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS) + +################## +# COREBOOT IA32 definitions +################## +*_COREBOOT_IA32_OBJCOPY_PATH = DEF(COREBOOT_IA32_OBJCOPY) +*_COREBOOT_IA32_CC_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_SLINK_PATH = DEF(COREBOOT_IA32_PREFIX)-ar +*_COREBOOT_IA32_DLINK_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASLDLINK_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASM_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_PP_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_VFRPP_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASLCC_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASLPP_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_RC_PATH = DEF(COREBOOT_IA32_OBJCOPY) + +*_COREBOOT_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto +*_COREBOOT_IA32_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 +*_COREBOOT_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386 +*_COREBOOT_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) +*_COREBOOT_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS) +*_COREBOOT_IA32_OBJCOPY_FLAGS = +*_COREBOOT_IA32_NASM_FLAGS = -f elf32 + + DEBUG_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os + DEBUG_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 + +RELEASE_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os -Wno-unused-but-set-variable +RELEASE_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 + + NOOPT_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -O0 + NOOPT_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386 -O0 + +################## +# COREBOOT X64 definitions +################## +*_COREBOOT_X64_OBJCOPY_PATH = DEF(COREBOOT_X64_OBJCOPY) +*_COREBOOT_X64_CC_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_SLINK_PATH = DEF(COREBOOT_X64_PREFIX)-ar +*_COREBOOT_X64_DLINK_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASLDLINK_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASM_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_PP_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_VFRPP_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASLCC_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASLPP_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_RC_PATH = DEF(COREBOOT_X64_OBJCOPY) + +*_COREBOOT_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto +*_COREBOOT_X64_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64 +*_COREBOOT_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64 +*_COREBOOT_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) +*_COREBOOT_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS) +*_COREBOOT_X64_OBJCOPY_FLAGS = +*_COREBOOT_X64_NASM_FLAGS = -f elf64 + + DEBUG_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os + DEBUG_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os + +RELEASE_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable +RELEASE_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os + + NOOPT_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -O0 + NOOPT_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -O0 + +################## +# COREBOOT ARM definitions +################## +*_COREBOOT_ARM_CC_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_SLINK_PATH = ENV(COREBOOT_ARM_PREFIX)-ar +*_COREBOOT_ARM_DLINK_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASLDLINK_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASM_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_PP_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_VFRPP_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASLCC_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASLPP_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_RC_PATH = ENV(COREBOOT_ARM_OBJCOPY) + +*_COREBOOT_ARM_ARCHCC_FLAGS = -mthumb +*_COREBOOT_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_ARM_ASLDLINK_FLAGS = DEF(GCC5_ARM_ASLDLINK_FLAGS) +*_COREBOOT_ARM_ASM_FLAGS = DEF(GCC5_ARM_ASM_FLAGS) +*_COREBOOT_ARM_DLINK2_FLAGS = DEF(GCC5_ARM_DLINK2_FLAGS) +*_COREBOOT_ARM_PLATFORM_FLAGS = -march=armv7-a +*_COREBOOT_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) +*_COREBOOT_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS) +*_COREBOOT_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_ARM_CC_XIPFLAGS = DEF(GCC5_ARM_CC_XIPFLAGS) + + DEBUG_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 + DEBUG_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) + +RELEASE_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable +RELEASE_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm + + NOOPT_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 + NOOPT_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -O0 + +################## +# COREBOOT AARCH64 definitions +################## +*_COREBOOT_AARCH64_CC_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_SLINK_PATH = ENV(COREBOOT_ARM64_PREFIX)-ar +*_COREBOOT_AARCH64_DLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASLDLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASM_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_PP_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_VFRPP_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASLCC_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASLPP_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_RC_PATH = ENV(COREBOOT_ARM64_OBJCOPY) + +*_COREBOOT_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_AARCH64_ASLDLINK_FLAGS = DEF(GCC5_AARCH64_ASLDLINK_FLAGS) +*_COREBOOT_AARCH64_ASM_FLAGS = DEF(GCC5_AARCH64_ASM_FLAGS) +*_COREBOOT_AARCH64_DLINK2_FLAGS = DEF(GCC5_AARCH64_DLINK2_FLAGS) +*_COREBOOT_AARCH64_PLATFORM_FLAGS = +*_COREBOOT_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) +*_COREBOOT_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) +*_COREBOOT_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_AARCH64_CC_XIPFLAGS = DEF(GCC5_AARCH64_CC_XIPFLAGS) + + DEBUG_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small + DEBUG_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 + DEBUG_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 + +RELEASE_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -mcmodel=tiny -fomit-frame-pointer +RELEASE_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 + + NOOPT_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small + NOOPT_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 -O0 + NOOPT_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0 diff --git a/payloads/libpayload/Doxyfile b/payloads/libpayload/Doxyfile index 9844722..16f0c3b 100644 --- a/payloads/libpayload/Doxyfile +++ b/payloads/libpayload/Doxyfile @@ -806,7 +806,7 @@ HTML_FOOTER = -# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will +# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will # add generated date, project name and doxygen version to HTML footer. HTML_FOOTER_DESCRIPTION= YES diff --git a/payloads/libpayload/curses/form/frm_def.c b/payloads/libpayload/curses/form/frm_def.c index 54f743b..487b161 100644 --- a/payloads/libpayload/curses/form/frm_def.c +++ b/payloads/libpayload/curses/form/frm_def.c @@ -62,7 +62,7 @@ }; NCURSES_EXPORT_VAR(FORM *) _nc_Default_Form = &default_form; - + /*--------------------------------------------------------------------------- | Facility : libnform | Function : static FIELD *Insert_Field_By_Position( diff --git a/payloads/libpayload/include/queue.h b/payloads/libpayload/include/queue.h index e5f68af..7d579a7 100644 --- a/payloads/libpayload/include/queue.h +++ b/payloads/libpayload/include/queue.h @@ -95,15 +95,15 @@ struct name { \ struct type *slh_first; /* first element */ \ } - + #define SLIST_HEAD_INITIALIZER(head) \ { NULL } - + #define SLIST_ENTRY(type) \ struct { \ struct type *sle_next; /* next element */ \ } - + /* * Singly-linked List access methods. */ -- To view, visit https://review.coreboot.org/28430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1 Gerrit-Change-Number: 28430 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: util/lint: Update whitespace linter for FreeBSD
by Martin Roth (Code Review) 02 Sep '18

02 Sep '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28429 Change subject: util/lint: Update whitespace linter for FreeBSD ...................................................................... util/lint: Update whitespace linter for FreeBSD On FreeBSD, this test was failing with the error: "grep: Argument list too long" I found that changing this to other forms takes MUCH longer, so I left the original method mostly unchanged except for moving the include & exclude lists into variables. Currently, I'm setting all non-linux operating systems to use the second version. I'll update that if I find other that other OSes support the first. Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a Signed-off-by: Martin Roth <martinr(a)coreboot.org> --- M util/lint/lint-stable-003-whitespace 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/28429/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index d749f37..1a7dc7b 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,5 +15,21 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$)"` | \ - sed -e "s,^.*$,File & has lines ending with whitespace.," +EXCLUDELIST='^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$' +INCLUDELIST="src util" + +# shellcheck disable=SC2086,SC2046 +if uname | grep -qi "linux"; then + grep -l "[[:space:]][[:space:]]*$" \ + $(git ls-files $INCLUDELIST | \ + grep -Ev "($EXCLUDELIST)" ) | \ + sed -e "s,^.*$,File & has lines ending with whitespace.," +else + # The above form is much (100x) faster, but doesn't work + # on all systems. A for loop also works but takes 30% longer + git ls-files $INCLUDELIST | \ + grep -Ev "($EXCLUDELIST)" | \ + xargs -I % \ + grep -l "[[:space:]][[:space:]]*$" % | \ + sed -e "s,^.*$,File & has lines ending with whitespace.," +fi -- To view, visit https://review.coreboot.org/28429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a Gerrit-Change-Number: 28429 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Evgeny Zinoviev (Code Review) 02 Sep '18

02 Sep '18

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/28393 ) Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… File src/mainboard/lenovo/t430s/romstage.c: https://review.coreboot.org/#/c/28393/2/src/mainboard/lenovo/t430s/romstage… PS2, Line 72: > I'm fine with this solution. Done, but haven't been tested yet -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 6 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Sep 2018 22:07:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Evgeny Zinoviev (Code Review) 02 Sep '18

02 Sep '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28393 to look at the new patch set (#6). Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads Add CMOS option that allows to use both integrated and discrete GPU. Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- M src/drivers/lenovo/hybrid_graphics/romstage.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/lenovo/pmh7/pmh7.h M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/t530/romstage.c 15 files changed, 68 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/28393/6 -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 6 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Evgeny Zinoviev (Code Review) 02 Sep '18

02 Sep '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28393 to look at the new patch set (#5). Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads Add CMOS option that allows to use both integrated and discrete GPU. Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- M src/drivers/lenovo/hybrid_graphics/romstage.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/lenovo/pmh7/pmh7.h M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/t530/romstage.c 15 files changed, 69 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/28393/5 -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 5 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by build bot (Jenkins) (Code Review) 02 Sep '18

02 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28393 ) Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/28393/4/src/mainboard/lenovo/t430s/romstage… File src/mainboard/lenovo/t430s/romstage.c: https://review.coreboot.org/#/c/28393/4/src/mainboard/lenovo/t430s/romstage… PS4, Line 73: if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 4 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Sep 2018 22:03:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018