coreboot-gerrit September 2018

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Change in coreboot[master]: cpu/intel/model_206ax: detect number of MCE banks
by Dan Elkouby (Code Review) 03 Sep '18

03 Sep '18

Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/28443 Change subject: cpu/intel/model_206ax: detect number of MCE banks ...................................................................... cpu/intel/model_206ax: detect number of MCE banks My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset only 7. This causes Linux to spuriously log errors during boot and S3 resume. Fix this by reading the real value from the right MSR. Change-Id: Id05645009259fd77b4de49bde518361eeae46617 --- M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/28443/1 diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 7cb4069..98203b6 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -39,6 +39,7 @@ #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401 +#define IA32_MCG_CAP 0x179 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 75631c1..3cc8d82 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,10 +414,14 @@ { msr_t msr; int i; + int num_banks; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ - for (i = 0; i < 7; i++) + for (i = 0; i < num_banks; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -- To view, visit https://review.coreboot.org/28443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Gerrit-Change-Number: 28443 Gerrit-PatchSet: 1 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com>

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Change in coreboot[master]: arch/x86/Makefile: include dependencies for romcc bootblock
by Nico Huber (Code Review) 03 Sep '18

03 Sep '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28442 Change subject: arch/x86/Makefile: include dependencies for romcc bootblock ...................................................................... arch/x86/Makefile: include dependencies for romcc bootblock We already explicitly generated a dependencies file for the romcc bootblock. Though, as it has its own rule and isn't registered to any of our object-file classes, the dependencies file wasn't included automatically. Change-Id: I441cf229312dff82f377dcb594939fb85c441eed Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/arch/x86/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/28442/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1d9ee4d..584902a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -145,6 +145,7 @@ cat $^ >> $@.tmp mv $@.tmp $@ +-include $(objgenerated)/bootblock.inc.d $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) # The open quote in the subst messes with syntax highlighting. Fix it - ") @printf " ROMCC $(subst $(obj)/,,$(@))\n" -- To view, visit https://review.coreboot.org/28442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I441cf229312dff82f377dcb594939fb85c441eed Gerrit-Change-Number: 28442 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: mb/emulation/qemu x86: Use scratchpad for RAM size
by Nico Huber (Code Review) 03 Sep '18

03 Sep '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28441 Change subject: mb/emulation/qemu x86: Use scratchpad for RAM size ...................................................................... mb/emulation/qemu x86: Use scratchpad for RAM size Qemu communicates its RAM size through some bytes in CMOS. This works fine as long as we don't try to use CMOS for configuration. If we do, i.e. with CONFIG_USE_OPTION_TABLE enabled, these bytes would be erased on boot (because of a checksum mismatch) even if we'd reserve them in `cmos.layout`. Instead of patching our option table implementation, we work around the issue in Qemu's mainboard code: Before the option table is initialized, we copy the RAM size to a scratchpad in the northbridge's PCI device. Note: The scratchpad used is actually only for i440fx, but as there is no real emulation of the northbridge, this works for q35 too. Change-Id: I5d4a238feb252561ad2dac06c44b9398bf908105 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc A src/mainboard/emulation/qemu-i440fx/bootblock.c M src/mainboard/emulation/qemu-i440fx/memory.c A src/mainboard/emulation/qemu-i440fx/memory.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/emulation/qemu-q35/romstage.c 10 files changed, 126 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/28441/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index fc56ab6..b779bbf 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -21,6 +21,10 @@ string default "QEMU x86 i440fx/piix4" +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "mainboard/emulation/qemu-i440fx/bootblock.c" + config IRQ_SLOT_COUNT int default 6 diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index f9cf252..525b4c2 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,3 +1,5 @@ cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +romstage-y += memory.c +ramstage-y += memory.c ramstage-y += northbridge.c ramstage-y += fw_cfg.c diff --git a/src/mainboard/emulation/qemu-i440fx/bootblock.c b/src/mainboard/emulation/qemu-i440fx/bootblock.c new file mode 100644 index 0000000..e409cb3 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/bootblock.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <pc80/mc146818rtc.h> +#include "memory.h" + +void bootblock_northbridge_init(void) +{ + /* + * We have to cache Qemu's RAM size (from CMOS) for the case + * that USE_OPTION_TABLE is enabled. We use a scratchpad in + * D0F0 for this. + */ + + unsigned long tomk; + tomk = (unsigned long)cmos_read(HIGH_RAM_ADDR) << 14; + tomk |= (unsigned long)cmos_read(LOW_RAM_ADDR) << 6; + tomk += 16 * 1024; + pci_write_config32(PCI_DEV(0, 0x00, 0), QEMU_D0F0_SCRATCHPAD, tomk); + + unsigned long high; + high = (unsigned long)cmos_read(HIGH_HIGHRAM_ADDR) << 22; + high |= (unsigned long)cmos_read(MID_HIGHRAM_ADDR) << 14; + high |= (unsigned long)cmos_read(LOW_HIGHRAM_ADDR) << 6; + pci_write_config32(PCI_DEV(0, 0x00, 0), QEMU_D0F0_SCRATCHPAD + 4, high); +} diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index b8109e5..12d9a96 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -13,27 +13,34 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> #include <cbmem.h> +#include "memory.h" -#define CMOS_ADDR_PORT 0x70 -#define CMOS_DATA_PORT 0x71 - -#define HIGH_RAM_ADDR 0x35 -#define LOW_RAM_ADDR 0x34 - -#define HIGH_HIGHRAM_ADDR 0x5d -#define MID_HIGHRAM_ADDR 0x5c -#define LOW_HIGHRAM_ADDR 0x5b - -static unsigned long qemu_get_memory_size(void) +unsigned long qemu_get_memory_size(void) { - unsigned long tomk; - outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT); - tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; - outb (LOW_RAM_ADDR, CMOS_ADDR_PORT); - tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; - tomk += 16 * 1024; - return tomk; +#ifdef __SIMPLE_DEVICE__ + const device_t d0f0 = PCI_DEV(0, 0x00, 0); +#else + struct device *const d0f0 = dev_find_slot(0, PCI_DEVFN(0x00, 0)); + if (!d0f0) + return 16 * 1024; +#endif + return pci_read_config32(d0f0, QEMU_D0F0_SCRATCHPAD); +} + +unsigned long qemu_get_high_memory_size(void) +{ +#ifdef __SIMPLE_DEVICE__ + const device_t d0f0 = PCI_DEV(0, 0x00, 0); +#else + struct device *const d0f0 = dev_find_slot(0, PCI_DEVFN(0x00, 0)); + if (!d0f0) + return 16 * 1024; +#endif + return pci_read_config32(d0f0, QEMU_D0F0_SCRATCHPAD + 4); } void *cbmem_top(void) diff --git a/src/mainboard/emulation/qemu-i440fx/memory.h b/src/mainboard/emulation/qemu-i440fx/memory.h new file mode 100644 index 0000000..753ef63 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/memory.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EMULATION_QEMU_I440FX_MEMORY_H +#define MAINBOARD_EMULATION_QEMU_I440FX_MEMORY_H 1 + +#define HIGH_RAM_ADDR 0x35 +#define LOW_RAM_ADDR 0x34 + +#define HIGH_HIGHRAM_ADDR 0x5d +#define MID_HIGHRAM_ADDR 0x5c +#define LOW_HIGHRAM_ADDR 0x5b + +#define QEMU_D0F0_SCRATCHPAD 0xd0 + +unsigned long qemu_get_memory_size(void); +unsigned long qemu_get_high_memory_size(void); + +#endif diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index aa309de..5711e72 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -28,21 +28,9 @@ #include "fw_cfg.h" #include "fw_cfg_if.h" -#include "memory.c" +#include "memory.h" #include "acpi.h" -static unsigned long qemu_get_high_memory_size(void) -{ - unsigned long high; - outb (HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high = ((unsigned long) inb(CMOS_DATA_PORT)) << 22; - outb (MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 14; - outb (LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; - return high; -} - static void qemu_reserve_ports(struct device *dev, unsigned int idx, unsigned int base, unsigned int size, const char *name) diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index ce12a8b..decd85f 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -24,8 +24,7 @@ #include <timestamp.h> #include <delay.h> #include <cpu/x86/lapic.h> - -#include "memory.c" +#include <cbmem.h> void *asmlinkage romstage_main(unsigned long bist) { diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index fc4374c..cb85def 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,3 +1,5 @@ cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +romstage-y += ../qemu-i440fx/memory.c +ramstage-y += ../qemu-i440fx/memory.c ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += ../qemu-i440fx/fw_cfg.c diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 3625cf9..b190cfc 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -12,6 +12,8 @@ */ #include <arch/io.h> +#include <pc80/mc146818rtc.h> +#include "../qemu-i440fx/memory.h" /* Just define these here, there is no gm35.h file to include. */ #define D0F0_PCIEXBAR_LO 0x60 @@ -37,6 +39,28 @@ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + + /* + * We have to cache Qemu's RAM size (from CMOS) for the case + * that USE_OPTION_TABLE is enabled. We use a scratchpad in + * D0F0 for this. + * Warning: This is actually a scratchpad address for I440FX, + * but it is not used in Qemu's emulated Q35. Although unlikely, + * this may break in the future. We could use an actual scratch- + * pad register (0xdc) but this is already used for timestamps + * in ICH9. + */ + unsigned long tomk; + tomk = (unsigned long)cmos_read(HIGH_RAM_ADDR) << 14; + tomk |= (unsigned long)cmos_read(LOW_RAM_ADDR) << 6; + tomk += 16 * 1024; + pci_write_config32(PCI_DEV(0, 0x00, 0), QEMU_D0F0_SCRATCHPAD, tomk); + + unsigned long high; + high = (unsigned long)cmos_read(HIGH_HIGHRAM_ADDR) << 22; + high |= (unsigned long)cmos_read(MID_HIGHRAM_ADDR) << 14; + high |= (unsigned long)cmos_read(LOW_HIGHRAM_ADDR) << 6; + pci_write_config32(PCI_DEV(0, 0x00, 0), QEMU_D0F0_SCRATCHPAD + 4, high); } static void bootblock_mainboard_init(void) diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 870dd07..8f6a479 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -26,8 +26,7 @@ #include <timestamp.h> #include <delay.h> #include <cpu/x86/lapic.h> - -#include "../qemu-i440fx/memory.c" +#include <cbmem.h> void * asmlinkage romstage_main(unsigned long bist) { -- To view, visit https://review.coreboot.org/28441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d4a238feb252561ad2dac06c44b9398bf908105 Gerrit-Change-Number: 28441 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV
by Seunghwan Kim (Code Review) 03 Sep '18

03 Sep '18

Hello Marx Wang, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28439 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV ...................................................................... mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV Nautilus-Wifi with m3 AP got a halt issue during CTS test. Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was validated only with Celeron. Since Celeron deos not support turbo boost mode, its steady power demend and lower CPU frequency may not reflect the potential noise hidden inside the board. Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the potential noise coupling to VCC_GT/SA, and we verified this change makes this issue go away on Nautilus-Wifi board. Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have better grounding and less noise/ripple than 8L PCB. BUG=b:111417632 BRANCH=poppy TEST=Verified CTS test pass without an issue. Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/poppy/variants/nautilus/Makefile.inc M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/nautilus/memory.c A src/mainboard/google/poppy/variants/nautilus/sku.c 6 files changed, 78 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28439/2 -- To view, visit https://review.coreboot.org/28439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Gerrit-Change-Number: 28439 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mend
by Seunghwan Kim (Code Review) 03 Sep '18

03 Sep '18

Seunghwan Kim has abandoned this change. ( https://review.coreboot.org/28440 ) Change subject: mend ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I7cd1e128a779d997dd682f65c46c5ade9262dcef Gerrit-Change-Number: 28440 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: mend
by Seunghwan Kim (Code Review) 03 Sep '18

03 Sep '18

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/28440 Change subject: mend ...................................................................... mend Change-Id: I7cd1e128a779d997dd682f65c46c5ade9262dcef --- M 3rdparty/blobs M src/mainboard/google/poppy/variants/nautilus/mainboard.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28440/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 372012e..d2e558a 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 372012e8e1d0d01f3e77ff73b118665b41ff68b6 +Subproject commit d2e558a81f95f7b9149bea6b8362bb43ade82584 diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 32e9b97..41653e3 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -20,7 +20,6 @@ #include <smbios.h> #include <string.h> #include <variant/sku.h> -#include <console/console.h> #define R_PCH_OC_WDT_CTL 0x54 #define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 -- To view, visit https://review.coreboot.org/28440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7cd1e128a779d997dd682f65c46c5ade9262dcef Gerrit-Change-Number: 28440 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV
by Seunghwan Kim (Code Review) 03 Sep '18

03 Sep '18

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/28439 Change subject: mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV ...................................................................... mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV Nautilus-Wifi with m3 AP got a halt issue during CTS test. Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was validated only with Celeron. Since Celeron deos not support turbo boost mode, its steady power demend and lower CPU frequency may not reflect the potential noise hidden inside the board. Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the potential noise coupling to VCC_GT/SA, and we verified this change makes this issue go away on Nautilus-Wifi board. Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have better grounding and less noise/ripple than 8L PCB. BUG=b:111417632 BRANCH=poppy TEST=Verified CTS test pass without an issue. Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/poppy/variants/nautilus/Makefile.inc M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/nautilus/memory.c A src/mainboard/google/poppy/variants/nautilus/sku.c 6 files changed, 79 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28439/1 diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index af4f70b..adc13ed 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -173,4 +173,9 @@ mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mem_cfg->MemorySpdDataLen = spd_info[p.type].len; + + if (p.enable_sa_oc_support) { + mem_cfg->SaOcSupport = 1; + mem_cfg->SaVoltageOffset = p.sa_voltage_offset_val; + } } diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index 391f809..ef41c9b 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -54,6 +54,8 @@ const void *rcomp_target; size_t rcomp_target_size; bool use_sec_spd; + bool enable_sa_oc_support; + uint16_t sa_voltage_offset_val; }; void variant_memory_params(struct memory_params *p); diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc index d52893e..130c940 100644 --- a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc @@ -7,9 +7,11 @@ romstage-y += memory.c romstage-y += gpio.c +romstage-y += sku.c ramstage-y += gpio.c ramstage-y += nhlt.c ramstage-y += mainboard.c +ramstage-y += sku.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index e51370c..32e9b97 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -15,32 +15,17 @@ #include <baseboard/variants.h> #include <chip.h> -#include <gpio.h> #include <device/device.h> +#include <device/pci.h> #include <smbios.h> #include <string.h> #include <variant/sku.h> +#include <console/console.h> -uint32_t variant_board_sku(void) -{ - static uint32_t sku_id = SKU_UNKNOWN; - - if (sku_id != SKU_UNKNOWN) - return sku_id; - - /* - * Nautilus uses GPP_B20 to determine SKU - * 0 - Wifi SKU - * 1 - LTE SKU - */ - gpio_input_pulldown(GPP_B20); - if (!gpio_get(GPP_B20)) - sku_id = SKU_0_NAUTILUS; - else - sku_id = SKU_1_NAUTILUS_LTE; - - return sku_id; -} +#define R_PCH_OC_WDT_CTL 0x54 +#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 +#define B_PCH_OC_WDT_CTL_EN BIT14 +#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 const char *smbios_mainboard_sku(void) { @@ -57,11 +42,22 @@ uint32_t sku_id = variant_board_sku(); struct device *root = SA_DEV_ROOT; config_t *cfg = root->chip_info; + uint16_t abase; + uint32_t val32; switch (sku_id) { case SKU_0_NAUTILUS: /* Disable LTE module */ cfg->usb3_ports[3].enable = 0; + + /* Enabling SaOcSupport flag makes OC_WDT be enabled in FSP-M. + * We should clear OC_WDT to prevent turning the system off. */ + abase = pci_read_config16(PCH_DEV_PMC, ABASE) & 0xfffc; + val32 = inl(abase + R_PCH_OC_WDT_CTL); + val32 &= ~(B_PCH_OC_WDT_CTL_EN | + B_PCH_OC_WDT_CTL_FORCE_ALL | + B_PCH_OC_WDT_CTL_UNXP_RESET_STS); + outl(val32, abase + R_PCH_OC_WDT_CTL); break; case SKU_1_NAUTILUS_LTE: diff --git a/src/mainboard/google/poppy/variants/nautilus/memory.c b/src/mainboard/google/poppy/variants/nautilus/memory.c index dc845bc..a0dd76b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/memory.c +++ b/src/mainboard/google/poppy/variants/nautilus/memory.c @@ -14,6 +14,7 @@ */ #include <baseboard/variants.h> +#include <variant/sku.h> /* DQ byte map */ static const u8 dq_map[][12] = { @@ -46,4 +47,13 @@ p->rcomp_resistor_size = sizeof(rcomp_resistor); p->rcomp_target = rcomp_target; p->rcomp_target_size = sizeof(rcomp_target); + + switch (variant_board_sku()) { + case SKU_0_NAUTILUS: + /* Bumping VCC_SA voltage offset 75mV to allow a + * tolerance to PLLGT on Nautilus-Wifi sku */ + p->enable_sa_oc_support = 1; + p->sa_voltage_offset_val = 75; + break; + } } diff --git a/src/mainboard/google/poppy/variants/nautilus/sku.c b/src/mainboard/google/poppy/variants/nautilus/sku.c new file mode 100644 index 0000000..55b118d --- /dev/null +++ b/src/mainboard/google/poppy/variants/nautilus/sku.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <variant/sku.h> + +uint32_t variant_board_sku(void) +{ +#if ENV_ROMSTAGE + uint32_t sku_id = SKU_UNKNOWN; +#else + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; +#endif + + /* + * Nautilus uses GPP_B20 to determine SKU + * 0 - Wifi SKU + * 1 - LTE SKU + */ + gpio_input_pulldown(GPP_B20); + if (!gpio_get(GPP_B20)) + sku_id = SKU_0_NAUTILUS; + else + sku_id = SKU_1_NAUTILUS_LTE; + + return sku_id; +} -- To view, visit https://review.coreboot.org/28439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Gerrit-Change-Number: 28439 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Evgeny Zinoviev (Code Review) 03 Sep '18

03 Sep '18

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/28393 ) Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/28393/7/src/mainboard/lenovo/t430s/cmos.lay… File src/mainboard/lenovo/t430s/cmos.layout: https://review.coreboot.org/#/c/28393/7/src/mainboard/lenovo/t430s/cmos.lay… PS7, Line 79: 435 1 e 1 enable_dual_graphics > 1 Done https://review.coreboot.org/#/c/28393/7/src/mainboard/lenovo/t430s/cmos.lay… PS7, Line 96: 1 0 Disable > use enum 1 already in the list Done -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 8 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Sep 2018 10:45:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads
by Evgeny Zinoviev (Code Review) 03 Sep '18

03 Sep '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28393 to look at the new patch set (#8). Change subject: mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads ...................................................................... mb/lenovo: Dual Graphics for xx20/xx30 ThinkPads Add CMOS option that allows to use both integrated and discrete GPU. Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> --- M src/drivers/lenovo/hybrid_graphics/romstage.c M src/ec/lenovo/pmh7/pmh7.c M src/ec/lenovo/pmh7/pmh7.h M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/t530/romstage.c 15 files changed, 66 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/28393/8 -- To view, visit https://review.coreboot.org/28393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Gerrit-Change-Number: 28393 Gerrit-PatchSet: 8 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/fsp2_0: Add FSP NEXT shared stack feature support
by build bot (Jenkins) (Code Review) 03 Sep '18

03 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28358 ) Change subject: intel/fsp2_0: Add FSP NEXT shared stack feature support ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/28358/8/src/drivers/intel/fsp2_0/memory_ini… File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/#/c/28358/8/src/drivers/intel/fsp2_0/memory_ini… PS8, Line 203: if(setup_fsp_stack_frame(arch_upd, memmap)) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/28358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Gerrit-Change-Number: 28358 Gerrit-PatchSet: 8 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 03 Sep 2018 08:42:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018