coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
by Shaunak Saha (Code Review) 04 Sep '18

04 Sep '18

Shaunak Saha has uploaded a new patch set (#2). ( https://review.coreboot.org/28424 ) Change subject: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree ...................................................................... soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree This patch adds the support for CmdTriStateDis FSP upd in skylake soc structure so that we can define it in devicetree.CmdTriStateDis needed to be set for the skylake/kabylake based boards where LPDDR3 design is without RTT for CMD/CTRL.We need to set this bit for those designs for the margin to be proper. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28424/2 -- To view, visit https://review.coreboot.org/28424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Gerrit-Change-Number: 28424 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
by Shaunak Saha (Code Review) 04 Sep '18

04 Sep '18

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/28424 ) Change subject: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28424/1/src/soc/intel/skylake/chip.h File src/soc/intel/skylake/chip.h: https://review.coreboot.org/#/c/28424/1/src/soc/intel/skylake/chip.h@157 PS1, Line 157: Enable/disable > Just say "Disable" since this config is used to basically disable command tristate? Ack -- To view, visit https://review.coreboot.org/28424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Gerrit-Change-Number: 28424 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 04 Sep 2018 18:18:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus/variants/fleex: Enable TBMC device
by Amanda Hwang (Code Review) 04 Sep '18

04 Sep '18

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/28466 Change subject: mb/google/octopus/variants/fleex: Enable TBMC device ...................................................................... mb/google/octopus/variants/fleex: Enable TBMC device This change enables tablet mode ACPI device for fleex. BUG=b:113348027 Change-Id: I69a5dd41cd0958b93f8eed338fed4b6ee77a178f Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28466/1 diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h index 16f931b..48cb584 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + #endif -- To view, visit https://review.coreboot.org/28466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I69a5dd41cd0958b93f8eed338fed4b6ee77a178f Gerrit-Change-Number: 28466 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>

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Change in coreboot[master]: vendorcode/google/chromeos: Move enable_update from BS_PAYLOAD_LOAD t...
by Subrata Banik (Code Review) 04 Sep '18

04 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28465 Change subject: vendorcode/google/chromeos: Move enable_update from BS_PAYLOAD_LOAD to BS_WRITE_TABLES ...................................................................... vendorcode/google/chromeos: Move enable_update from BS_PAYLOAD_LOAD to BS_WRITE_TABLES This patch changes the sequence of enable_update() function because of post_cpus_init() is assume to be executed at very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path. But later with enable_update() function introduction into BS_STATE machine execution its now gettings executed to ON_ENTRY of BS_PAYLOAD_LOAD which is just next to BS_WRITE_TABLES state. This leads to some rare cases when post_cpus_init() function is still on going and enable_update() function is getting timeout. TEST=enable_update() is gettings called before post_cpus_init() during BS_STATE machine execution. Change-Id: I85def7028bd21c8729b0f5857652900a3f848cdd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/google/chromeos/cr50_enable_update.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28465/1 diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index d07a9a3..6e14522 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -71,4 +71,4 @@ } halt(); } -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, enable_update, NULL); +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, enable_update, NULL); -- To view, visit https://review.coreboot.org/28465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I85def7028bd21c8729b0f5857652900a3f848cdd Gerrit-Change-Number: 28465 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: util/lint: update whitespace checking rules
by Patrick Georgi (Code Review) 04 Sep '18

04 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28431 ) Change subject: util/lint: update whitespace checking rules ...................................................................... util/lint: update whitespace checking rules - Check payloads, the root Makefiles and toolchain.inc - 3rdparty is already not checked, so remove - The marks around COPYING, LICENSE, and README were not needed - Skip checking .ico files Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2 Signed-off-by: Martin Roth <martinr(a)coreboot.org> Reviewed-on: https://review.coreboot.org/28431 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M util/lint/lint-stable-003-whitespace 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Jonathan Neuschäfer: Looks good to me, but someone else must approve diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 1a7dc7b..f9b7891 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,8 +15,8 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -EXCLUDELIST='^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$' -INCLUDELIST="src util" +EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$' +INCLUDELIST="src util payloads Makefile* toolchain.inc" # shellcheck disable=SC2086,SC2046 if uname | grep -qi "linux"; then -- To view, visit https://review.coreboot.org/28431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2 Gerrit-Change-Number: 28431 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads: Remove/fix trailing whitespace
by Patrick Georgi (Code Review) 04 Sep '18

04 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28430 ) Change subject: payloads: Remove/fix trailing whitespace ...................................................................... payloads: Remove/fix trailing whitespace Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1 Signed-off-by: Martin Roth <martinr(a)coreboot.org> Reviewed-on: https://review.coreboot.org/28430 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M payloads/bayou/Doxyfile M payloads/external/tianocore/tools_def.txt M payloads/libpayload/Doxyfile M payloads/libpayload/curses/form/frm_def.c M payloads/libpayload/include/queue.h 5 files changed, 189 insertions(+), 190 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/payloads/bayou/Doxyfile b/payloads/bayou/Doxyfile index 8aa0729..acab01c 100644 --- a/payloads/bayou/Doxyfile +++ b/payloads/bayou/Doxyfile @@ -800,7 +800,7 @@ HTML_FOOTER = -# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will +# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will # add generated date, project name and doxygen version to HTML footer. HTML_FOOTER_DESCRIPTION= YES diff --git a/payloads/external/tianocore/tools_def.txt b/payloads/external/tianocore/tools_def.txt index c5c9911..fba9b09 100755 --- a/payloads/external/tianocore/tools_def.txt +++ b/payloads/external/tianocore/tools_def.txt @@ -1,184 +1,183 @@ -# -# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved. -# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved. -# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. -# Copyright (c) 2015, Hewlett-Packard Development Company, L.P. -# (C) Copyright 2016 Hewlett Packard Enterprise Development LP -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# - -#The following has been adapted from the BaseTools/Conf/tools_def.template file -#and is used to direct the Tianocore build to use coreboot's crossgcc toolchain -#rather than the host machine's toolchain - -DEFINE COREBOOT_IA32_PREFIX = ENV(GCC_CC_x86_32) -DEFINE COREBOOT_X64_PREFIX = ENV(GCC_CC_x86_64) -DEFINE COREBOOT_ARM_PREFIX = ENV(GCC_CC_arm) -DEFINE COREBOOT_ARM64_PREFIX = ENV(GCC_CC_arm64) - -DEFINE COREBOOT_IA32_OBJCOPY = ENV(OBJCOPY_x86_32) -DEFINE COREBOOT_X64_OBJCOPY = ENV(OBJCOPY_x86_64) -DEFINE COREBOOT_ARM_OBJCOPY = ENV(OBJCOPY_arm) -DEFINE COREBOOT_ARM64_OBJCOPY = ENV(OBJCOPY_arm64) - -#################################################################################### -# -# COREBOOT - This configuration is used to compile under Linux to produce -# PE/COFF binaries using coreboot's toolchain. -# -################################################################################## - -*_COREBOOT_*_*_FAMILY = GCC - -*_COREBOOT_*_MAKE_PATH = make -*_COREBOOT_*_*_DLL = ENV(GCC5_DLL) -*_COREBOOT_*_ASL_PATH = DEF(UNIX_IASL_BIN) - -*_COREBOOT_*_PP_FLAGS = DEF(GCC_PP_FLAGS) -*_COREBOOT_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) -*_COREBOOT_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -*_COREBOOT_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) -*_COREBOOT_*_APP_FLAGS = -*_COREBOOT_*_ASL_FLAGS = DEF(IASL_FLAGS) -*_COREBOOT_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS) - -################## -# COREBOOT IA32 definitions -################## -*_COREBOOT_IA32_OBJCOPY_PATH = DEF(COREBOOT_IA32_OBJCOPY) -*_COREBOOT_IA32_CC_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_SLINK_PATH = DEF(COREBOOT_IA32_PREFIX)-ar -*_COREBOOT_IA32_DLINK_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASLDLINK_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASM_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_PP_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_VFRPP_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASLCC_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_ASLPP_PATH = DEF(COREBOOT_IA32_PREFIX) -*_COREBOOT_IA32_RC_PATH = DEF(COREBOOT_IA32_OBJCOPY) - -*_COREBOOT_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto -*_COREBOOT_IA32_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 -*_COREBOOT_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386 -*_COREBOOT_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) -*_COREBOOT_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS) -*_COREBOOT_IA32_OBJCOPY_FLAGS = -*_COREBOOT_IA32_NASM_FLAGS = -f elf32 - - DEBUG_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os - DEBUG_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 - -RELEASE_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os -Wno-unused-but-set-variable -RELEASE_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 - - NOOPT_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -O0 - NOOPT_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386 -O0 - -################## -# COREBOOT X64 definitions -################## -*_COREBOOT_X64_OBJCOPY_PATH = DEF(COREBOOT_X64_OBJCOPY) -*_COREBOOT_X64_CC_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_SLINK_PATH = DEF(COREBOOT_X64_PREFIX)-ar -*_COREBOOT_X64_DLINK_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASLDLINK_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASM_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_PP_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_VFRPP_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASLCC_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_ASLPP_PATH = DEF(COREBOOT_X64_PREFIX) -*_COREBOOT_X64_RC_PATH = DEF(COREBOOT_X64_OBJCOPY) - -*_COREBOOT_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto -*_COREBOOT_X64_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64 -*_COREBOOT_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64 -*_COREBOOT_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) -*_COREBOOT_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS) -*_COREBOOT_X64_OBJCOPY_FLAGS = -*_COREBOOT_X64_NASM_FLAGS = -f elf64 - - DEBUG_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os - DEBUG_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os - -RELEASE_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable -RELEASE_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os - - NOOPT_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -O0 - NOOPT_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -O0 - -################## -# COREBOOT ARM definitions -################## -*_COREBOOT_ARM_CC_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_SLINK_PATH = ENV(COREBOOT_ARM_PREFIX)-ar -*_COREBOOT_ARM_DLINK_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASLDLINK_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASM_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_PP_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_VFRPP_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASLCC_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_ASLPP_PATH = ENV(COREBOOT_ARM_PREFIX) -*_COREBOOT_ARM_RC_PATH = ENV(COREBOOT_ARM_OBJCOPY) - -*_COREBOOT_ARM_ARCHCC_FLAGS = -mthumb -*_COREBOOT_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -*_COREBOOT_ARM_ASLDLINK_FLAGS = DEF(GCC5_ARM_ASLDLINK_FLAGS) -*_COREBOOT_ARM_ASM_FLAGS = DEF(GCC5_ARM_ASM_FLAGS) -*_COREBOOT_ARM_DLINK2_FLAGS = DEF(GCC5_ARM_DLINK2_FLAGS) -*_COREBOOT_ARM_PLATFORM_FLAGS = -march=armv7-a -*_COREBOOT_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) -*_COREBOOT_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS) -*_COREBOOT_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) -*_COREBOOT_ARM_CC_XIPFLAGS = DEF(GCC5_ARM_CC_XIPFLAGS) - - DEBUG_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 - DEBUG_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) - -RELEASE_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable -RELEASE_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm - - NOOPT_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 - NOOPT_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -O0 - -################## -# COREBOOT AARCH64 definitions -################## -*_COREBOOT_AARCH64_CC_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_SLINK_PATH = ENV(COREBOOT_ARM64_PREFIX)-ar -*_COREBOOT_AARCH64_DLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASLDLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASM_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_PP_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_VFRPP_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASLCC_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_ASLPP_PATH = ENV(COREBOOT_ARM64_PREFIX) -*_COREBOOT_AARCH64_RC_PATH = ENV(COREBOOT_ARM64_OBJCOPY) - -*_COREBOOT_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -*_COREBOOT_AARCH64_ASLDLINK_FLAGS = DEF(GCC5_AARCH64_ASLDLINK_FLAGS) -*_COREBOOT_AARCH64_ASM_FLAGS = DEF(GCC5_AARCH64_ASM_FLAGS) -*_COREBOOT_AARCH64_DLINK2_FLAGS = DEF(GCC5_AARCH64_DLINK2_FLAGS) -*_COREBOOT_AARCH64_PLATFORM_FLAGS = -*_COREBOOT_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) -*_COREBOOT_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) -*_COREBOOT_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) -*_COREBOOT_AARCH64_CC_XIPFLAGS = DEF(GCC5_AARCH64_CC_XIPFLAGS) - - DEBUG_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small - DEBUG_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 - DEBUG_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 - -RELEASE_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -mcmodel=tiny -fomit-frame-pointer -RELEASE_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 - - NOOPT_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small - NOOPT_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 -O0 - NOOPT_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0 - +# +# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved. +# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved. +# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015, Hewlett-Packard Development Company, L.P. +# (C) Copyright 2016 Hewlett Packard Enterprise Development LP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +#The following has been adapted from the BaseTools/Conf/tools_def.template file +#and is used to direct the Tianocore build to use coreboot's crossgcc toolchain +#rather than the host machine's toolchain + +DEFINE COREBOOT_IA32_PREFIX = ENV(GCC_CC_x86_32) +DEFINE COREBOOT_X64_PREFIX = ENV(GCC_CC_x86_64) +DEFINE COREBOOT_ARM_PREFIX = ENV(GCC_CC_arm) +DEFINE COREBOOT_ARM64_PREFIX = ENV(GCC_CC_arm64) + +DEFINE COREBOOT_IA32_OBJCOPY = ENV(OBJCOPY_x86_32) +DEFINE COREBOOT_X64_OBJCOPY = ENV(OBJCOPY_x86_64) +DEFINE COREBOOT_ARM_OBJCOPY = ENV(OBJCOPY_arm) +DEFINE COREBOOT_ARM64_OBJCOPY = ENV(OBJCOPY_arm64) + +#################################################################################### +# +# COREBOOT - This configuration is used to compile under Linux to produce +# PE/COFF binaries using coreboot's toolchain. +# +################################################################################## + +*_COREBOOT_*_*_FAMILY = GCC + +*_COREBOOT_*_MAKE_PATH = make +*_COREBOOT_*_*_DLL = ENV(GCC5_DLL) +*_COREBOOT_*_ASL_PATH = DEF(UNIX_IASL_BIN) + +*_COREBOOT_*_PP_FLAGS = DEF(GCC_PP_FLAGS) +*_COREBOOT_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) +*_COREBOOT_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_*_APP_FLAGS = +*_COREBOOT_*_ASL_FLAGS = DEF(IASL_FLAGS) +*_COREBOOT_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS) + +################## +# COREBOOT IA32 definitions +################## +*_COREBOOT_IA32_OBJCOPY_PATH = DEF(COREBOOT_IA32_OBJCOPY) +*_COREBOOT_IA32_CC_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_SLINK_PATH = DEF(COREBOOT_IA32_PREFIX)-ar +*_COREBOOT_IA32_DLINK_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASLDLINK_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASM_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_PP_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_VFRPP_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASLCC_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_ASLPP_PATH = DEF(COREBOOT_IA32_PREFIX) +*_COREBOOT_IA32_RC_PATH = DEF(COREBOOT_IA32_OBJCOPY) + +*_COREBOOT_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto +*_COREBOOT_IA32_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 +*_COREBOOT_IA32_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m32 -march=i386 +*_COREBOOT_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) +*_COREBOOT_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS) +*_COREBOOT_IA32_OBJCOPY_FLAGS = +*_COREBOOT_IA32_NASM_FLAGS = -f elf32 + + DEBUG_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os + DEBUG_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 + +RELEASE_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -flto -Os -Wno-unused-but-set-variable +RELEASE_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 + + NOOPT_COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) -O0 + NOOPT_COREBOOT_IA32_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386 -O0 + +################## +# COREBOOT X64 definitions +################## +*_COREBOOT_X64_OBJCOPY_PATH = DEF(COREBOOT_X64_OBJCOPY) +*_COREBOOT_X64_CC_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_SLINK_PATH = DEF(COREBOOT_X64_PREFIX)-ar +*_COREBOOT_X64_DLINK_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASLDLINK_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASM_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_PP_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_VFRPP_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASLCC_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_ASLPP_PATH = DEF(COREBOOT_X64_PREFIX) +*_COREBOOT_X64_RC_PATH = DEF(COREBOOT_X64_OBJCOPY) + +*_COREBOOT_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto +*_COREBOOT_X64_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64 +*_COREBOOT_X64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) -m64 +*_COREBOOT_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) +*_COREBOOT_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS) +*_COREBOOT_X64_OBJCOPY_FLAGS = +*_COREBOOT_X64_NASM_FLAGS = -f elf64 + + DEBUG_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os + DEBUG_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os + +RELEASE_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable +RELEASE_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os + + NOOPT_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -O0 + NOOPT_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -O0 + +################## +# COREBOOT ARM definitions +################## +*_COREBOOT_ARM_CC_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_SLINK_PATH = ENV(COREBOOT_ARM_PREFIX)-ar +*_COREBOOT_ARM_DLINK_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASLDLINK_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASM_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_PP_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_VFRPP_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASLCC_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_ASLPP_PATH = ENV(COREBOOT_ARM_PREFIX) +*_COREBOOT_ARM_RC_PATH = ENV(COREBOOT_ARM_OBJCOPY) + +*_COREBOOT_ARM_ARCHCC_FLAGS = -mthumb +*_COREBOOT_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_ARM_ASLDLINK_FLAGS = DEF(GCC5_ARM_ASLDLINK_FLAGS) +*_COREBOOT_ARM_ASM_FLAGS = DEF(GCC5_ARM_ASM_FLAGS) +*_COREBOOT_ARM_DLINK2_FLAGS = DEF(GCC5_ARM_DLINK2_FLAGS) +*_COREBOOT_ARM_PLATFORM_FLAGS = -march=armv7-a +*_COREBOOT_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) +*_COREBOOT_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS) +*_COREBOOT_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_ARM_CC_XIPFLAGS = DEF(GCC5_ARM_CC_XIPFLAGS) + + DEBUG_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 + DEBUG_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) + +RELEASE_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable +RELEASE_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm + + NOOPT_COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) -O0 + NOOPT_COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) -O0 + +################## +# COREBOOT AARCH64 definitions +################## +*_COREBOOT_AARCH64_CC_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_SLINK_PATH = ENV(COREBOOT_ARM64_PREFIX)-ar +*_COREBOOT_AARCH64_DLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASLDLINK_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASM_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_PP_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_VFRPP_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASLCC_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_ASLPP_PATH = ENV(COREBOOT_ARM64_PREFIX) +*_COREBOOT_AARCH64_RC_PATH = ENV(COREBOOT_ARM64_OBJCOPY) + +*_COREBOOT_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_AARCH64_ASLDLINK_FLAGS = DEF(GCC5_AARCH64_ASLDLINK_FLAGS) +*_COREBOOT_AARCH64_ASM_FLAGS = DEF(GCC5_AARCH64_ASM_FLAGS) +*_COREBOOT_AARCH64_DLINK2_FLAGS = DEF(GCC5_AARCH64_DLINK2_FLAGS) +*_COREBOOT_AARCH64_PLATFORM_FLAGS = +*_COREBOOT_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) +*_COREBOOT_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) +*_COREBOOT_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_AARCH64_CC_XIPFLAGS = DEF(GCC5_AARCH64_CC_XIPFLAGS) + + DEBUG_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small + DEBUG_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 + DEBUG_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 + +RELEASE_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -mcmodel=tiny -fomit-frame-pointer +RELEASE_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 + + NOOPT_COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) -O0 -mcmodel=small + NOOPT_COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 -O0 + NOOPT_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0 diff --git a/payloads/libpayload/Doxyfile b/payloads/libpayload/Doxyfile index 9844722..16f0c3b 100644 --- a/payloads/libpayload/Doxyfile +++ b/payloads/libpayload/Doxyfile @@ -806,7 +806,7 @@ HTML_FOOTER = -# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will +# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will # add generated date, project name and doxygen version to HTML footer. HTML_FOOTER_DESCRIPTION= YES diff --git a/payloads/libpayload/curses/form/frm_def.c b/payloads/libpayload/curses/form/frm_def.c index 54f743b..487b161 100644 --- a/payloads/libpayload/curses/form/frm_def.c +++ b/payloads/libpayload/curses/form/frm_def.c @@ -62,7 +62,7 @@ }; NCURSES_EXPORT_VAR(FORM *) _nc_Default_Form = &default_form; - + /*--------------------------------------------------------------------------- | Facility : libnform | Function : static FIELD *Insert_Field_By_Position( diff --git a/payloads/libpayload/include/queue.h b/payloads/libpayload/include/queue.h index e5f68af..7d579a7 100644 --- a/payloads/libpayload/include/queue.h +++ b/payloads/libpayload/include/queue.h @@ -95,15 +95,15 @@ struct name { \ struct type *slh_first; /* first element */ \ } - + #define SLIST_HEAD_INITIALIZER(head) \ { NULL } - + #define SLIST_ENTRY(type) \ struct { \ struct type *sle_next; /* next element */ \ } - + /* * Singly-linked List access methods. */ -- To view, visit https://review.coreboot.org/28430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1 Gerrit-Change-Number: 28430 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/lint: Update whitespace linter for FreeBSD
by Patrick Georgi (Code Review) 04 Sep '18

04 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28429 ) Change subject: util/lint: Update whitespace linter for FreeBSD ...................................................................... util/lint: Update whitespace linter for FreeBSD On FreeBSD, this test was failing with the error: "grep: Argument list too long" I found that changing this to other forms takes MUCH longer, so I left the original method mostly unchanged except for moving the include & exclude lists into variables. Currently, I'm setting all non-linux operating systems to use the second version. I'll update that if I find other that other OSes support the first. Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a Signed-off-by: Martin Roth <martinr(a)coreboot.org> Reviewed-on: https://review.coreboot.org/28429 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M util/lint/lint-stable-003-whitespace 1 file changed, 18 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index d749f37..1a7dc7b 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,5 +15,21 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$)"` | \ - sed -e "s,^.*$,File & has lines ending with whitespace.," +EXCLUDELIST='^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$' +INCLUDELIST="src util" + +# shellcheck disable=SC2086,SC2046 +if uname | grep -qi "linux"; then + grep -l "[[:space:]][[:space:]]*$" \ + $(git ls-files $INCLUDELIST | \ + grep -Ev "($EXCLUDELIST)" ) | \ + sed -e "s,^.*$,File & has lines ending with whitespace.," +else + # The above form is much (100x) faster, but doesn't work + # on all systems. A for loop also works but takes 30% longer + git ls-files $INCLUDELIST | \ + grep -Ev "($EXCLUDELIST)" | \ + xargs -I % \ + grep -l "[[:space:]][[:space:]]*$" % | \ + sed -e "s,^.*$,File & has lines ending with whitespace.," +fi -- To view, visit https://review.coreboot.org/28429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a Gerrit-Change-Number: 28429 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/rammus: add sku info into smbios table
by Patrick Georgi (Code Review) 04 Sep '18

04 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28426 ) Change subject: mb/google/poppy/variants/rammus: add sku info into smbios table ...................................................................... mb/google/poppy/variants/rammus: add sku info into smbios table This patch adds the mainboard.c in order to support the sku id in smbios table where the sku id is queried from the eeprom via EC. BUG=b:113714761 BRANCH=master TEST=check the result of 'dmidecode' Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/28426 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/rammus/Makefile.inc A src/mainboard/google/poppy/variants/rammus/mainboard.c 2 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index eed7c44..9db2c21 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -6,3 +6,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/poppy/variants/rammus/mainboard.c b/src/mainboard/google/poppy/variants/rammus/mainboard.c new file mode 100644 index 0000000..a3474d4 --- /dev/null +++ b/src/mainboard/google/poppy/variants/rammus/mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> +#include <smbios.h> +#include <string.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +uint32_t variant_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + uint32_t id; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + if (google_chromeec_cbi_get_sku_id(&id)) + return SKU_UNKNOWN; + sku_id = id; + + return sku_id; +} + +const char *smbios_mainboard_sku(void) +{ + static char sku_str[14]; /* sku{0..4294967295} */ + + snprintf(sku_str, sizeof(sku_str), "sku%u", variant_board_sku()); + + return sku_str; +} -- To view, visit https://review.coreboot.org/28426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Gerrit-Change-Number: 28426 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
by Patrick Georgi (Code Review) 04 Sep '18

04 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28394 ) Change subject: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page ...................................................................... riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page Must to set MXR, when needs to read the page which is execution-only. So make this change. Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Signed-off-by: Xiang Wang <wxjstz(a)126.com> Reviewed-on: https://review.coreboot.org/28394 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/include/vm.h 1 file changed, 16 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index a30d6bb..749c9c8 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -38,11 +38,11 @@ void mstatus_init(void); // need to setup mstatus so we know we have virtual memory -#define DEFINE_MPRV_READ(name, type, insn) \ +#define DEFINE_MPRV_READ_FLAGS(name, type, insn, flags) \ static inline type name(type *p); \ static inline type name(type *p) \ { \ - size_t mprv = MSTATUS_MPRV; \ + size_t mprv = flags; \ type value; \ asm ( \ "csrs mstatus, %1\n" \ @@ -53,6 +53,12 @@ return value; \ } +#define DEFINE_MPRV_READ(name, type, insn) \ + DEFINE_MPRV_READ_FLAGS(name, type, insn, MSTATUS_MPRV) + +#define DEFINE_MPRV_READ_MXR(name, type, insn) \ + DEFINE_MPRV_READ_FLAGS(name, type, insn, MSTATUS_MPRV | MSTATUS_MXR) + #define DEFINE_MPRV_WRITE(name, type, insn) \ static inline void name(type *p, type value); \ static inline void name(type *p, type value) \ @@ -83,6 +89,12 @@ DEFINE_MPRV_READ(mprv_read_u64, uint64_t, ld) DEFINE_MPRV_READ(mprv_read_long, long, ld) DEFINE_MPRV_READ(mprv_read_ulong, unsigned long, ld) +DEFINE_MPRV_READ_MXR(mprv_read_mxr_u8, uint8_t, lbu) +DEFINE_MPRV_READ_MXR(mprv_read_mxr_u16, uint16_t, lhu) +DEFINE_MPRV_READ_MXR(mprv_read_mxr_u32, uint32_t, lwu) +DEFINE_MPRV_READ_MXR(mprv_read_mxr_u64, uint64_t, ld) +DEFINE_MPRV_READ_MXR(mprv_read_mxr_long, long, ld) +DEFINE_MPRV_READ_MXR(mprv_read_mxr_ulong, unsigned long, ld) DEFINE_MPRV_WRITE(mprv_write_u8, uint8_t, sb) DEFINE_MPRV_WRITE(mprv_write_u16, uint16_t, sh) DEFINE_MPRV_WRITE(mprv_write_u32, uint32_t, sw) @@ -90,8 +102,9 @@ DEFINE_MPRV_WRITE(mprv_write_long, long, sd) DEFINE_MPRV_WRITE(mprv_write_ulong, unsigned long, sd) +#undef DEFINE_MPRV_READ_FLAGS #undef DEFINE_MPRV_READ +#undef DEFINE_MPRV_READ_MXR #undef DEFINE_MPRV_WRITE - #endif -- To view, visit https://review.coreboot.org/28394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Gerrit-Change-Number: 28394 Gerrit-PatchSet: 4 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/drivers/intel/fsp1_1: Configure UART after memory init
by Frans Hendriks (Code Review) 04 Sep '18

04 Sep '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/28464 Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... src/drivers/intel/fsp1_1: Configure UART after memory init FSP code will default enable the onboard serial port. When external serial port is used, this onboard port needs to be disabled. Add function mainboard_after_memory_init() function to perform required actions to re-enabled output to external serial port. BUG=N/A TEST=LPC Post card on Intel Cherry Hill Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/raminit.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28464/1 diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index d79be70..1524fe2 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -3,6 +3,7 @@ * * Copyright (C) 2014 Google Inc. * Copyright (C) 2015-2016 Intel Corporation + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -92,5 +93,6 @@ /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, struct mma_config_param *mma_cfg); +void mainboard_after_memory_init(void); #endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index e5714ae..1af1ad0 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014-2016 Intel Corporation + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -125,6 +126,7 @@ timestamp_add_now(TS_FSP_MEMORY_INIT_START); post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); + mainboard_after_memory_init(); post_code(0x37); timestamp_add_now(TS_FSP_MEMORY_INIT_END); @@ -319,3 +321,10 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +/* Initialize the SoC after MemoryInit */ +__weak void mainboard_after_memory_init( + void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} -- To view, visit https://review.coreboot.org/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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coreboot-gerrit September 2018