coreboot-gerrit September 2018

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Change in coreboot[master]: amd/stoneyridge: Create an MCA structure
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28476 Change subject: amd/stoneyridge: Create an MCA structure ...................................................................... amd/stoneyridge: Create an MCA structure Convert the Machine Check reporting to use a newly defined structure. This will facilitate later patches that will pass pointers to the MSR values. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/mca.c 1 file changed, 26 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28476/1 diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index b782ef3..bcaa927 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -20,6 +20,14 @@ #include <soc/northbridge.h> #include <console/console.h> +struct mca_bank { + msr_t ctl; + msr_t sts; + msr_t addr; + msr_t misc; + msr_t cmask; +}; + static const char *const mca_bank_name[] = { "Load-store unit", "Instruction fetch unit", @@ -33,45 +41,46 @@ void check_mca(void) { int i; - msr_t msr; + msr_t cap; + struct mca_bank mci; int num_banks; - msr = rdmsr(MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; + cap = rdmsr(MCG_CAP); + num_banks = cap.lo & MCA_BANKS_MASK; if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { if (i == 3) /* Reserved in Family 15h */ continue; - msr = rdmsr(MC0_STATUS + (i * 4)); - if (msr.hi || msr.lo) { + mci.sts = rdmsr(MC0_STATUS + (i * 4)); + if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", core, i, mca_bank_name[i]); printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_ADDR + (i * 4)); + i, mci.sts.hi, mci.sts.lo); + mci.addr = rdmsr(MC0_ADDR + (i * 4)); printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_MISC + (i * 4)); + i, mci.addr.hi, mci.addr.lo); + mci.misc = rdmsr(MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL + (i * 4)); + i, mci.misc.hi, mci.misc.lo); + mci.ctl = rdmsr(MC0_CTL + (i * 4)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + i); + i, mci.ctl.hi, mci.ctl.lo); + mci.cmask = rdmsr(MC0_CTL_MASK + i); printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, msr.hi, msr.lo); + i, mci.cmask.hi, mci.cmask.lo); } } } /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; + mci.sts.lo = 0; + mci.sts.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), mci.sts); } -- To view, visit https://review.coreboot.org/28476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff Gerrit-Change-Number: 28476 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/fam15: Add more MCA information
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28473 Change subject: amd/fam15: Add more MCA information ...................................................................... amd/fam15: Add more MCA information Add more definitions to be used for Machine Check Architecture support, mainly for determining the type of error that is being interpreted. MCA is described in detail in the BKDG. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/cpu/amd/amdfam15.h 1 file changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28473/1 diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 1441c05..bafd2b8 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -16,13 +16,175 @@ #ifndef CPU_AMD_FAM15_H #define CPU_AMD_FAM15_H +#include <types.h> +#include <cpu/x86/msr.h> + #define MCG_CAP 0x00000179 # define MCA_BANKS_MASK 0xff #define MC0_CTL 0x00000400 #define MC0_STATUS 0x00000401 +# define MCA_STATUS_HI_VAL BIT(63 - 32) +# define MCA_STATUS_HI_OVERFLOW BIT(62 - 32) +# define MCA_STATUS_HI_UC BIT(61 - 32) +# define MCA_STATUS_HI_EN BIT(60 - 32) +# define MCA_STATUS_HI_MISCV BIT(59 - 32) +# define MCA_STATUS_HI_ADDRV BIT(58 - 32) +# define MCA_STATUS_HI_PCC BIT(57 - 32) +# define MCA_STATUS_HI_COREID_VAL BIT(56 - 32) +# define MCA_STATUS_HI_CECC BIT(46 - 32) +# define MCA_STATUS_HI_UECC BIT(45 - 32) +# define MCA_STATUS_HI_DEFERRED BIT(44 - 32) +# define MCA_STATUS_HI_POISON BIT(43 - 32) +# define MCA_STATUS_HI_SUBLINK BIT(41 - 32) +# define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0) +# define MCA_STATUS_LO_ERRCODE_EXT_SH 16 +# define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) +# define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) #define MC0_ADDR 0x00000402 #define MC0_MISC 0x00000403 #define MC0_CTL_MASK 0xC0010044 + +/* Helpers for interpreting MC[i]_STATUS */ + +static inline int mca_valid(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_VAL); +} + +static inline int mca_over(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_OVERFLOW); +} + +static inline int mca_uc(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_UC); +} + +static inline int mca_en(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_EN); +} + +static inline int mca_miscv(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_MISCV); +} + +static inline int mca_addrv(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_ADDRV); +} + +static inline int mca_pcc(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_PCC); +} + +static inline int mca_idv(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_COREID_VAL); +} + +static inline int mca_cecc(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_CECC); +} + +static inline int mca_uecc(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_UECC); +} + +static inline int mca_defd(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_DEFERRED); +} + +static inline int mca_poison(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_POISON); +} + +static inline int mca_sublink(msr_t msr) +{ + return !!(msr.hi & MCA_STATUS_HI_SUBLINK); +} + +static inline uint16_t mca_err_code(msr_t reg) +{ + return reg.lo &= MCA_STATUS_LO_ERRCODE_MASK; +} + +static inline uint16_t mca_err_extcode(msr_t reg) +{ + return reg.lo &= MCA_STATUS_LO_ERRCODE_EXT_MASK; +} + +/* TLB Errors 0000 0000 0001 TTLL */ +#define MCA_ERRCODE_TLB_DETECT 0xfff0 +#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */ +#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH) +#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */ +#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH) + +/* Memory Errors 0000 0001 RRRR TTLL */ +#define MCA_ERRCODE_MEM_DETECT 0xff00 +#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */ +#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK) +#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */ +#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH) +#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */ +#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH) + +/* Bus Errors 0000 1PPT RRRR IILL */ +#define MCA_ERRCODE_BUS_DETECT 0xf800 +#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */ +#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH) +#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */ +#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH) +#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */ +#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH) +#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */ +#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH) +#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */ +#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH) + +/* Int. Unclassified Errors 0000 01UU 0000 0000 */ +#define MCA_ERRCODE_INT_DETECT 0xfc00 +#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */ +#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH) + +#define MCA_BANK_LS 0 /* Load-store, including DC */ +#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */ +#define MCA_BANK_CU 2 /* Combined Unit, including L2 */ +/* bank 3 reserved */ +#define MCA_BANK_NB 4 /* Northbridge, including IO link */ +#define MCA_BANK_EX 5 /* Execution Unit */ +#define MCA_BANK_FP 6 /* Floating Point */ + +enum mca_err_code_types { + MCA_ERRTYPE_UNKNOWN, + MCA_ERRTYPE_TLB, + MCA_ERRTYPE_MEM, + MCA_ERRTYPE_BUS, + MCA_ERRTYPE_INT +}; + +static inline enum mca_err_code_types mca_err_type(msr_t reg) +{ + uint16_t error = mca_err_code(reg); + if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */ + return MCA_ERRTYPE_BUS; + if (error & MCA_ERRCODE_INT_DETECT) + return MCA_ERRTYPE_INT; + if (error & MCA_ERRCODE_MEM_DETECT) + return MCA_ERRTYPE_MEM; + if (error & MCA_ERRCODE_TLB_DETECT) + return MCA_ERRTYPE_TLB; + return MCA_ERRTYPE_UNKNOWN; +} + #define MSR_SMM_BASE 0xC0010111 #define MSR_TSEG_BASE 0xC0010112 #define MSR_SMM_MASK 0xC0010113 -- To view, visit https://review.coreboot.org/28473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68 Gerrit-Change-Number: 28473 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Adjust memory map for reserved
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28474 Change subject: amd/stoneyridge: Adjust memory map for reserved ...................................................................... amd/stoneyridge: Adjust memory map for reserved Carve out memory to be reported to the OS as reserved. This makes room for a region usable for Boot Error Record Table information. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/ramtop.c 1 file changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28474/1 diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 24386ed..57bb71e 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -23,6 +23,7 @@ #include <cpu/amd/amdfam15.h> #include <cbmem.h> #include <stage_cache.h> +#include <arch/bert_storage.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -36,6 +37,21 @@ return biosram_read32(BIOSRAM_CBMEM_TOP); } +#if IS_ENABLED(CONFIG_ACPI_BERT) +#define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE +#else +#define BERT_REGION_MAX_SIZE 0 +#endif + +void bert_reserved_region(void **start, size_t *size) +{ + if (IS_ENABLED(CONFIG_ACPI_BERT)) + *start = cbmem_top(); + else + start = NULL; + *size = BERT_REGION_MAX_SIZE; +} + void *cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -45,12 +61,13 @@ else /* 8MB alignment to keep MTRR usage low */ return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE, 8*MiB); + - CONFIG_SMM_TSEG_SIZE + - BERT_REGION_MAX_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top(); + return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) -- To view, visit https://review.coreboot.org/28474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18 Gerrit-Change-Number: 28474 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: x86/acpi: Add BERT table
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28472 Change subject: x86/acpi: Add BERT table ...................................................................... x86/acpi: Add BERT table Create a structure for the Boot Error Record Table, and a generic table generator function. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28472/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index d334eb3..d75d889 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -958,6 +958,27 @@ header->checksum = acpi_checksum((void *)hest, header->length); } +/* ACPI 3.0b */ +void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) +{ + acpi_header_t *header = &(bert->header); + + memset(bert, 0, sizeof(acpi_bert_t)); + + memcpy(header->signature, "BERT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->length += sizeof(acpi_bert_t); + header->revision = get_acpi_table_revision(BERT); + + bert->error_region = region; + bert->region_length = length; + + /* Calculate checksums. */ + header->checksum = acpi_checksum((void *)bert, header->length); +} + #if IS_ENABLED(CONFIG_COMMON_FADT) void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index cf223e5..6991235 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -644,6 +644,13 @@ u32 error_threshold_win; } __packed acpi_hest_hen_t; +/* BERT (Boot Error Record Table) */ +typedef struct acpi_bert { + struct acpi_table_header header; + u32 region_length; + u64 error_region; +} __packed acpi_bert_t; + /* Generic Error Data Entry. */ typedef struct acpi_hest_generic_data { guid_t section_type; @@ -751,6 +758,7 @@ unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); +void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length); void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); #if IS_ENABLED(CONFIG_COMMON_FADT) void acpi_fill_fadt(acpi_fadt_t *fadt); -- To view, visit https://review.coreboot.org/28472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538 Gerrit-Change-Number: 28472 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: x86/acpi: add BERT to the revision table
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28471 Change subject: x86/acpi: add BERT to the revision table ...................................................................... x86/acpi: add BERT to the revision table Add the proper table revision level for the Boot Error Record Table. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib4596fe8c0dd2a4e2e98df3a1bb60803c48d0256 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28471/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 0701bbe..d334eb3 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1296,6 +1296,8 @@ return 1; case NHLT: return 5; + case BERT: + return 1; default: return -1; } -- To view, visit https://review.coreboot.org/28471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4596fe8c0dd2a4e2e98df3a1bb60803c48d0256 Gerrit-Change-Number: 28471 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: src/include: Add CPER definitions
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28468 Change subject: src/include: Add CPER definitions ...................................................................... src/include: Add CPER definitions Add definitions from the UEFI appendix on Common Platform Error Record (appx. N in revision 2.7-A). The structures and fields defined are the minimum required for generating ACPI Boot Error Record data in a subsequent patch. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/include/cper.h 1 file changed, 507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28468/1 diff --git a/src/include/cper.h b/src/include/cper.h new file mode 100644 index 0000000..06e8c95 --- /dev/null +++ b/src/include/cper.h @@ -0,0 +1,507 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPER_H_ +#define _CPER_H_ + +#include <types.h> +#include <uuid.h> +#include <bcd.h> +#include <rtc.h> + +/* This file contains some definitions and helpers for implementing structures + * in the UEFI specification, Appendix "Common Platform Error Record". This + * is not a complete definition, but contains enough to generate a BERT ACPI + * table. + * + * All table numbers and references correspond with UEFI spec version 2.7, + * errata A, available at uefi.org. + */ + +/* Error Record Header, Timestamp field (Table 251) */ +typedef struct cper_timestamp { /* BCD values */ + u8 sec; + u8 min; + u8 hour; + u8 precise; /* b[0] precise - timestamp of error, b[7:1] rsvd */ + u8 day; + u8 month; + u8 year; + u8 century; +} __packed cper_timestamp_t; + +#define CPER_TIMESTAMP_PRECISE BIT(0) + +/* Section Descriptor, Flags field (Table 253) */ +#define CPER_SEC_PRIMARY BIT(0) +#define CPER_SEC_CONTAINMENT_WARNING BIT(1) +#define CPER_SEC_RESET BIT(2) +#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED BIT(3) +#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE BIT(4) +#define CPER_SEC_LATENT_ERROR BIT(5) +#define CPER_SEC_PROPAGATED BIT(6) +#define CPER_SEC_OVERFLOW BIT(7) + +/* Section Descriptor, Section Types values (Table 253) */ +#define CPER_SEC_PROC_GENERIC_GUID \ + GUID_INIT(0x9876ccad, 0x47b4, 0x4bdb, \ + 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb) +#define CPER_SEC_PROC_IA32X64_GUID \ + GUID_INIT(0xdc3ea0b0, 0xa144, 0x4797, \ + 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d) +#define CPER_SEC_PROC_ARM_GUID \ + GUID_INIT(0xe19e3d16, 0xbc11, 0x11e4, \ + 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0) +#define CPER_SEC_PLATFORM_MEM_GUID \ + GUID_INIT(0xa5bc1114, 0x6f64, 0x4ede, \ + 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1) +#define CPER_SEC_PLATFORM_MEM2_GUID \ + GUID_INIT(0x61ec04fc, 0x48e6, 0xd813, \ + 0x25, 0xc9, 0x8d, 0xaa, 0x44, 0x75, 0x0b, 0x12) +#define CPER_SEC_PCIE_GUID \ + GUID_INIT(0xd995e954, 0xbbc1, 0x430f, \ + 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35) +#define CPER_SEC_FW_ERR_REC_REF_GUID \ + GUID_INIT(0x81212a96, 0x09ed, 0x4996, \ + 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed) +#define CPER_SEC_PCI_X_BUS_GUID \ + GUID_INIT(0xc5753963, 0x3b84, 0x4095, \ + 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd) +#define CPER_SEC_PCI_DEV_GUID \ + GUID_INIT(0xeb5e4685, 0xca66, 0x4769, \ + 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26) +#define CPER_SEC_DMAR_GENERIC_GUID \ + GUID_INIT(0x5b51fef7, 0xc79d, 0x4434, \ + 0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64) +#define CPER_SEC_DMAR_VT_GUID \ + GUID_INIT(0x71761d37, 0x32b2, 0x45cd, \ + 0xa7, 0xd0, 0xb0, 0xfe, 0xdd, 0x93, 0xe8, 0xcf) +#define CPER_SEC_DMAR_IOMMU_GUID \ + GUID_INIT(0x036f84e1, 0x7f37, 0x428c, \ + 0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec) + +/* + * Processor Generic Error Section (Table 254) + */ +typedef struct cper_proc_generic_error_section { + u64 validation; + u8 proc_type; + u8 proc_isa; + u8 error_type; + u8 operation; + u8 flags; + u8 level; + u16 reserved; + u64 cpu_version; + char cpu_brand_string[128]; + u64 proc_id; + u64 target_addr; + u64 requestor_id; + u64 responder_id; + u64 instruction_ip; +} __packed cper_proc_generic_error_section_t; + +/* Processor Generic Error Section, Validation Bits field (Table 254) */ +#define GENPROC_VALID_PROC_TYPE BIT(0) +#define GENPROC_VALID_PROC_ISA BIT(1) +#define GENPROC_VALID_PROC_ERR_TYPE BIT(2) +#define GENPROC_VALID_OPERATION BIT(3) +#define GENPROC_VALID_FLAGS BIT(4) +#define GENPROC_VALID_LEVEL BIT(5) +#define GENPROC_VALID_CPU_VERSION BIT(6) +#define GENPROC_VALID_CPU_BRAND BIT(7) +#define GENPROC_VALID_CPU_ID BIT(8) /* LAPIC ID, not CPUID */ +#define GENPROC_VALID_TGT_ADDR BIT(9) +#define GENPROC_VALID_REQR_ID BIT(10) +#define GENPROC_VALID_RSPR_ID BIT(11) +#define GENPROC_VALID_INSTR_IP BIT(12) + +/* Processor Generic Error Section, Processor Type field (Table 254) */ +#define GENPROC_PROCTYPE_IA32X64 0x0 +#define GENPROC_PROCTYPE_IA64 0x1 +#define GENPROC_PROCTYPE_ARM 0x2 + +/* Processor Generic Error Section, Processor ISA (@time of fail) (Table 254) */ +#define GENPROC_ISA_IA32 0x0 +#define GENPROC_ISA_IA64 0x1 +#define GENPROC_ISA_X64 0x2 +#define GENPROC_ISA_ARM32 0x3 +#define GENPROC_ISA_ARM64 0x4 + +/* error_type definitions */ +/* Processor Generic Error Section, Processor Error Type field (Table 254) */ +#define GENPROC_ERRTYPE_UNKNOWN 0x0 +#define GENPROC_ERRTYPE_CACHE 0x1 +#define GENPROC_ERRTYPE_TLB 0x2 +#define GENPROC_ERRTYPE_BUS 0x4 +#define GENPROC_ERRTYPE_UARCH 0x8 + +/* Processor Generic Error Section, Operation field (Table 254) */ +#define GENPROC_ERROP_UNKNOWN 0x0 +#define GENPROC_ERROP_READ 0x1 +#define GENPROC_ERROP_WRITE 0x2 +#define GENPROC_ERROP_EXECUTION 0x3 + +/* Processor Generic Error Section, Flags field (Table 254) */ +#define GENPROC_FLAG_RESTARTABLE 0x0 +#define GENPROC_FLAG_PRECISE_IP 0x1 +#define GENPROC_FLAG_OVERFLOW 0x2 +#define GENPROC_FLAG_CORRECTED 0x3 + +/* + * IA32/X64 Processor Error Section (Table 255) + */ +typedef struct cper_ia32x64_proc_error_section { + u64 validation; + u64 apicid; + u64 cpuid[6]; + /* PROC_ERR_INFO_NUM x 64-byte structures */ + /* PROC_CONTEXT_INFO_NUM x context structures */ +} __packed cper_ia32x64_proc_error_section_t; + +/* IA32/X64 Processor Error, Validation Bits field (Table 255) */ +#define I32X64SEC_VALID_LAPIC BIT(0) +#define I32X64SEC_VALID_CPUID BIT(1) +#define I32X64SEC_VALID_ERRNUM_SH 2 +#define I32X64SEC_VALID_ERRNUM_MAX 0x3f +#define I32X64SEC_VALID_ERRNUM_MASK \ + (I32X64SEC_VALID_ERRNUM_MAX \ + << I32X64SEC_VALID_ERRNUM_SH) +#define I32X64SEC_VALID_CTXNUM_SH 8 +#define I32X64SEC_VALID_CTXNUM_MAX 0x3f +#define I32X64SEC_VALID_CTXNUM_MASK \ + (I32X64SEC_VALID_CTXNUM_MAX \ + << I32X64SEC_VALID_CTXNUM_SH) + +/* IA32/X64 Processor Error Information Structure (Table 256) */ +typedef struct cper_ia32x64_proc_error_info { + guid_t type; /* cache, tlb, bus, micro-architecture specific */ + u64 validation; + u64 check_info; + u64 target_id; + u64 requestor_id; + u64 responder_id; + u64 instruction_ip; +} cper_ia32x64_proc_error_info_t; + +/* IA32/X64 Processor Error Information Structs, Err Struct Types (Table 256) */ +#define X86_PROCESSOR_CACHE_CHK_ERROR_GUID \ + GUID_INIT(0xa55701f5, 0xe3ef, 0x43de, \ + 0xac, 0x72, 0x24, 0x9b, 0x57, 0x3f, 0xad, 0x2c) +#define X86_PROCESSOR_TLB_CHK_ERROR_GUID \ + GUID_INIT(0xfc06b535, 0x5e1f, 0x4562, \ + 0x9f, 0x25, 0x0a, 0x3b, 0x9a, 0xdb, 0x63, 0xc3) +#define X86_PROCESSOR_BUS_CHK_ERROR_GUID \ + GUID_INIT(0x1cf3f8b3, 0xc5b1, 0x49a2, \ + 0xaa, 0x59, 0x5e, 0xef, 0x92, 0xff, 0xa6, 0x3c) +#define X86_PROCESSOR_MS_CHK_ERROR_GUID \ + GUID_INIT(0x48ab7f57, 0xdc34, 0x4f6c, \ + 0xa7, 0xd3, 0xb0, 0xb5, 0xb0, 0xa7, 0x43, 0x14) + +enum cper_x86_check_type { + X86_PROCESSOR_CACHE_CHK, /* X86_PROCESSOR_CACHE_CHK_ERROR_GUID */ + X86_PROCESSOR_TLB_CHK, /* X86_PROCESSOR_TLB_CHK_ERROR_GUID */ + X86_PROCESSOR_BUS_CHK, /* X86_PROCESSOR_BUS_CHK_ERROR_GUID */ + X86_PROCESSOR_MS_CHK /* X86_PROCESSOR_MS_CHK_ERROR_GUID */ +}; + +/* IA32/X64 Processor Error Information Structure, Validation Bits (Tbl 256) */ +#define I32X64ERRINFO_VALID_CHECK BIT(0) +#define I32X64ERRINFO_VALID_TGT_ADDR BIT(1) +#define I32X64ERRINFO_VALID_RQST_ID BIT(2) +#define I32X64ERRINFO_VALID_RSPD_ID BIT(3) +#define I32X64ERRINFO_VALID_IPPTR BIT(4) + +/* IA32/X64 Proc. Error Info: Cache/TLB/Check defs (Tables 257, 258, 259) */ +#define X86_PROC_CHK_XACT_TYPE_VALID BIT(0) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_OPERATION_VALID BIT(1) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_LEVEL_VALID BIT(2) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_CONTEXT_CORPT_VALID BIT(3) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_UNCORRECTED_VALID BIT(4) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_PRECISE_IP_VALID BIT(5) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_RESTARTABLE_VALID BIT(6) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_OVERFLOW_VALID BIT(7) /* CACHE|TLB|BUS */ +#define X86_PROC_CHK_PART_TYPE_VALID BIT(8) /* | |BUS */ +#define X86_PROC_CHK_TIMEOUT_VALID BIT(9) /* | |BUS */ +#define X86_PROC_CHK_ADDR_SPACE_VALID BIT(10) /* | |BUS */ +#define X86_PROC_CHK_XACT_SH 16 /* CA|TLB|BUS */ +#define X86_PROC_CHK_XACT_MASK (0x3 << X86_PROC_CHK_XACT_SH) +#define X86_PROC_CHK_XACT_INSTRUCTION (0 << X86_PROC_CHK_XACT_SH) +#define X86_PROC_CHK_XACT_DATA (1 << X86_PROC_CHK_XACT_SH) +#define X86_PROC_CHK_XACT_GENERIC (2 << X86_PROC_CHK_XACT_SH) +#define X86_PROC_CHK_OPER_SH 18 /* CA|TLB|BUS */ +#define X86_PROC_CHK_OPER_MASK (0xf << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_GENERIC (0 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_GENREAD (1 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_GENWRITE (2 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_DATAREAD (3 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_DATAWRITE (4 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_FETCH (5 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_PREFETCH (6 << X86_PROC_CHK_OPER_SH) + /* CA| | */ +#define X86_PROC_CHK_OPER_EVICTION (7 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_OPER_SNOOP (8 << X86_PROC_CHK_OPER_SH) +#define X86_PROC_CHK_LEVEL_SH 22 /* CA|TLB|BUS */ +#define X86_PROC_CHK_LEVEL_MASK (0x7 << X86_PROC_CHK_LEVEL_SH) +#define X86_PROC_CHK_LEVEL_1 (1 << X86_PROC_CHK_LEVEL_SH) +#define X86_PROC_CHK_LEVEL_2 (2 << X86_PROC_CHK_LEVEL_SH) +#define X86_PROC_CHK_LEVEL_3 (3 << X86_PROC_CHK_LEVEL_SH) +#define X86_PROC_CHK_CTX_CORRUPT (1 << 25) /* CA|TLB|BUS */ +#define X86_PROC_CHK_UNCORRECTED (1 << 26) /* CA|TLB|BUS */ +#define X86_PROC_CHK_PRECISE_IP (1 << 27) /* CA|TLB|BUS */ +#define X86_PROC_CHK_RESTARTABLE_IP (1 << 28) /* CA|TLB|BUS */ +#define X86_PROC_CHK_OVERFLOW (1 << 29) /* CA|TLB|BUS */ +#define X86_PROC_CHK_PARTIC_SH 30 /* | |BUS */ +#define X86_PROC_CHK_PARTIC_MASK (3 << X86_PROC_CHK_PARTIC_SH) +#define X86_PROC_CHK_ORIGINATED (0 << X86_PROC_CHK_PARTIC_SH) +#define X86_PROC_CHK_RESPONDED (1 << X86_PROC_CHK_PARTIC_SH) +#define X86_PROC_CHK_OBSERVED (2 << X86_PROC_CHK_PARTIC_SH) +#define X86_PROC_CHK_TIMEOUT 0x100000000 /* BIT(32) */ +#define X86_PROC_CHK_SPACE_SH 33 /* | |BUS */ +#define X86_PROC_CHK_SPACE_MASK (0x3 << X86_PROC_CHK_SPACE_SH) +#define X86_PROC_CHK_SPACE_MEM (0 << X86_PROC_CHK_SPACE_SH) +#define X86_PROC_CHK_SPACE_IO (2 << X86_PROC_CHK_SPACE_SH) +#define X86_PROC_CHK_SPACE_OTHER (3 << X86_PROC_CHK_SPACE_SH) +/* MS check defines & aligns (Table 260 */ +#define X86_PROC_MS_ERROR_TYPE_VALID BIT(0) +#define X86_PROC_MS_CONTEXT_CORPT_VALID BIT(1) +#define X86_PROC_MS_UNCORRECTED_VALID BIT(2) +#define X86_PROC_MS_PRECISE_IP_VALID BIT(3) +#define X86_PROC_MS_RESTARTABLE_IP_VALID BIT(4) +#define X86_PROC_MS_OVERFLOW_VALID BIT(5) +#define X86_PROC_MS_CHK_XACT_SH 16 +#define X86_PROC_MS_CHK_XACT_MASK (0x7 << X86_PROC_MS_CHK_XACT_SH) +#define X86_PROC_MS_CHK_XACT_TYPE_NOERR (0 << X86_PROC_MS_CHK_XACT_SH) +#define X86_PROC_MS_CHK_XACT_TYPE_UNCL (1 << X86_PROC_MS_CHK_XACT_SH) +#define X86_PROC_MS_CHK_XACT_TYPE_UCODE_ROM (2 << X86_PROC_MS_CHK_XACT_SH) +#define X86_PROC_MS_CHK_XACT_TYPE_EXT (3 << X86_PROC_MS_CHK_XACT_SH) +#define X86_PROC_MS_CHK_XACT_TYPE_FRC (4 << X86_PROC_MS_CHK_XACT_SH) +#define X86_PROC_MS_CHK_XACT_TYPE_INT_UNCL (5 << X86_PROC_MS_CHK_XACT_SH) +#define X86_PROC_MS_CHK_CTX_CORRUPT (1 << 19) +#define X86_PROC_MS_CHK_UNCORRECTED (1 << 20) +#define X86_PROC_MS_CHK_PRECISE_IP (1 << 21) +#define X86_PROC_MS_CHK_RESTARTABLE_IP (1 << 22) +#define X86_PROC_MS_CHK_OVERFLOW (1 << 23) + +/* IA32/X64 Processor Context Information (Table 261) */ +typedef struct cper_ia32x64_context { + u16 type; + u16 array_size; + u32 msr_addr; + u64 mmap_addr; + /* N bytes of register array */ +} cper_ia32x64_context_t; + +/* IA32/X64 Processor Context Information, Types field (Table 261) */ +#define CPER_IA32X64_CTX_UNCL 0 +#define CPER_IA32X64_CTX_MSR 1 +#define CPER_IA32X64_CTX_32BIT_EX 2 +#define CPER_IA32X64_CTX_64BIT_EX 3 +#define CPER_IA32X64_CTX_FXSAVE 4 +#define CPER_IA32X64_CTX_32BIT_DBG 5 +#define CPER_IA32X64_CTX_64BIT_DBG 6 +#define CPER_IA32X64_CTX_MEMMAPPED 7 + +/* IA32/X64 Processor Context IA32 Register State (Table 262) */ +typedef struct cper_ia32x64_ctx_ia32state { + u32 eax; + u32 ebx; + u32 ecx; + u32 edx; + u32 esi; + u32 edi; + u32 ebp; + u32 esp; + u16 cs; + u16 ds; + u16 ss; + u16 es; + u16 fs; + u16 gs; + u32 eflags; + u32 eip; + u32 cr0; + u32 cr1; + u32 cr2; + u32 cr3; + u32 cr4; + u64 gdtr; + u64 idtr; + u16 ldtr; + u16 tr; +} cper_ia32x64_ctx_ia32state_t; + +/* IA32/X64 Processor Context X64 Register state (Table 263) */ +typedef struct cper_ia32x64_ctx_x64state { + u64 rax; + u64 rbx; + u64 rcx; + u64 rdx; + u64 rsi; + u64 rdi; + u64 rbp; + u64 rsp; + u64 r8; + u64 r9; + u64 r10; + u64 r11; + u64 r12; + u64 r13; + u64 r14; + u64 r15; + u16 cs; + u16 ds; + u16 ss; + u16 es; + u16 fs; + u16 gs; + u32 reserved; + u64 rflags; + u64 eip; + u64 cr0; + u64 cr1; + u64 cr2; + u64 cr3; + u64 cr4; + u64 cr8; + u8 gdtr[16]; + u8 idtr[16]; + u16 ldtr; + u16 tr; +} cper_ia32x64_ctx_x64state_t; + +static inline cper_timestamp_t cper_timestamp(int precise) +{ + cper_timestamp_t ts; +#if IS_ENABLED(CONFIG_RTC) + struct rtc_time time; + + rtc_get(&time); + ts.sec = bin2bcd(time.sec); + ts.min = bin2bcd(time.min); + ts.hour = bin2bcd(time.hour); + ts.day = bin2bcd(time.mday); + ts.month = bin2bcd(time.mon); + ts.year = bin2bcd(time.year % 100); + ts.century = 0x20; + ts.precise = precise; +#else + ts.sec = 0; + ts.min = 0; + ts.hour = 0; + ts.day = 0; + ts.month = 0; + ts.year = 0; + ts.century = 0; + ts.precise = 0; +#endif + return ts; +} + +/* Calculate the size of an IA32/X64 context by its type. Some types have a + * predetermined size, and others are variable size. All sizes are rounded up + * to the nearest multiple of 16 bytes (See Processor Context field of + * Table 255). + * + * type is one of: + * CPER_IA32X64_CTX_UNCL + * CPER_IA32X64_CTX_MSR + * CPER_IA32X64_CTX_32BIT_EX + * CPER_IA32X64_CTX_64BIT_EX + * CPER_IA32X64_CTX_FXSAVE + * CPER_IA32X64_CTX_32BIT_DBG + * CPER_IA32X64_CTX_64BIT_DBG + * CPER_IA32X64_CTX_MEMMAPPED + * num is the number of items in the context's register array + */ +static inline size_t cper_ia32x64_ctx_sz_bytype(int type, int arr_num) +{ + size_t sz = sizeof(cper_ia32x64_context_t); + + switch (type) { + case CPER_IA32X64_CTX_32BIT_EX: + return ALIGN_UP(sz + sizeof(cper_ia32x64_ctx_ia32state_t), 16); + case CPER_IA32X64_CTX_64BIT_EX: + return ALIGN_UP(sz + sizeof(cper_ia32x64_ctx_x64state_t), 16); + case CPER_IA32X64_CTX_UNCL: + case CPER_IA32X64_CTX_MSR: + case CPER_IA32X64_CTX_FXSAVE: + case CPER_IA32X64_CTX_32BIT_DBG: + case CPER_IA32X64_CTX_64BIT_DBG: + case CPER_IA32X64_CTX_MEMMAPPED: + default: + /* Table 261: "size ... is determined by (Array Size / 8)" */ + return ALIGN_UP(sz + arr_num * 8, 16); + } +} + +static inline size_t cper_ia32x64_check_sz(void) +{ + return sizeof(cper_ia32x64_proc_error_info_t); /* all the same size */ +} + +/* Return PROC_ERR_INFO_NUM for an IA32/X64 Processor Error Record */ +static inline int cper_ia32x64_proc_num_chks( + cper_ia32x64_proc_error_section_t *x86err) +{ + int mask; + int shift; + + mask = I32X64SEC_VALID_ERRNUM_MASK; + shift = I32X64SEC_VALID_ERRNUM_SH; + + return (x86err->validation & mask) >> shift; +} + +/* Return PROC_CONTEXT_INFO_NUM for an IA32/X64 Processor Error Record */ +static inline int cper_ia32x64_proc_num_ctxs( + cper_ia32x64_proc_error_section_t *x86err) +{ + int mask; + int shift; + + mask = I32X64SEC_VALID_CTXNUM_MASK; + shift = I32X64SEC_VALID_CTXNUM_SH; + + return (x86err->validation & mask) >> shift; +} + +/* Do PROC_ERR_INFO_NUM++ of an IA32/X64 error section. Caller should ensure + * the max is not being exceeded. + */ +static inline void cper_bump_ia32x64_chk_count( + cper_ia32x64_proc_error_section_t *x86err) +{ + int count; + + count = cper_ia32x64_proc_num_chks(x86err) + 1; + x86err->validation &= ~I32X64SEC_VALID_ERRNUM_MASK; + x86err->validation |= count << I32X64SEC_VALID_ERRNUM_SH; +} + +/* Do PROC_CONTEXT_INFO_NUM++ of an IA32/X64 error section. Caller should + * ensure the max is not being exceeded. + */ +static inline void cper_bump_ia32x64_ctx_count( + cper_ia32x64_proc_error_section_t *x86err) +{ + int count; + + count = cper_ia32x64_proc_num_ctxs(x86err) + 1; + x86err->validation &= ~I32X64SEC_VALID_CTXNUM_MASK; + x86err->validation |= count << I32X64SEC_VALID_CTXNUM_SH; +} + +#endif /* _CPER_H_ */ -- To view, visit https://review.coreboot.org/28468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Gerrit-Change-Number: 28468 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: x86/acpi: Add APEI definitions
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28469 Change subject: x86/acpi: Add APEI definitions ...................................................................... x86/acpi: Add APEI definitions Add ACPI Platform Error Interfaces definitions that will be used for building a BERT table region in a subsequent patch. Two tables are defined: the Generic Error Status Block, Generic Error Data Entry. For reference, see the ACPI specification 6.2-A tables 381 and 382. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28469/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 52245ee..cf223e5 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -58,6 +58,8 @@ #include <rules.h> #include <commonlib/helpers.h> #include <device/device.h> +#include <uuid.h> +#include <cper.h> #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ @@ -642,6 +644,66 @@ u32 error_threshold_win; } __packed acpi_hest_hen_t; +/* Generic Error Data Entry. */ +typedef struct acpi_hest_generic_data { + guid_t section_type; + u32 error_severity; + u16 revision; + u8 validation_bits; + u8 flags; + u32 data_length; + guid_t fru_id; + u8 fru_text[20]; + /* error data */ +} __packed acpi_hest_generic_data_t; + +/* Generic Error Data Entry (see Table 18-382) */ +typedef struct acpi_hest_generic_data_v300 { + guid_t section_type; + u32 error_severity; + u16 revision; + u8 validation_bits; + u8 flags; /* see CPER Section Descriptor, Flags field */ + u32 data_length; + guid_t fru_id; + u8 fru_text[20]; + cper_timestamp_t timestamp; + /* error data */ +} __packed acpi_hest_generic_data_v300_t; +#define HEST_GENERIC_ENTRY_V300 0x300 + +/* Both Generic Error Status & Generic Error Data Entry, Error Severity field */ +#define ACPI_GENERROR_SEV_RECOVERABLE 0 +#define ACPI_GENERROR_SEV_FATAL 1 +#define ACPI_GENERROR_SEV_CORRECTED 2 +#define ACPI_GENERROR_SEV_NONE 3 + +/* Generic Error Data Entry, Validation Bits field */ +#define ACPI_GENERROR_VALID_FRUID BIT(0) +#define ACPI_GENERROR_VALID_FRUID_TEXT BIT(1) +#define ACPI_GENERROR_VALID_TIMESTAMP BIT(2) + +/* Generic Error Status Block */ +typedef struct acpi_generic_error_status { + u32 block_status; + u32 raw_data_offset; /* must follow any generic entries */ + u32 raw_data_length; + u32 data_length; /* generic data */ + u32 error_severity; + /* zero or more Generic Error Data Entries */ +} __packed acpi_generic_error_status_t; + +/* Generic Status Block, Block Status values */ +#define GENERIC_ERR_STS_UNCORRECTABLE_VALID BIT(0) +#define GENERIC_ERR_STS_CORRECTABLE_VALID BIT(1) +#define GENERIC_ERR_STS_MULT_UNCORRECTABLE BIT(2) +#define GENERIC_ERR_STS_MULT_CORRECTABLE BIT(3) +#define GENERIC_ERR_STS_ENTRY_COUNT_SHIFT 4 +#define GENERIC_ERR_STS_ENTRY_COUNT_MAX 0x3ff +#define GENERIC_ERR_STS_ENTRY_COUNT_MASK \ + (GENERIC_ERR_STS_ENTRY_COUNT_MAX \ + << GENERIC_ERR_STS_ENTRY_COUNT_SHIFT) + typedef struct acpi_cstate { u8 ctype; u16 latency; -- To view, visit https://review.coreboot.org/28469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Gerrit-Change-Number: 28469 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: arch/x86: Add BERT region support functions
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28470 Change subject: arch/x86: Add BERT region support functions ...................................................................... arch/x86: Add BERT region support functions Add code for generating the region pointed to in an ACPI Boot Error Record Table. The BERT region must be reported as Reserved to the OSPM, so this code calls out to a system-specific region locator. cbmem is reported as type 16 and is not usable for the BERT region. Events reported via BERT are Generic Error Data, and are constructed as follows (see ACPI and UEFI specs for reference): * Each event begins with a Generic Error Status Block, which may contain zero or more Generic Data Entries * Each Generic Data Entry is identifiable by its Section Type field, and the data structures associated are also in the UEFI spec. * The GUIDs are listed in the Section Type field of the CPER Section Descriptor structure. BERT doesn't use this structure but simply uses its GUIDs. * Data structures used in the Generic Data Entry are named as Error Sections in the UEFI spec. * Some sections may optionally include a variable number of additional structures, e.g. an IA32/X64 processor error can report error information as well as machine contexts. It is worth noting that the Linux kernel (as of v4.4) does not attempt to parse IA32/X64 sections, and opts to hexdump them instead. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/Kconfig M src/arch/x86/Makefile.inc A src/arch/x86/acpi_bert_storage.c A src/arch/x86/include/arch/bert_storage.h 4 files changed, 716 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28470/1 diff --git a/src/Kconfig b/src/Kconfig index bce3e32..ca75c0b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -586,6 +586,12 @@ help Build support for NHLT (non HD Audio) ACPI table generation. +config ACPI_BERT + bool + depends on HAVE_ACPI_TABLES + help + Build an ACPI Boot Error Record Table. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1d9ee4d..3c4bc1f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -291,6 +291,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c ramstage-y += c_start.S ramstage-y += cbmem.c diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c new file mode 100644 index 0000000..826c14c --- /dev/null +++ b/src/arch/x86/acpi_bert_storage.c @@ -0,0 +1,542 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/name.h> /* todo: support on other architectures */ +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <arch/bert_storage.h> +#include <string.h> + +/* BERT region management: Allow the chipset to determine the specific + * location of the BERT region. We find that base and size, then manage + * the allocation of error information within it. + * + * Use simple static variables for managing the BERT region. This is a thin + * implementation; it is only created and consumed by coreboot, and only in + * a single stage, and we don't want its information to survive reboot or + * resume cycles. If the requirements change, consider using IMD to help + * manage the space. + */ +static int bert_region_broken; +static void *bert_region_base; +static size_t bert_region_size; +static size_t bert_region_used; + +/* Calculate the remaining space in the BERT region. This knowledge may help + * the caller prioritize the information to store. + */ +size_t bert_storage_remaining(void) +{ + return bert_region_broken ? 0 : bert_region_size - bert_region_used; +} + +int bert_errors_present(void) +{ + return bert_region_broken ? 0 : !!bert_region_used; +} + +void bert_errors_region(void **start, size_t *size) +{ + if (bert_region_broken) { + *start = NULL; + *size = 0; + return; + } + + /* No metadata, etc. with our region, so this is easy */ + *start = bert_region_base; + *size = bert_region_used; +} + +static void *bert_allocate_storage(size_t size) +{ + size_t alloc; + + if (bert_region_broken) + return NULL; + if (bert_region_used + size > bert_region_size) + return NULL; + + alloc = bert_region_used; + bert_region_used += size; + + return (void *)((u8 *)bert_region_base + alloc); +} + +/* Generic Error Status: Each Status represents a unique error event within + * the BERT errors region. Each event may have multiple errors associated + * with it. + */ + +/* Update data_length for this Error Status, and final Data Entry it contains */ +static void revise_error_sizes(acpi_generic_error_status_t *status, size_t size) +{ + acpi_hest_generic_data_v300_t *entry; + int entries; + + if (!status) + return; + + entries = bert_entry_count(status); + entry = acpi_hest_generic_data_nth(status, entries); + status->data_length += size; + if (entry) + entry->data_length += size; +} + +/* Create space for a new BERT Generic Error Status Block, by finding the next + * available slot and moving the ending location. There is nothing to designate + * this as another Generic Error Status Block (e.g. no signature); only that it + * is within the BERT region. + * + * It is up to the caller to correctly fill the information, including status + * and error severity, and to update/maintain data offsets and lengths as + * entries are added. + */ +static acpi_generic_error_status_t *new_bert_status(void) +{ + acpi_generic_error_status_t *status; + + status = bert_allocate_storage(sizeof(*status)); + + if (!status) { + printk(BIOS_ERR, "Error: New BERT error entry would exceed available region\n"); + return NULL; + } + + status->error_severity = ACPI_GENERROR_SEV_NONE; + return status; +} + +/* Generic Error Data: Each Generic Error Status may contain zero or more + * Generic Error Data structures. The data structures describe particular + * error(s) associated with an event. The definition for the structure is + * found in the ACPI spec, however the data types and any accompanying data + * definitions are in the Common Platform Error Record appendix of the UEFI + * spec. + */ + +/* Create space for a new BERT Generic Data Entry. Update the count and + * data length in the parent Generic Error Status Block. Version 0x300 of + * the structure is used, and the timestamp is filled and marked precise + * (i.e. assumed close enough for reporting). + * + * It is up to the caller to fill the Section Type field and add the Common + * Platform Error Record type data as appropriate. In addition, the caller + * should update the error severity, and may optionally add FRU information + * or override any existing information. + */ +static acpi_hest_generic_data_v300_t *new_generic_error_entry( + acpi_generic_error_status_t *status) +{ + acpi_hest_generic_data_v300_t *entry; + + if (bert_entry_count(status) == GENERIC_ERR_STS_ENTRY_COUNT_MAX) { + printk(BIOS_ERR, "Error: New BERT error would exceed maximum entries\n"); + return NULL; + } + + entry = bert_allocate_storage(sizeof(*entry)); + if (!entry) { + printk(BIOS_ERR, "Error: New BERT error entry would exceed available region\n"); + return NULL; + } + + entry->revision = HEST_GENERIC_ENTRY_V300; + + entry->timestamp = cper_timestamp(CPER_TIMESTAMP_PRECISE); + entry->validation_bits |= ACPI_GENERROR_VALID_TIMESTAMP; + + status->data_length += sizeof(*entry); + bert_bump_entry_count(status); + + return entry; +} + +/* Find the size of a CPER error section w/o any add-ons */ +static size_t sizeof_error_section(guid_t *guid) +{ + if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) + return sizeof(cper_proc_generic_error_section_t); + else if (!guidcmp(guid, &CPER_SEC_PROC_IA32X64_GUID)) + return sizeof(cper_ia32x64_proc_error_section_t); + /* else if ... sizeof(structures not yet defined) */ + + printk(BIOS_ERR, "Error: requested size of unrecognized CPER GUID\n"); + return 0; +} + +/* Append a new ACPI Generic Error Data Entry plus CPER Error Section to an + * existing ACPI Generic Error Status Block. The caller is responsible for + * the setting the status and entry severity, as well as populating all fields + * of the error section. + */ +acpi_hest_generic_data_v300_t *bert_append_error_datasection( + acpi_generic_error_status_t *status, guid_t *guid) +{ + acpi_hest_generic_data_v300_t *entry; + void *sect; + size_t sect_size; + + sect_size = sizeof_error_section(guid); + if (!sect_size) + return NULL; /* Don't allocate structure if bad GUID passed */ + + if (sizeof(*entry) + sect_size > bert_storage_remaining()) + return NULL; + + entry = new_generic_error_entry(status); + if (!entry) + return NULL; + + /* error section immediately follows the Generic Error Data Entry */ + sect = bert_allocate_storage(sect_size); + if (!sect) + return NULL; + + revise_error_sizes(status, sect_size); + + guidcpy(&entry->section_type, guid); + return entry; +} + +/* Helper to append an ACPI Generic Error Data Entry plus a CPER Processor + * Generic Error Section. As many fields are populated as possible for the + * caller. + */ +acpi_hest_generic_data_v300_t *bert_append_genproc( + acpi_generic_error_status_t *status) +{ + acpi_hest_generic_data_v300_t *entry; + cper_proc_generic_error_section_t *ges; + + entry = bert_append_error_datasection(status, + &CPER_SEC_PROC_GENERIC_GUID); + if (!entry) + return NULL; + + status->block_status |= GENERIC_ERR_STS_UNCORRECTABLE_VALID; + status->error_severity = ACPI_GENERROR_SEV_FATAL; + + entry->error_severity = ACPI_GENERROR_SEV_FATAL; + + ges = section_of_acpientry(ges, entry); + + ges->proc_type = GENPROC_PROCTYPE_IA32X64; + ges->validation |= GENPROC_VALID_PROC_TYPE; + + ges->cpu_version = cpuid_eax(1); + ges->validation |= GENPROC_VALID_CPU_VERSION; + + fill_processor_name(ges->cpu_brand_string); + ges->validation |= GENPROC_VALID_CPU_BRAND; + + ges->proc_id = lapicid(); + ges->validation |= GENPROC_VALID_CPU_ID; + + return entry; +} + +/* Add a new IA32/X64 Processor Context Structure (Table 261), following any + * other contexts, to an existing Processor Error Section (Table 255). Contexts + * may only be added after the entire Processor Error Info array has been + * created. + * + * This function fills only the minimal amount of information required to parse + * or step through the contexts. The type is filled and PROC_CONTEXT_INFO_NUM + * is updated. + * + * type is one of: + * CPER_IA32X64_CTX_UNCL + * CPER_IA32X64_CTX_MSR + * CPER_IA32X64_CTX_32BIT_EX + * CPER_IA32X64_CTX_64BIT_EX + * CPER_IA32X64_CTX_FXSAVE + * CPER_IA32X64_CTX_32BIT_DBG + * CPER_IA32X64_CTX_64BIT_DBG + * CPER_IA32X64_CTX_MEMMAPPED + * num is the number of bytes eventually used to fill the context's register + * array, e.g. 4 MSRs * sizeof(msr_t) + * + * status and entry data_length values are updated. + */ +cper_ia32x64_context_t *new_cper_ia32x64_ctx( + acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, int type, int num) +{ + size_t size; + cper_ia32x64_context_t *ctx; + static const char * const ctx_names[] = { + "Unclassified Data", + "MSR Registers", + "32-bit Mode Execution", + "64-bit Mode Execution", + "FXSAVE" + "32-bit Mode Debug" + "64-bit Mode Debug" + "Memory Mapped" + }; + + if (type > CPER_IA32X64_CTX_MEMMAPPED) + return NULL; + + if (cper_ia32x64_proc_num_ctxs(x86err) == I32X64SEC_VALID_CTXNUM_MAX) { + printk(BIOS_ERR, "Error: New IA32X64 %s context entry would exceed max allowable contexts\n", + ctx_names[type]); + return NULL; + } + + size = cper_ia32x64_ctx_sz_bytype(type, num); + ctx = bert_allocate_storage(size); + if (!ctx) { + printk(BIOS_ERR, "Error: New IA32X64 %s context entry would exceed available region\n", + ctx_names[type]); + return NULL; + } + + revise_error_sizes(status, size); + + ctx->type = type; + ctx->array_size = num; + cper_bump_ia32x64_ctx_count(x86err); + + return ctx; +} + +/* Add a new IA32/X64 Processor Error Information Structure (Table 256), + * following any other errors, to an existing Processor Error Section + * (Table 255). All error structures must be added before any contexts are + * added. + * + * This function fills only the minimal amount of information required to parse + * or step through the errors. The type is filled and PROC_ERR_INFO_NUM is + * updated. + */ +cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check( + acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, + enum cper_x86_check_type type) +{ + cper_ia32x64_proc_error_info_t *check; + static const char * const check_names[] = { + "cache", + "TLB", + "bus", + "MS" + }; + const guid_t check_guids[] = { + X86_PROCESSOR_CACHE_CHK_ERROR_GUID, + X86_PROCESSOR_TLB_CHK_ERROR_GUID, + X86_PROCESSOR_BUS_CHK_ERROR_GUID, + X86_PROCESSOR_MS_CHK_ERROR_GUID + }; + + if (type > 3) + return NULL; + + if (cper_ia32x64_proc_num_chks(x86err) == I32X64SEC_VALID_ERRNUM_MAX) { + printk(BIOS_ERR, "Error: New IA32X64 %s check entry would exceed max allowable errors\n", + check_names[type]); + return NULL; + } + + check = bert_allocate_storage(sizeof(*check)); + if (!check) { + printk(BIOS_ERR, "Error: New IA32X64 %s check entry would exceed available region\n", + check_names[type]); + return NULL; + } + + revise_error_sizes(status, sizeof(*check)); + + guidcpy(&check->type, &check_guids[type]); + cper_bump_ia32x64_chk_count(x86err); + + return check; +} + +/* Helper to append an ACPI Generic Error Data Entry plus a CPER IA32/X64 + * Processor Error Section. As many fields are populated as possible for the + * caller. + */ +acpi_hest_generic_data_v300_t *bert_append_ia32x64( + acpi_generic_error_status_t *status) +{ + acpi_hest_generic_data_v300_t *entry; + cper_ia32x64_proc_error_section_t *ipe; + + entry = bert_append_error_datasection(status, + &CPER_SEC_PROC_IA32X64_GUID); + if (!entry) + return NULL; + + status->block_status |= GENERIC_ERR_STS_UNCORRECTABLE_VALID; + status->error_severity = ACPI_GENERROR_SEV_FATAL; + + entry->error_severity = ACPI_GENERROR_SEV_FATAL; + + ipe = section_of_acpientry(ipe, entry); + + ipe->apicid = lapicid(); + ipe->validation |= I32X64SEC_VALID_LAPIC; + + ipe->cpuid[0] = cpuid_eax(1); + ipe->cpuid[1] = cpuid_ebx(1); + ipe->cpuid[2] = cpuid_ecx(1); + ipe->cpuid[3] = cpuid_edx(1); + ipe->validation |= I32X64SEC_VALID_CPUID; + + return entry; +} + +static const char * const generic_error_types[] = { + "PROCESSOR_GENERIC", + "PROCESSOR_SPECIFIC_X86", + "PROCESSOR_SPECIFIC_ARM", + "PLATFORM_MEMORY", + "PLATFORM_MEMORY2", + "PCIE", + "FW_ERROR_RECORD", + "PCI_PCIX_BUS", + "PCI_DEVICE", + "DMAR_GENERIC", + "DIRECTED_IO_DMAR", + "IOMMU_DMAR", + "UNRECOGNIZED" +}; + +static const char *generic_error_name(guid_t *guid) +{ + if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) + return generic_error_types[0]; + if (!guidcmp(guid, &CPER_SEC_PROC_IA32X64_GUID)) + return generic_error_types[1]; + if (!guidcmp(guid, &CPER_SEC_PROC_ARM_GUID)) + return generic_error_types[2]; + if (!guidcmp(guid, &CPER_SEC_PLATFORM_MEM_GUID)) + return generic_error_types[3]; + if (!guidcmp(guid, &CPER_SEC_PLATFORM_MEM2_GUID)) + return generic_error_types[4]; + if (!guidcmp(guid, &CPER_SEC_PCIE_GUID)) + return generic_error_types[5]; + if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) + return generic_error_types[6]; + if (!guidcmp(guid, &CPER_SEC_PCI_X_BUS_GUID)) + return generic_error_types[7]; + if (!guidcmp(guid, &CPER_SEC_PCI_DEV_GUID)) + return generic_error_types[8]; + if (!guidcmp(guid, &CPER_SEC_DMAR_GENERIC_GUID)) + return generic_error_types[9]; + if (!guidcmp(guid, &CPER_SEC_DMAR_VT_GUID)) + return generic_error_types[10]; + if (!guidcmp(guid, &CPER_SEC_DMAR_IOMMU_GUID)) + return generic_error_types[11]; + return generic_error_types[12]; +} + +/* Add a new event to the BERT region. An event consists of an ACPI Error + * Status Block, a Generic Error Data Entry, and an associated CPER Error + * Section. + */ +acpi_generic_error_status_t *bert_new_event(guid_t *guid) +{ + size_t size; + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *entry, *r; + + size = sizeof(*status); + size += sizeof(*entry); + size += sizeof_error_section(guid); + + if (size > bert_storage_remaining()) { + printk(BIOS_ERR, "Error: Not enough BERT region space to add event for type %s\n", + generic_error_name(guid)); + return NULL; + } + + status = new_bert_status(); + if (!status) + return NULL; + + if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) + r = bert_append_genproc(status); + else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) + r = bert_append_ia32x64(status); + /* else if other types not implemented */ + else + r = NULL; + + if (r) + return status; + return NULL; +} + +/* Helper to add an MSR context to an existing IA32/X64-type error entry */ +cper_ia32x64_context_t *cper_new_ia32x64_context_msr( + acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, u32 addr, int num) +{ + cper_ia32x64_context_t *ctx; + int i; + msr_t *dest; + + ctx = new_cper_ia32x64_ctx(status, x86err, CPER_IA32X64_CTX_MSR, num); + if (!ctx) + return NULL; + + /* already filled ctx->type = CPER_IA32X64_CTX_MSR; */ + ctx->msr_addr = addr; + ctx->array_size = num * sizeof(msr_t); + + dest = (msr_t *)((u8 *)(ctx + 1)); /* point to the Register Array */ + + for (i = 0 ; i < num ; i++) + *(dest + i) = rdmsr(addr + i); + return ctx; +} + +/* The region must be in memory marked as reserved. If not implemented, + * skip generating the information in the region. + */ +__weak void bert_reserved_region(void **start, size_t *size) +{ + *start = NULL; + *size = 0; +} + +static void bert_storage_setup(int unused) +{ + /* Always start with a blank bert region. Make sure nothing is + * maintained across reboots or resumes. + */ + bert_region_broken = 0; + bert_region_used = 0; + + bert_reserved_region(&bert_region_base, &bert_region_size); + + if (!bert_region_base || !bert_region_size) { + printk(BIOS_ERR, "Bug: Can't find/add BERT storage area\n"); + bert_region_broken = 1; + return; + } + + memset(bert_region_base, 0, bert_region_size); +} + +RAMSTAGE_CBMEM_INIT_HOOK(bert_storage_setup) diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h new file mode 100644 index 0000000..9d5b2da --- /dev/null +++ b/src/arch/x86/include/arch/bert_storage.h @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BERT_STORAGE_H_ +#define _BERT_STORAGE_H_ + +#include <stdint.h> +#include <arch/acpi.h> + +/* Items in the BERT region + * + * * Each item begins with a Generic Error Status Block + * * Zero or more Generic Error Data Entries follow, and + * are associated with the Status Block + * * Each Generic Error Data Entry must be a certain type, + * as defined in the UEFI CPER appendix + * * Each type may allow zero or more additional sets of + * data, e.g. error descriptions, or processor contexts. + * + * In the example layout below, there are three BERT region + * entries. The first two are a single error. The third + * has two errors, with one providing a variable amount + * of additional information. + * + * +====================================================================+ + * | Generic Error | Generic Error | Platform Memory Error | + * | Status | Data Entry | | + * |====================================================================| + * | Generic Error | Generic Error | Generic Processor Error | + * | Status | Data Entry | | + * |====================================================================| + * | Generic Error | Generic Error | IA32/X64 Processor Error | + * | Status | Data Entry | +----------------------------+ + * | | | | Error Check Data | + * | | | +----------------------------+ + * | | | | MSR Context | + * | | | +----------------------------+ + * | | | | X64 Registers Context | + * | +-----------------+----+----------------------------+ + * | | Generic Error | PCI Express Error | + * | | Data Entry | | + * +--------------------------------------------------------------------+ + */ + +/* Get implementation-specific reserved area for generating BERT info */ +void bert_reserved_region(void **start, size_t *size); + +/* Get the region where BERT error structures have been constructed for + * generating the ACPI table + */ +void bert_errors_region(void **start, size_t *size); + +/* Get amount of available storage left for error info */ +size_t bert_storage_remaining(void); +/* Find if errors were added, a BERT region is present, and ACPI table needed */ +int bert_errors_present(void); + +/* Get the number of entries accociated with status */ +static inline size_t bert_entry_count(acpi_generic_error_status_t *status) +{ + return (status->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) + >> GENERIC_ERR_STS_ENTRY_COUNT_SHIFT; +} + +/* Increment the number of entries this status describes */ +static inline void bert_bump_entry_count(acpi_generic_error_status_t *status) +{ + int count; + + count = bert_entry_count(status) + 1; + status->block_status &= ~GENERIC_ERR_STS_ENTRY_COUNT_MASK; + status->block_status |= count << GENERIC_ERR_STS_ENTRY_COUNT_SHIFT; +} + +/* Find the nth (1-based) Generic Data Structure attached to an Error Status */ +static inline void *acpi_hest_generic_data_nth( + acpi_generic_error_status_t *status, int num) +{ + acpi_hest_generic_data_v300_t *ptr; + size_t struct_size; + + if (!num || num > bert_entry_count(status)) + return NULL; + + ptr = (acpi_hest_generic_data_v300_t *)(status + 1); + while (--num) { + if (ptr->revision == HEST_GENERIC_ENTRY_V300) + struct_size = sizeof(acpi_hest_generic_data_v300_t); + else + struct_size = sizeof(acpi_hest_generic_data_t); + ptr = (acpi_hest_generic_data_v300_t *)( + (u8 *)ptr + + ptr->data_length + + struct_size); + } + return ptr; +} + +/* Find the address of the first Generic Data structure from its status entry */ +static inline acpi_hest_generic_data_v300_t *acpi_hest_generic_data3( + acpi_generic_error_status_t *status) +{ + return (acpi_hest_generic_data_v300_t *) + ((u8 *)status + sizeof(*status)); +} + +/* Find the address of a Generic Data structure's CPER error record section */ +#define section_of_acpientry(A, B) ((typeof(A))((u8 *)(B) + sizeof(*(B)))) + + +/* Add a context to an existing IA32/X64-type error entry */ +cper_ia32x64_context_t *new_cper_ia32x64_ctx( + acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, int type, int num); + +/* Helper to add an MSR context to an existing IA32/X64-type error entry */ +cper_ia32x64_context_t *cper_new_ia32x64_context_msr( + acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, u32 addr, int num); + +/* Add check info to an existing IA32/X64-type error entry */ +cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check( + acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, + enum cper_x86_check_type type); + +/* Append a new ACPI Generic Error Data Entry plus CPER Error Section to an + * existing ACPI Generic Error Status Block. The caller is responsible for + * the setting the status and entry severity, as well as populating all fields + * of the error section. + */ +acpi_hest_generic_data_v300_t *bert_append_error_datasection( + acpi_generic_error_status_t *status, guid_t *guid); + +/* Helper to append an ACPI Generic Error Data Entry plus a CPER Processor + * Generic Error Section. As many fields are populated as possible for the + * caller. + */ +acpi_hest_generic_data_v300_t *bert_append_genproc( + acpi_generic_error_status_t *status); + +/* Helper to append an ACPI Generic Error Data Entry plus a CPER IA32/X64 + * Processor Error Section. As many fields are populated as possible for the + * caller. + */ +acpi_hest_generic_data_v300_t *bert_append_ia32x64( + acpi_generic_error_status_t *status); + +/* Add a new event to the BERT region. An event consists of an ACPI Error + * Status Block, a Generic Error Data Entry, and an associated CPER Error + * Section. + */ +acpi_generic_error_status_t *bert_new_event(guid_t *guid); + +#endif /* _BERT_STORAGE_H_ */ -- To view, visit https://review.coreboot.org/28470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9 Gerrit-Change-Number: 28470 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: src/include: Introduce guid_t type
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28467 Change subject: src/include: Introduce guid_t type ...................................................................... src/include: Introduce guid_t type Duplicate the guid_t and GUID_INIT framework from the Linux driver. Adapt it for coreboot, and create supporting copy and compare functions. Change-Id: Ia1cd7a1f0e0f900858830e1a6a7e2bbbe272fa30 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/include/uuid.h 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28467/1 diff --git a/src/include/uuid.h b/src/include/uuid.h new file mode 100644 index 0000000..0209055 --- /dev/null +++ b/src/include/uuid.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010, Intel Corp. Huang Ying <ying.huang(a)intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _UUID_H_ +#define _UUID_H_ + +#include <string.h> + +typedef struct { + uint8_t b[16]; +} __packed guid_t; + +#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ +((guid_t) \ +{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }) + +static inline int guidcmp(const guid_t *guid1, const guid_t *guid2) +{ + return memcmp(guid1, guid2, sizeof(guid_t)); +} + +static inline guid_t *guidcpy(guid_t *dest, const guid_t *src) +{ + return (guid_t *)memcpy(dest, src, sizeof(guid_t)); +} + +#endif /* _UUID_H_ */ -- To view, visit https://review.coreboot.org/28467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia1cd7a1f0e0f900858830e1a6a7e2bbbe272fa30 Gerrit-Change-Number: 28467 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
by Furquan Shaikh (Code Review) 04 Sep '18

04 Sep '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28424 ) Change subject: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Gerrit-Change-Number: 28424 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Comment-Date: Tue, 04 Sep 2018 18:45:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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