coreboot-gerrit September 2018

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Change in coreboot[master]: x86/acpi: Add APEI definitions
by Marshall Dawson (Code Review) 06 Sep '18

06 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28469 to look at the new patch set (#2). Change subject: x86/acpi: Add APEI definitions ...................................................................... x86/acpi: Add APEI definitions Add ACPI Platform Error Interfaces definitions that will be used for building a BERT table region in a subsequent patch. Two tables are defined: the Generic Error Status Block, Generic Error Data Entry. For reference, see the ACPI specification 6.2-A tables 381 and 382. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28469/2 -- To view, visit https://review.coreboot.org/28469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Gerrit-Change-Number: 28469 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: src/include: Add CPER definitions
by Marshall Dawson (Code Review) 06 Sep '18

06 Sep '18

Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28468 to look at the new patch set (#2). Change subject: src/include: Add CPER definitions ...................................................................... src/include: Add CPER definitions Add definitions from the UEFI appendix on Common Platform Error Record (appx. N in revision 2.7-A). The structures and fields defined are the minimum required for generating ACPI Boot Error Record data in a subsequent patch. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/include/cper.h 1 file changed, 507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28468/2 -- To view, visit https://review.coreboot.org/28468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Gerrit-Change-Number: 28468 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus: Configure H1 interrupt pad using Rx level config
by build bot (Jenkins) (Code Review) 05 Sep '18

05 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28507 ) Change subject: mb/google/octopus: Configure H1 interrupt pad using Rx level config ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28507/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28507/1/src/mainboard/google/octopus/varian… PS1, Line 94: PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/28507/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/28507/1/src/mainboard/google/octopus/varian… PS1, Line 92: PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ line over 80 characters -- To view, visit https://review.coreboot.org/28507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Gerrit-Change-Number: 28507 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Sep 2018 21:24:48 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Configure H1 interrupt pad using Rx level config
by Furquan Shaikh (Code Review) 05 Sep '18

05 Sep '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28507 Change subject: mb/google/octopus: Configure H1 interrupt pad using Rx level config ...................................................................... mb/google/octopus: Configure H1 interrupt pad using Rx level config This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bip/gpio.c M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/phaser/gpio.c 6 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/28507/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 2942601..2b9d4b4 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -91,7 +91,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */ @@ -297,7 +297,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ /* GSPI0_INT */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ /* GSPI0_CLK */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index 647a903..1e94b0e 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -89,7 +89,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), /* UART2-RTS_B -- LTE_OFF_ODL*/ @@ -290,7 +290,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ /* GSPI0_INT */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ /* GSPI0_CLK */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 8ce2c51..de0f1b2 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -55,7 +55,7 @@ /* PCH_WP_OD */ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 741eeaf..34dd07a 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -92,7 +92,7 @@ /* PCH_WP_OD */ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 0f31388..6f2abc4 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -44,7 +44,7 @@ /* PCH_WP_OD */ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index fd8777b..1c39e65 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -72,7 +72,7 @@ /* PCH_WP_OD */ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/28507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Gerrit-Change-Number: 28507 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: nb/intel/x4x: Don't use cached settings if CPU FSB has been changed
by Arthur Heymans (Code Review) 05 Sep '18

05 Sep '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28506 Change subject: nb/intel/x4x: Don't use cached settings if CPU FSB has been changed ...................................................................... nb/intel/x4x: Don't use cached settings if CPU FSB has been changed Using the cached CPU FSB setting can simply be wrong, in which case it won't boot. Since the selected timings also depend on the CPU FSB, it is also best to not use cached timings at all when a change is detected. UNTESTED. Change-Id: I12d91d0e892c15778409d7c00b27652ee52ca80c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28506/1 diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 9d37ada..b4f103b 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -669,9 +669,16 @@ /* check SPD checksum to make sure the DIMMs haven't been * replaced */ fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS; - if (!fast_boot) + if (!fast_boot) { printk(BIOS_DEBUG, "SPD checksums don't match," " dimm's have been replaced\n"); + } else { + find_fsb_speed(&s); + fast_boot = s.max_fsb == ctrl_cached->max_fsb; + if (!fast_boot) + printk(BIOS_DEBUG, + "CPU FSB does match and has been replaced\n"); + } } else { fast_boot = boot_path == BOOT_PATH_RESUME; } -- To view, visit https://review.coreboot.org/28506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I12d91d0e892c15778409d7c00b27652ee52ca80c Gerrit-Change-Number: 28506 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: rammus: add SPD mapping for rammus and shyvana support.
by Furquan Shaikh (Code Review) 05 Sep '18

05 Sep '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28484 ) Change subject: rammus: add SPD mapping for rammus and shyvana support. ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28484/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/rammus/Makefile.inc: https://review.coreboot.org/#/c/28484/1/src/mainboard/google/poppy/variants… PS1, Line 1: samsung_dimm_K4E8E324EB-EGCF Memory ID 0 and 1 are using the same memory? -- To view, visit https://review.coreboot.org/28484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6 Gerrit-Change-Number: 28484 Gerrit-PatchSet: 1 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Jerry Chou <jerry_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Sep 2018 16:29:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/device/dram: Fix typo
by Elyes HAOUAS (Code Review) 05 Sep '18

05 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28504 Change subject: src/device/dram: Fix typo ...................................................................... src/device/dram: Fix typo Change-Id: I5d8e5f978c538d2b9f74b29e21eb39ce6455315f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28504/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 0d395c4..53106f2 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -124,7 +124,7 @@ /** * \brief Return index of MSB set * - * Returns the index fof MSB set. + * Returns the index of MSB set. */ u8 spd_get_msbs(u8 c) { -- To view, visit https://review.coreboot.org/28504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d8e5f978c538d2b9f74b29e21eb39ce6455315f Gerrit-Change-Number: 28504 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 05 Sep '18

05 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 36: (1 comment) https://review.coreboot.org/#/c/27972/36/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/36/src/arch/riscv/misaligend.c@164 PS36, Line 164: if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) { line over 80 characters -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 36 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Wed, 05 Sep 2018 10:10:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
by Nick Vaccaro (Code Review) 05 Sep '18

05 Sep '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/28424 ) Change subject: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/28424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Gerrit-Change-Number: 28424 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Sep 2018 09:28:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: x86/acpi: Add APEI definitions
by Martin Roth (Code Review) 05 Sep '18

05 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28469 ) Change subject: x86/acpi: Add APEI definitions ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28469/1/src/arch/x86/include/arch/acpi.h File src/arch/x86/include/arch/acpi.h: https://review.coreboot.org/#/c/28469/1/src/arch/x86/include/arch/acpi.h@693 PS1, Line 693: /* zero or more Generic Error Data Entries */ > The "zero or more" part? That odd phrase came from the spec but I can make it better. Yeah, maybe it will make more sense as I finish reviewing the rest of the patches. Just seeing it here makes me say why would we have a status block if there were no entries. -- To view, visit https://review.coreboot.org/28469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Gerrit-Change-Number: 28469 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 04 Sep 2018 22:43:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018