coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0
by Sathyanarayana Nujella (Code Review) 04 Sep '18

04 Sep '18

Hello HARSHAPRIYA N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28433 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0 ...................................................................... mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0 DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Signed-off-by: Harsha Priya <harshapriya.n(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28433/2 -- To view, visit https://review.coreboot.org/28433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Gerrit-Change-Number: 28433 Gerrit-PatchSet: 2 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/include: Introduce guid_t type
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28467 ) Change subject: src/include: Introduce guid_t type ...................................................................... Patch Set 1: > src/include/uuid.h Line 28: please, no spaces at the start of a line Line 29: please, no spaces at the start of a line Line 30: please, no spaces at the start of a line I notice these, and left them there intentionally to help readability. -- To view, visit https://review.coreboot.org/28467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1cd7a1f0e0f900858830e1a6a7e2bbbe272fa30 Gerrit-Change-Number: 28467 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Sep 2018 20:10:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: NOT_FOR_MERGE: Add code to dump BERT region contents
by build bot (Jenkins) (Code Review) 04 Sep '18

04 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28480 ) Change subject: NOT_FOR_MERGE: Add code to dump BERT region contents ...................................................................... Patch Set 1: (150 comments) https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c File src/soc/amd/stoneyridge/bertdump.c: https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 46: static const char *acpi_severity[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 65: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 68: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 71: check & X86_PROC_CHK_OPERATION_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 74: check & X86_PROC_CHK_LEVEL_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 76: printk(0, " e Context Corrupt = %x %s\n", !!(check & X86_PROC_CHK_CTX_CORRUPT), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 77: check & X86_PROC_CHK_CONTEXT_CORPT_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 79: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 80: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 82: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 83: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 85: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 86: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 88: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 89: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 92: check & X86_PROC_CHK_PART_TYPE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 94: printk(0, " e Time Out = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 95: check & X86_PROC_CHK_TIMEOUT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 98: check & X86_PROC_CHK_ADDR_SPACE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 104: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 107: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 109: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_MS_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 110: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 112: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_MS_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 113: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 115: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_MS_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 116: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 118: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_MS_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 119: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 122: static const char *check_guid_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 147: printk(0, " ___ CPER IA32/x64 Processor Error (Check) Information @0x%p - 0x%p (size 0x%zx) ___\n", err, err + 1, sizeof(*err)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 148: printk(0, " e Structure Type GUID = %s\n", check_guid_name(err->type)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 151: printk(0, " e Validation Bits = %llx\n", err->validation); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 153: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 154: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 155: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 156: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 158: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 159: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 160: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 161: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 163: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 164: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 165: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 166: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 167: | X86_PROC_CHK_PART_TYPE_VALID | X86_PROC_CHK_TIMEOUT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 168: | X86_PROC_CHK_ADDR_SPACE_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 170: x86_mschkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 171: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 172: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 179: static const char *context_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 210: printk(0, " ___ CPER IA32/x64 Processor Context Information @0x%p - 0x%p (size 0x%zx) ___\n", ctx, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 211: (u8 *)ctx + ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 212: ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 213: printk(0, " t Context Type = %x %s\n", ctx->type, context_name(ctx->type)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 214: printk(0, " t Array Size = %x\n", ctx->array_size); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 216: printk(0, " t MM Address = %llx\n", ctx->mmap_addr); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 224: printk(0, " t %08x_%08x\n", (u32)(*(array + i) >> 32), (u32)*(array + i)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 233: int errs = (ia32->validation & I32X64SEC_VALID_ERRNUM_MASK) >> I32X64SEC_VALID_ERRNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 234: int ctxs = (ia32->validation & I32X64SEC_VALID_CTXNUM_MASK) >> I32X64SEC_VALID_CTXNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 236: printk(0, " ___ CPER IA32/x64 Processor Error @0x%p sizeof(proc error section struct) is 0x%zx/%zd) ___\n", ia32, sizeof(*ia32), sizeof(*ia32)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 237: printk(0, " x Validation Bits = %llx\n", ia32->validation); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 240: printk(0, " x Processor APIC ID = %llx %s\n", ia32->apicid, ia32->validation & I32X64SEC_VALID_LAPIC ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 241: printk(0, " x Processor CPUID = EAX = %x %s\n", (u32)ia32->cpuid[0], ia32->validation & I32X64SEC_VALID_CPUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 242: printk(0, " x EBX = %x\n", (u32)ia32->cpuid[1]); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 243: printk(0, " x ECX = %x\n", (u32)ia32->cpuid[2]); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 244: printk(0, " x EDX = %x\n", (u32)ia32->cpuid[3]); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 248: adder += parse_x86_error_info((cper_ia32x64_proc_error_info_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 251: adder += parse_x86_context_info((cper_ia32x64_context_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 256: static size_t parse_cper_structure_generic(cper_proc_generic_error_section_t *gen) line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 258: printk(0, " ___ CPER Generic Processor Error @0x%p sizeof(generic error struct) is 0x%zx/%zd\n", gen, sizeof(*gen), sizeof(*gen)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 259: printk(0, " c Validation Bits = %llx\n", gen->validation); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 260: printk(0, " c Processor Type = %x %s\n", gen->proc_type, gen->validation & GENPROC_VALID_PROC_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 261: printk(0, " c Processor ISA = %x %s\n", gen->proc_isa, gen->validation & GENPROC_VALID_PROC_ISA ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 262: printk(0, " c Processor Error Type = %x %s\n", gen->error_type, gen->validation & GENPROC_VALID_PROC_ERR_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 263: printk(0, " c Operation = %x %s\n", gen->operation, gen->validation & GENPROC_VALID_OPERATION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 264: printk(0, " c Flags = %x %s\n", gen->flags, gen->validation & GENPROC_VALID_FLAGS ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 265: printk(0, " c Level = %x %s\n", gen->level, gen->validation & GENPROC_VALID_LEVEL ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 266: printk(0, " c CPU Version Info = %llx %s\n", gen->cpu_version, gen->validation & GENPROC_VALID_CPU_VERSION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 267: printk(0, " c CPU Brand String = %s %s\n", gen->cpu_brand_string, gen->validation & GENPROC_VALID_CPU_BRAND ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 268: printk(0, " c Processor ID = %llx %s\n", gen->proc_id, gen->validation & GENPROC_VALID_CPU_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 269: printk(0, " c Target Address = %llx %s\n", gen->target_addr, gen->validation & GENPROC_VALID_TGT_ADDR ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 270: printk(0, " c Requestor Identifier = %llx %s\n", gen->requestor_id, gen->validation & GENPROC_VALID_REQR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 271: printk(0, " c Responder Identifier = %llx %s\n", gen->responder_id, gen->validation & GENPROC_VALID_RSPR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 272: printk(0, " c Instruction IP = %llx %s\n", gen->instruction_ip, gen->validation & GENPROC_VALID_INSTR_IP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 296: return sizeof(acpi_hest_generic_data_v300_t) + entry->data_length; line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 301: static const char *guids382[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 319: if(!guidcmp(&guid, &CPER_SEC_PROC_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 321: if(!guidcmp(&guid, &CPER_SEC_PROC_IA32X64_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 323: if(!guidcmp(&guid, &CPER_SEC_PROC_ARM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 325: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 327: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM2_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 329: if(!guidcmp(&guid, &CPER_SEC_PCIE_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 331: if(!guidcmp(&guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 333: if(!guidcmp(&guid, &CPER_SEC_PCI_X_BUS_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 335: if(!guidcmp(&guid, &CPER_SEC_PCI_DEV_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 337: if(!guidcmp(&guid, &CPER_SEC_DMAR_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 339: if(!guidcmp(&guid, &CPER_SEC_DMAR_VT_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 341: if(!guidcmp(&guid, &CPER_SEC_DMAR_IOMMU_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 351: printk(0, " ___ 382 found @0x%p sizeof(%s) = 0x%zx/%zd ___\n", entry, entry->revision == 0x300 ? "v3" : "old-type", line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 352: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t), line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 353: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 354: printk(0, " 3 Section Type GUID = %s\n", guid382_name(entry->section_type)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 357: printk(0, " 3 Severity = %x: %s\n", entry->error_severity, acpi_sev(entry->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 358: printk(0, " 3 Revision = %x\n", entry->revision); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 359: printk(0, " 3 Validation = %x\n", entry->validation_bits); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 361: printk(0, " 3 Error Data Length = %x\n", entry->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 362: printk(0, " 3 FRU ID = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 363: printk(0, " 3 FRU text = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID_TEXT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 365: /* I can cheat on x300 because I know only diff is timestamp */ line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 370: entry->timestamp.hour, entry->timestamp.min, entry->timestamp.sec, line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 371: entry->validation_bits & ACPI_GENERROR_VALID_TIMESTAMP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 375: /* each table-382 entry should contain 0 or 1 cper structure at its end */ line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 378: parse_cper_structure((void *)(entry + 1), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 380: parse_cper_structure((void *)((u8 *)entry + sizeof(acpi_hest_generic_data_t)), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 384: entry = (acpi_hest_generic_data_v300_t *)((u8 *)entry + entry382_size(entry)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 400: static acpi_hest_generic_data_v300_t *ptr382_from_bert_entry(acpi_generic_error_status_t *bert_data) line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 403: return (acpi_hest_generic_data_v300_t *)((u8 *)bert_data + sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 429: printk(0, "***** BERT storage at 0x%p - 0x%p (%zd) *****\n", bert_base, (u8 *)bert_base + size, size); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 431: while(offset < size) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 432: entries = (bert_data->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) >> GENERIC_ERR_STS_ENTRY_COUNT_SHIFT; line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 433: printk(0, " ___ BERT entry @0x%p - (sizeof(status)=0x%zx/%zd) ___\n", bert_data, sizeof(*bert_data), sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 434: printk(0, " b Block Status = %x\n", bert_data->block_status); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 436: bert_data->block_status & BIT(0) ? " uncorrectable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 437: bert_data->block_status & BIT(1) ? " correctable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 438: bert_data->block_status & BIT(2) ? " mult-uncorrected" : "", line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 439: bert_data->block_status & BIT(3) ? " mult-corrected" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 441: printk(0, " b Raw Data Offset = %x\n", bert_data->raw_data_offset); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 442: printk(0, " b Raw Data Length = %x\n", bert_data->raw_data_length); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 443: printk(0, " b Data Length = %x\n", bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 444: printk(0, " b Error Severity = %x: %s\n", bert_data->error_severity, acpi_sev(bert_data->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 445: if (bert_data->data_length && bert_data->data_length < sizeof(acpi_hest_generic_data_v300_t)) line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 447: bert_data->data_length, sizeof(acpi_hest_generic_data_v300_t)); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 448: if (bert_data->raw_data_length && bert_data->raw_data_offset < sizeof(*bert_data) + bert_data->data_length) line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 450: bert_data->raw_data_offset, sizeof(*bert_data), bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 453: /* can have zero or more data entries, of type 382 and/or of raw */ line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 454: gen382 = ptr382_from_bert_entry(bert_data); // todo: this only handles a single 382 entry line over 80 characters https://review.coreboot.org/#/c/28480/1/src/soc/amd/stoneyridge/bertdump.c@… PS1, Line 463: bert_data = (acpi_generic_error_status_t *)((u8 *)bert_data + offset); line over 80 characters -- To view, visit https://review.coreboot.org/28480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ecf920499a662db34a332e9df05e4ee2383b6d4 Gerrit-Change-Number: 28480 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Sep 2018 20:09:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src/include: Introduce guid_t type
by build bot (Jenkins) (Code Review) 04 Sep '18

04 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28467 ) Change subject: src/include: Introduce guid_t type ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/28467/1/src/include/uuid.h File src/include/uuid.h: https://review.coreboot.org/#/c/28467/1/src/include/uuid.h@28 PS1, Line 28: (b) & 0xff, ((b) >> 8) & 0xff, \ please, no spaces at the start of a line https://review.coreboot.org/#/c/28467/1/src/include/uuid.h@29 PS1, Line 29: (c) & 0xff, ((c) >> 8) & 0xff, \ please, no spaces at the start of a line https://review.coreboot.org/#/c/28467/1/src/include/uuid.h@30 PS1, Line 30: (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1cd7a1f0e0f900858830e1a6a7e2bbbe272fa30 Gerrit-Change-Number: 28467 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Sep 2018 20:07:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: NOT_FOR_MERGE: Add fake MCA errors to test BERT
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28481 Change subject: NOT_FOR_MERGE: Add fake MCA errors to test BERT ...................................................................... NOT_FOR_MERGE: Add fake MCA errors to test BERT Fill the BERT region with some sample errors. The first core's errors should be reported by the ACPI driver as: [Hardware Error]: event severity: fatal [Hardware Error]: precise tstamp: 2018-09-04 16:58:11 [Hardware Error]: Error 0, type: fatal [Hardware Error]: section_type: general processor error [Hardware Error]: processor_type: 0, IA32/X64 [Hardware Error]: error_type: 0x01 [Hardware Error]: cache error [Hardware Error]: version_info: 0x0000000000670f00 [Hardware Error]: processor_id: 0x0000000000000010 [Hardware Error]: precise tstamp: 2018-09-04 16:58:11 [Hardware Error]: Error 1, type: fatal [Hardware Error]: section type: unknown, dc3ea0b0-a144-4797-b95b-53fa242b6e1d [Hardware Error]: section length: 0x100 [Hardware Error]: 00000000: 00000307 00000000 00000010 00000000 ................ [Hardware Error]: 00000010: 00670f00 00000000 00020800 00000000 ..g............. [Hardware Error]: 00000020: 76d8320b 00000000 178bfbff 00000000 .2.v............ [Hardware Error]: 00000030: 00000000 00000000 00000000 00000000 ................ [Hardware Error]: 00000040: a55701f5 43dee3ef 9b2472ac 2cad3f57 ..W....C.r$.W?., [Hardware Error]: 00000050: 00000000 00000000 00000000 00000000 ................ [Hardware Error]: 00000060: 00000000 00000000 00000000 00000000 ................ [Hardware Error]: 00000070: 00000000 00000000 00000000 00000000 ................ [Hardware Error]: 00000080: 00180001 00000179 00000000 00000000 ....y........... [Hardware Error]: 00000090: 00000107 00000000 00000000 00000000 ................ [Hardware Error]: 000000a0: 00000000 00000000 00000000 00000000 ................ [Hardware Error]: 000000b0: 00200001 00000404 00000000 00000000 .. ............. [Hardware Error]: 000000c0: 00000000 00000000 00100153 fe000000 ........S....... [Hardware Error]: 000000d0: 00000009 00000000 00000000 d01a0003 ................ [Hardware Error]: 000000e0: 00080001 c0010045 00000000 00000000 ....E........... [Hardware Error]: 000000f0: 00000080 00000000 00000000 00000000 ................ Change-Id: I413955fb0fcf0d98a89da647f6f70b0df25a923a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/acpi_bert_storage.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 97 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28481/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 826c14c..c15989c 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -487,6 +487,8 @@ return NULL; } +void fake_msr_reads(msr_t *p, u32 addr, int num); + /* Helper to add an MSR context to an existing IA32/X64-type error entry */ cper_ia32x64_context_t *cper_new_ia32x64_context_msr( acpi_generic_error_status_t *status, @@ -506,8 +508,11 @@ dest = (msr_t *)((u8 *)(ctx + 1)); /* point to the Register Array */ - for (i = 0 ; i < num ; i++) - *(dest + i) = rdmsr(addr + i); + if (1) + fake_msr_reads(dest, addr, num); + else + for (i = 0 ; i < num ; i++) + *(dest + i) = rdmsr(addr + i); return ctx; } diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 81d95fb..e762134 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -13,7 +13,9 @@ * GNU General Public License for more details. */ +#include <cpu/x86/mp.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <cpu/amd/amdfam15.h> #include <soc/cpu.h> @@ -31,6 +33,84 @@ msr_t cmask; }; +void fake_msr_reads(msr_t *p, u32 addr, int num); +void fake_msr_reads(msr_t *p, u32 addr, int num) +{ + int i; + + /* These are taken from actual failures we've seen */ + switch (addr) { + case 0x404: /* 1 */ + p[0].hi = 0x00000000; p[0].lo = 0x00000000; + p[1].hi = 0xfe000000; p[1].lo = 0x00100153; + p[2].hi = 0x00000000; p[2].lo = 0x00000009; + p[3].hi = 0xd01a0003; p[3].lo = 0x00000000; + break; + case 0x408: /* 2 */ + p[0].hi = 0x00000000; p[0].lo = 0x00000000; + p[1].hi = 0xb6000000; p[1].lo = 0x0012010a; + p[2].hi = 0x00000000; p[2].lo = 0x00004500; + p[3].hi = 0xd0100000; p[3].lo = 0x00000000; + break; + case 0x410: /* 4 */ + p[0].hi = 0x00000000; p[0].lo = 0x00000000; + p[1].hi = 0xb2000010; p[1].lo = 0x00020c0f; + p[2].hi = 0x00000000; p[2].lo = 0x00000000; + p[3].hi = 0xd0000000; p[3].lo = 0x01000000; + break; + case 0x418: /* 6 */ + p[0].hi = 0x00000000, p[0].lo = 0x00000000; + p[1].hi = 0xb2000000, p[1].lo = 0x00030e0f; + p[2].hi = 0x00000000, p[2].lo = 0x00000000; + p[3].hi = 0x00000000, p[3].lo = 0x00000000; + break; + case 0x400: /* 0 */ + case 0x40c: /* 3 */ + case 0x414: /* 5 */ + default: + for (i = 0 ; i < num ; i++) + p[i] = rdmsr(addr + i); + break; + } +} + +void load_fake_msr_info(struct mca_bank *mci, int bank); +void load_fake_msr_info(struct mca_bank *mci, int bank) +{ + + /* These are taken from actual failures we've seen */ + switch (bank) { + case 1: /* 1 */ + mci->bank = 1; + mci->ctl.hi = 0x00000000; mci->ctl.lo = 0x00000000; + mci->sts.hi = 0xfe000000; mci->sts.lo = 0x00100153; + mci->addr.hi = 0x00000000; mci->addr.lo = 0x00000009; + mci->misc.hi = 0xd01a0003; mci->misc.lo = 0x00000000; + break; + case 2: /* 2 */ + mci->bank = 2; + mci->ctl.hi = 0x00000000; mci->ctl.lo = 0x00000000; + mci->sts.hi = 0xb6000000; mci->sts.lo = 0x0012010a; + mci->addr.hi = 0x00000000; mci->addr.lo = 0x00004500; + mci->misc.hi = 0xd0100000; mci->misc.lo = 0x00000000; + break; + case 4: /* 4 */ + mci->bank = 4; + mci->ctl.hi = 0x00000000; mci->ctl.lo = 0x00000000; + mci->sts.hi = 0xb2000010; mci->sts.lo = 0x00020c0f; + mci->addr.hi = 0x00000000; mci->addr.lo = 0x00000000; + mci->misc.hi = 0xd0000000; mci->misc.lo = 0x01000000; + break; + case 6: /* 6 */ + mci->bank = 6; + mci->ctl.hi = 0x00000000, mci->ctl.lo = 0x00000000; + mci->sts.hi = 0xb2000000, mci->sts.lo = 0x00030e0f; + mci->addr.hi = 0x00000000, mci->addr.lo = 0x00000000; + mci->misc.hi = 0x00000000, mci->misc.lo = 0x00000000; + break; + } +} + static inline size_t mca_report_size_reqd(void) { size_t size; @@ -180,6 +260,16 @@ cap = rdmsr(MCG_CAP); num_banks = cap.lo & MCA_BANKS_MASK; + + printk(0, "======================= Adding Fake MC Errors ====================\n"); + if (boot_cpu()) { + load_fake_msr_info(&mci, 1); + build_bert_mca_error(&mci); + } else { + load_fake_msr_info(&mci, 4); + build_bert_mca_error(&mci); + } + if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { if (i == 3) /* Reserved in Family 15h */ -- To view, visit https://review.coreboot.org/28481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I413955fb0fcf0d98a89da647f6f70b0df25a923a Gerrit-Change-Number: 28481 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: NOT_FOR_MERGE: Add code to dump BERT region contents
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28480 Change subject: NOT_FOR_MERGE: Add code to dump BERT region contents ...................................................................... NOT_FOR_MERGE: Add code to dump BERT region contents Has been useful for development and debug. Change-Id: I8ecf920499a662db34a332e9df05e4ee2383b6d4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/bertdump.c M src/soc/amd/stoneyridge/finalize.c 3 files changed, 474 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28480/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index a8db2c2..45e8aa3 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -37,6 +37,8 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm +ramstage-y += bertdump.c + bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock/bootblock.c diff --git a/src/soc/amd/stoneyridge/bertdump.c b/src/soc/amd/stoneyridge/bertdump.c new file mode 100644 index 0000000..187ca24 --- /dev/null +++ b/src/soc/amd/stoneyridge/bertdump.c @@ -0,0 +1,465 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <cpu/amd/amdfam15.h> +#include <soc/cpu.h> +#include <console/console.h> +#include <lib.h> +#include <commonlib/helpers.h> +#include <arch/bert_storage.h> +#include <cper.h> + +///////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////// +// +// +// Table checker code +// +// +///////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////// + +static void print_guid(guid_t guid) +{ + u8 *g = (u8 *)&guid; + printk(0, "{{0x%02x%02x%02x%02x, 0x%02x%02x, 0x%02x%02x, {0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x}}\n", + g[3], g[2], g[1], g[0], + g[5], g[4], + g[7], g[6], + g[8], g[9], g[10], g[11], g[12], g[13], g[14], g[15]); +} + +// Status and Error Data structures have idential Error Severity definitions +static const char *acpi_severity[] = { + "Recoverable", + "Fatal", + "Corrected", + "None", + "you did something wrong" +}; + +static const char *acpi_sev(u32 sev) +{ + if (sev > 3) + return acpi_severity[4]; + return acpi_severity[sev]; +} + +static void x86_chkprint_with_valid(u64 check, u64 valid) +{ + + if (check & 0xffff & ~valid) /* validation bits are 15:0 */ + printk(0, " e * Invalid bits %llx\n", check & ~valid); + if (valid & X86_PROC_CHK_XACT_MASK) + printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, + check & X86_PROC_CHK_XACT_MASK ? "V" : ""); + if (valid & X86_PROC_CHK_OPERATION_VALID) + printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, + check & X86_PROC_CHK_OPERATION_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_LEVEL_VALID) + printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, + check & X86_PROC_CHK_LEVEL_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_CONTEXT_CORPT_VALID) + printk(0, " e Context Corrupt = %x %s\n", !!(check & X86_PROC_CHK_CTX_CORRUPT), + check & X86_PROC_CHK_CONTEXT_CORPT_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_UNCORRECTED_VALID) + printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_CHK_UNCORRECTED), + check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_PRECISE_IP_VALID) + printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_CHK_PRECISE_IP), + check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_RESTARTABLE_VALID) + printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_CHK_RESTARTABLE_IP), + check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_OVERFLOW_VALID) + printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), + check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_PART_TYPE_VALID) + printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, + check & X86_PROC_CHK_PART_TYPE_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_TIMEOUT) + printk(0, " e Time Out = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), + check & X86_PROC_CHK_TIMEOUT ? "V" : ""); + if (valid & X86_PROC_CHK_ADDR_SPACE_VALID) + printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, + check & X86_PROC_CHK_ADDR_SPACE_VALID ? "V" : ""); +} + +static void x86_mschkprint_with_valid(u64 check, u64 valid) +{ + if (check & 0xffff & ~valid) /* validation bits are 15:0 */ + printk(0, " e * Invalid bits %llx\n", check & ~valid); + if (valid & X86_PROC_CHK_XACT_MASK) + printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, + check & X86_PROC_CHK_XACT_MASK ? "V" : ""); + if (valid & X86_PROC_CHK_UNCORRECTED_VALID) + printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_MS_CHK_UNCORRECTED), + check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_PRECISE_IP_VALID) + printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_MS_CHK_PRECISE_IP), + check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_RESTARTABLE_VALID) + printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_MS_CHK_RESTARTABLE_IP), + check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); + if (valid & X86_PROC_CHK_OVERFLOW_VALID) + printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_MS_CHK_OVERFLOW), + check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); +} + +static const char *check_guid_names[] = { + "CACHE_CHK_ERROR_GUID", + "TLB_CHK_ERROR_GUID", + "BUS_CHK_ERROR_GUID", + "MS_CHK_ERROR_GUID", + "you did something wrong" +}; + +static const char *check_guid_name(guid_t type) +{ + + if (!guidcmp(&type, &X86_PROCESSOR_CACHE_CHK_ERROR_GUID)) + return check_guid_names[0]; + if (!guidcmp(&type, &X86_PROCESSOR_TLB_CHK_ERROR_GUID)) + return check_guid_names[1]; + if (!guidcmp(&type, &X86_PROCESSOR_BUS_CHK_ERROR_GUID)) + return check_guid_names[2]; + if (!guidcmp(&type, &X86_PROCESSOR_MS_CHK_ERROR_GUID)) + return check_guid_names[3]; + + return check_guid_names[4]; +} + +static size_t parse_x86_error_info(cper_ia32x64_proc_error_info_t *err) +{ + printk(0, " ___ CPER IA32/x64 Processor Error (Check) Information @0x%p - 0x%p (size 0x%zx) ___\n", err, err + 1, sizeof(*err)); + printk(0, " e Structure Type GUID = %s\n", check_guid_name(err->type)); + printk(0, " e Structure Type = "); + print_guid(err->type); + printk(0, " e Validation Bits = %llx\n", err->validation); + if (!guidcmp(&err->type, &X86_PROCESSOR_CACHE_CHK_ERROR_GUID)) + x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID + | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID + | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID + | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); + else if (!guidcmp(&err->type, &X86_PROCESSOR_TLB_CHK_ERROR_GUID)) + x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID + | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID + | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID + | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); + else if (!guidcmp(&err->type, &X86_PROCESSOR_BUS_CHK_ERROR_GUID)) + x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID + | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID + | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID + | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID + | X86_PROC_CHK_PART_TYPE_VALID | X86_PROC_CHK_TIMEOUT_VALID + | X86_PROC_CHK_ADDR_SPACE_VALID); + else if (!guidcmp(&err->type, &X86_PROCESSOR_MS_CHK_ERROR_GUID)) + x86_mschkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID + | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID + | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID); + else + printk(0, " e INVALID CHECK TYPE!\n"); + printk(0, " eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee\n"); + return sizeof(*err); +} + +static const char *context_names[] = { + "Unclassified data", + "MSR Registers", + "32-bit mode execution registers", + "64-bit mode execution registers", + "FXSAVE context", + "32-bit mode debug registers", + "64-bit mode debug registers", + "Memory mapped registers", + "you did something wrong" +}; + +static const char *context_name(int type) +{ + switch (type) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + return context_names[type]; + default: + return context_names[8]; + } +} + +static size_t parse_x86_context_info(cper_ia32x64_context_t *ctx) +{ + printk(0, " ___ CPER IA32/x64 Processor Context Information @0x%p - 0x%p (size 0x%zx) ___\n", ctx, + (u8 *)ctx + ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16), + ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16)); + printk(0, " t Context Type = %x %s\n", ctx->type, context_name(ctx->type)); + printk(0, " t Array Size = %x\n", ctx->array_size); + printk(0, " t MSR Address = %x\n", ctx->msr_addr); + printk(0, " t MM Address = %llx\n", ctx->mmap_addr); + + int i; + u64 *array = (u64 *)(ctx + 1); + printk(0, " t Data Array\n"); + + int array_size = ctx->array_size / sizeof(u64); + for (i = 0 ; i < array_size ; i++) + printk(0, " t %08x_%08x\n", (u32)(*(array + i) >> 32), (u32)*(array + i)); + + printk(0, " ttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt\n"); + return ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16); +} + +static size_t parse_cper_structure_x86(cper_ia32x64_proc_error_section_t *ia32) +{ + int i; + int errs = (ia32->validation & I32X64SEC_VALID_ERRNUM_MASK) >> I32X64SEC_VALID_ERRNUM_SH; + int ctxs = (ia32->validation & I32X64SEC_VALID_CTXNUM_MASK) >> I32X64SEC_VALID_CTXNUM_SH; + + printk(0, " ___ CPER IA32/x64 Processor Error @0x%p sizeof(proc error section struct) is 0x%zx/%zd) ___\n", ia32, sizeof(*ia32), sizeof(*ia32)); + printk(0, " x Validation Bits = %llx\n", ia32->validation); + printk(0, " x errors = %d\n", errs); + printk(0, " x contexts = %d\n", ctxs); + printk(0, " x Processor APIC ID = %llx %s\n", ia32->apicid, ia32->validation & I32X64SEC_VALID_LAPIC ? "V" : ""); + printk(0, " x Processor CPUID = EAX = %x %s\n", (u32)ia32->cpuid[0], ia32->validation & I32X64SEC_VALID_CPUID ? "V" : ""); + printk(0, " x EBX = %x\n", (u32)ia32->cpuid[1]); + printk(0, " x ECX = %x\n", (u32)ia32->cpuid[2]); + printk(0, " x EDX = %x\n", (u32)ia32->cpuid[3]); + + uintptr_t adder = sizeof(*ia32); + for (i = 0 ; i < errs ; i++) + adder += parse_x86_error_info((cper_ia32x64_proc_error_info_t *)((u8 *)ia32 + adder)); + + for (i = 0 ; i < ctxs ; i++) + adder += parse_x86_context_info((cper_ia32x64_context_t *)((u8 *)ia32 + adder)); + + return adder; +} + +static size_t parse_cper_structure_generic(cper_proc_generic_error_section_t *gen) +{ + printk(0, " ___ CPER Generic Processor Error @0x%p sizeof(generic error struct) is 0x%zx/%zd\n", gen, sizeof(*gen), sizeof(*gen)); + printk(0, " c Validation Bits = %llx\n", gen->validation); + printk(0, " c Processor Type = %x %s\n", gen->proc_type, gen->validation & GENPROC_VALID_PROC_TYPE ? "V" : ""); + printk(0, " c Processor ISA = %x %s\n", gen->proc_isa, gen->validation & GENPROC_VALID_PROC_ISA ? "V" : ""); + printk(0, " c Processor Error Type = %x %s\n", gen->error_type, gen->validation & GENPROC_VALID_PROC_ERR_TYPE ? "V" : ""); + printk(0, " c Operation = %x %s\n", gen->operation, gen->validation & GENPROC_VALID_OPERATION ? "V" : ""); + printk(0, " c Flags = %x %s\n", gen->flags, gen->validation & GENPROC_VALID_FLAGS ? "V" : ""); + printk(0, " c Level = %x %s\n", gen->level, gen->validation & GENPROC_VALID_LEVEL ? "V" : ""); + printk(0, " c CPU Version Info = %llx %s\n", gen->cpu_version, gen->validation & GENPROC_VALID_CPU_VERSION ? "V" : ""); + printk(0, " c CPU Brand String = %s %s\n", gen->cpu_brand_string, gen->validation & GENPROC_VALID_CPU_BRAND ? "V" : ""); + printk(0, " c Processor ID = %llx %s\n", gen->proc_id, gen->validation & GENPROC_VALID_CPU_ID ? "V" : ""); + printk(0, " c Target Address = %llx %s\n", gen->target_addr, gen->validation & GENPROC_VALID_TGT_ADDR ? "V" : ""); + printk(0, " c Requestor Identifier = %llx %s\n", gen->requestor_id, gen->validation & GENPROC_VALID_REQR_ID ? "V" : ""); + printk(0, " c Responder Identifier = %llx %s\n", gen->responder_id, gen->validation & GENPROC_VALID_RSPR_ID ? "V" : ""); + printk(0, " c Instruction IP = %llx %s\n", gen->instruction_ip, gen->validation & GENPROC_VALID_INSTR_IP ? "V" : ""); + printk(0, " cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc\n"); + + return sizeof(*gen); +} + +static size_t parse_cper_structure(void *st, guid_t type) +{ + if (!guidcmp(&type, &CPER_SEC_PROC_GENERIC_GUID)) + return parse_cper_structure_generic(st); + else if (!guidcmp(&type, &CPER_SEC_PROC_IA32X64_GUID)) + return parse_cper_structure_x86(st); + // else if... + + printk(0, "Error, you asked me to parse type for "); + print_guid(type); + return 0; +} + +static size_t entry382_size(void *e382) +{ + acpi_hest_generic_data_t *entry = (acpi_hest_generic_data_t *)e382; + + if (entry->revision == HEST_GENERIC_ENTRY_V300) + return sizeof(acpi_hest_generic_data_v300_t) + entry->data_length; + else + return sizeof(acpi_hest_generic_data_t) + entry->data_length; +} + +static const char *guids382[] = { + "PROCESSOR_GENERIC", + "PROCESSOR_SPECIFIC_X86_GUID", + "PROCESSOR_SPECIFIC_ARM_GUID", + "PLATFORM_MEMORY_GUID", + "PLATFORM_MEMORY2_GUID", + "PCIE_GUID", + "FW_ERROR_RECORD_GUID", + "PCI_PCIX_BUS_GUID", + "PCI_DEVICE_GUID", + "DMAR_GENERIC_GUID", + "DIRECTED_IO_DMAR_GUID", + "IOMMU_DMAR_GUID", + "you did something wrong" +}; + +static const char *guid382_name(guid_t guid) +{ + if(!guidcmp(&guid, &CPER_SEC_PROC_GENERIC_GUID)) + return guids382[0]; + if(!guidcmp(&guid, &CPER_SEC_PROC_IA32X64_GUID)) + return guids382[1]; + if(!guidcmp(&guid, &CPER_SEC_PROC_ARM_GUID)) + return guids382[2]; + if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM_GUID)) + return guids382[3]; + if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM2_GUID)) + return guids382[4]; + if(!guidcmp(&guid, &CPER_SEC_PCIE_GUID)) + return guids382[5]; + if(!guidcmp(&guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) + return guids382[6]; + if(!guidcmp(&guid, &CPER_SEC_PCI_X_BUS_GUID)) + return guids382[7]; + if(!guidcmp(&guid, &CPER_SEC_PCI_DEV_GUID)) + return guids382[8]; + if(!guidcmp(&guid, &CPER_SEC_DMAR_GENERIC_GUID)) + return guids382[9]; + if(!guidcmp(&guid, &CPER_SEC_DMAR_VT_GUID)) + return guids382[10]; + if(!guidcmp(&guid, &CPER_SEC_DMAR_IOMMU_GUID)) + return guids382[11]; + return guids382[12]; +} + +static void parse_382_data(acpi_hest_generic_data_v300_t *entry, size_t size) +{ + size_t offset = 0; + + while (size > offset) { + printk(0, " ___ 382 found @0x%p sizeof(%s) = 0x%zx/%zd ___\n", entry, entry->revision == 0x300 ? "v3" : "old-type", + entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t), + entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t)); + printk(0, " 3 Section Type GUID = %s\n", guid382_name(entry->section_type)); + printk(0, " 3 Section Type = "); + print_guid(entry->section_type); + printk(0, " 3 Severity = %x: %s\n", entry->error_severity, acpi_sev(entry->error_severity)); + printk(0, " 3 Revision = %x\n", entry->revision); + printk(0, " 3 Validation = %x\n", entry->validation_bits); + printk(0, " 3 Flags = %x\n", entry->flags); + printk(0, " 3 Error Data Length = %x\n", entry->data_length); + printk(0, " 3 FRU ID = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID ? "V" : ""); + printk(0, " 3 FRU text = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID_TEXT ? "V" : ""); + if (entry->revision == HEST_GENERIC_ENTRY_V300) { + /* I can cheat on x300 because I know only diff is timestamp */ + printk(0, " 3 Timestamp = %02x, %02x%02x/%02x/%02x %02x:%02x:%02x %s\n", + entry->timestamp.precise, + entry->timestamp.century, entry->timestamp.year, + entry->timestamp.month, entry->timestamp.day, + entry->timestamp.hour, entry->timestamp.min, entry->timestamp.sec, + entry->validation_bits & ACPI_GENERROR_VALID_TIMESTAMP ? "V" : ""); + } + printk(0, " 333333333333333333333333333333333333333333333333333333333\n"); + + /* each table-382 entry should contain 0 or 1 cper structure at its end */ + if (entry->data_length) { + if (entry->revision == HEST_GENERIC_ENTRY_V300) + parse_cper_structure((void *)(entry + 1), entry->section_type); + else /* maybe I did this right? */ + parse_cper_structure((void *)((u8 *)entry + sizeof(acpi_hest_generic_data_t)), entry->section_type); + } + + offset += entry382_size(entry); + entry = (acpi_hest_generic_data_v300_t *)((u8 *)entry + entry382_size(entry)); + } +} + +static size_t bert_entry_size(acpi_generic_error_status_t *bert_data) +{ + size_t size = sizeof(*bert_data); + + if (bert_data->raw_data_length) + size += bert_data->raw_data_offset + bert_data->data_length; + else + size += bert_data->data_length; + + return size; +} + +static acpi_hest_generic_data_v300_t *ptr382_from_bert_entry(acpi_generic_error_status_t *bert_data) +{ + if (bert_data->data_length) + return (acpi_hest_generic_data_v300_t *)((u8 *)bert_data + sizeof(*bert_data)); + else + return (acpi_hest_generic_data_v300_t *)NULL; +} + +static u8 *ptr_raw_from_bert_entry(acpi_generic_error_status_t *bert_data) +{ + if (bert_data->raw_data_length) + return (u8 *)bert_data + bert_data->raw_data_offset; + else + return (u8 *)NULL; +} + +void parse_bert_region(void); +void parse_bert_region(void) +{ + acpi_generic_error_status_t *bert_base; + size_t size; + bert_errors_region((void **)&bert_base, &size); + + acpi_generic_error_status_t *bert_data = bert_base; + size_t offset = 0; + acpi_hest_generic_data_v300_t *gen382; + u8 *raw; + int entries; + + printk(0, "***** BERT storage at 0x%p - 0x%p (%zd) *****\n", bert_base, (u8 *)bert_base + size, size); + + while(offset < size) { + entries = (bert_data->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) >> GENERIC_ERR_STS_ENTRY_COUNT_SHIFT; + printk(0, " ___ BERT entry @0x%p - (sizeof(status)=0x%zx/%zd) ___\n", bert_data, sizeof(*bert_data), sizeof(*bert_data)); + printk(0, " b Block Status = %x\n", bert_data->block_status); + printk(0, " b severity =%s%s%s%s\n", + bert_data->block_status & BIT(0) ? " uncorrectable" : "", + bert_data->block_status & BIT(1) ? " correctable" : "", + bert_data->block_status & BIT(2) ? " mult-uncorrected" : "", + bert_data->block_status & BIT(3) ? " mult-corrected" : ""); + printk(0, " b count = %x\n", entries); + printk(0, " b Raw Data Offset = %x\n", bert_data->raw_data_offset); + printk(0, " b Raw Data Length = %x\n", bert_data->raw_data_length); + printk(0, " b Data Length = %x\n", bert_data->data_length); + printk(0, " b Error Severity = %x: %s\n", bert_data->error_severity, acpi_sev(bert_data->error_severity)); + if (bert_data->data_length && bert_data->data_length < sizeof(acpi_hest_generic_data_v300_t)) + printk(0, " b ERROR: data length not large enough: %d < %zd\n", + bert_data->data_length, sizeof(acpi_hest_generic_data_v300_t)); + if (bert_data->raw_data_length && bert_data->raw_data_offset < sizeof(*bert_data) + bert_data->data_length) + printk(0, " b ERROR: raw data offset is bad: %d < %zd + %d\n", + bert_data->raw_data_offset, sizeof(*bert_data), bert_data->data_length); + printk(0, " bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb\n"); + + /* can have zero or more data entries, of type 382 and/or of raw */ + gen382 = ptr382_from_bert_entry(bert_data); // todo: this only handles a single 382 entry + if (gen382) + parse_382_data(gen382, bert_data->data_length); + + raw = ptr_raw_from_bert_entry(bert_data); + if (raw) + printk(0, "todo: dump raw data\n"); + + offset += bert_entry_size(bert_data); + bert_data = (acpi_generic_error_status_t *)((u8 *)bert_data + offset); + } +} diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 21d203c..25cfee9 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -49,10 +49,17 @@ printk(BIOS_WARNING, "Failed to finalize all cores\n"); } +void parse_bert_region(void); // todo: remove me + static void soc_finalize(void *unused) { finalize_cores(); + /* In the event the region got misplaced and SMM_LOCKed, this is a + * good place to see that. + */ + parse_bert_region(); + post_code(POST_OS_BOOT); } -- To view, visit https://review.coreboot.org/28480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8ecf920499a662db34a332e9df05e4ee2383b6d4 Gerrit-Change-Number: 28480 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: amd/stoneyridge: Construct ACPI BERT table
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28478 Change subject: amd/stoneyridge: Construct ACPI BERT table ...................................................................... amd/stoneyridge: Construct ACPI BERT table Add a Boot Error Record Table to the ACPI information. Avoid a driver error message by skipping the table altogether when no errors are found, or support isn't built in. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/28478/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c78ca7c..912daa0 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -33,6 +33,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <agesa_headers.h> +#include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> @@ -40,6 +41,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <arch/bert_storage.h> static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) @@ -228,6 +230,7 @@ acpi_header_t *alib; acpi_header_t *ivrs; acpi_hest_t *hest; + acpi_bert_t *bert; /* HEST */ current = ALIGN(current, 8); @@ -236,6 +239,26 @@ acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; + /* BERT */ + if (IS_ENABLED(CONFIG_ACPI_BERT) && bert_errors_present()) { + /* Skip the table if no errors are present. ACPI driver reports + * a table with a 0-length region: + * BERT: [Firmware Bug]: table invalid. + */ + void *rgn; + size_t size; + bert_errors_region(&rgn, &size); + if (!rgn) { + printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); + } else { + current = ALIGN(current, 8); + bert = (acpi_bert_t *)current; + acpi_write_bert((void *)current, (uintptr_t)rgn, size); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + } + } + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); ivrs = agesawrapper_getlateinitptr(PICK_IVRS); -- To view, visit https://review.coreboot.org/28478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128 Gerrit-Change-Number: 28478 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: WIP: amd/stoneyridge: Enable BERT table generation
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28479 Change subject: WIP: amd/stoneyridge: Enable BERT table generation ...................................................................... WIP: amd/stoneyridge: Enable BERT table generation todo: Determine whether this is more appropriate to do in the mainboard directory. It is, IMO, rather than always reserving space. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/28479/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2716c8c..a2da782 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -67,6 +67,7 @@ select SSE2 select RTC select SOC_AMD_PSP_SELECTABLE_SMU_FW + select ACPI_BERT # todo:move to mainboard, probably config VBOOT select VBOOT_SEPARATE_VERSTAGE -- To view, visit https://review.coreboot.org/28479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe Gerrit-Change-Number: 28479 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Create an MCA structure
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28476 Change subject: amd/stoneyridge: Create an MCA structure ...................................................................... amd/stoneyridge: Create an MCA structure Convert the Machine Check reporting to use a newly defined structure. This will facilitate later patches that will pass pointers to the MSR values. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/mca.c 1 file changed, 26 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28476/1 diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index b782ef3..bcaa927 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -20,6 +20,14 @@ #include <soc/northbridge.h> #include <console/console.h> +struct mca_bank { + msr_t ctl; + msr_t sts; + msr_t addr; + msr_t misc; + msr_t cmask; +}; + static const char *const mca_bank_name[] = { "Load-store unit", "Instruction fetch unit", @@ -33,45 +41,46 @@ void check_mca(void) { int i; - msr_t msr; + msr_t cap; + struct mca_bank mci; int num_banks; - msr = rdmsr(MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; + cap = rdmsr(MCG_CAP); + num_banks = cap.lo & MCA_BANKS_MASK; if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { if (i == 3) /* Reserved in Family 15h */ continue; - msr = rdmsr(MC0_STATUS + (i * 4)); - if (msr.hi || msr.lo) { + mci.sts = rdmsr(MC0_STATUS + (i * 4)); + if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", core, i, mca_bank_name[i]); printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_ADDR + (i * 4)); + i, mci.sts.hi, mci.sts.lo); + mci.addr = rdmsr(MC0_ADDR + (i * 4)); printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_MISC + (i * 4)); + i, mci.addr.hi, mci.addr.lo); + mci.misc = rdmsr(MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL + (i * 4)); + i, mci.misc.hi, mci.misc.lo); + mci.ctl = rdmsr(MC0_CTL + (i * 4)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + i); + i, mci.ctl.hi, mci.ctl.lo); + mci.cmask = rdmsr(MC0_CTL_MASK + i); printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, msr.hi, msr.lo); + i, mci.cmask.hi, mci.cmask.lo); } } } /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; + mci.sts.lo = 0; + mci.sts.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), mci.sts); } -- To view, visit https://review.coreboot.org/28476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff Gerrit-Change-Number: 28476 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: amd/stoneyridge: Relocate MCA error identification
by Marshall Dawson (Code Review) 04 Sep '18

04 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28475 Change subject: amd/stoneyridge: Relocate MCA error identification ...................................................................... amd/stoneyridge: Relocate MCA error identification Move the process of interrogating the Machine Check registers into its own file. This rearranges source code in preparation of supporting a Boot Error Record Table, which stoneyridge will use to report latent MC errors to the OS. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/cpu.h A src/soc/amd/stoneyridge/mca.c 4 files changed, 79 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28475/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index bf5724f..a8db2c2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -92,6 +92,7 @@ ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += mca.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 09543b6..43ee6a0 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -117,62 +117,6 @@ set_warm_reset_flag(); } -static const char *const mca_bank_name[] = { - "Load-store unit", - "Instruction fetch unit", - "Combined unit", - "Reserved", - "Northbridge", - "Execution unit", - "Floating point unit" -}; - -static void check_mca(void) -{ - int i; - msr_t msr; - int num_banks; - - msr = rdmsr(MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; - - if (is_warm_reset()) { - for (i = 0 ; i < num_banks ; i++) { - if (i == 3) /* Reserved in Family 15h */ - continue; - - msr = rdmsr(MC0_STATUS + (i * 4)); - if (msr.hi || msr.lo) { - int core = cpuid_ebx(1) >> 24; - - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, mca_bank_name[i]); - - printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_ADDR + (i * 4)); - printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_MISC + (i * 4)); - printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL + (i * 4)); - printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + i); - printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, msr.hi, msr.lo); - } - } - } - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0 ; i < num_banks ; i++) - wrmsr(MC0_STATUS + (i * 4), msr); -} - static void model_15_init(struct device *dev) { check_mca(); diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index 3d230c3..934a9f2 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -30,5 +30,6 @@ #define SOC_EARLY_VMTRR_TEMPRAM 3 void stoney_init_cpus(struct device *dev); +void check_mca(void); #endif /* __STONEYRIDGE_CPU_H__ */ diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c new file mode 100644 index 0000000..b782ef3 --- /dev/null +++ b/src/soc/amd/stoneyridge/mca.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/msr.h> +#include <arch/acpi.h> +#include <cpu/amd/amdfam15.h> +#include <soc/cpu.h> +#include <soc/northbridge.h> +#include <console/console.h> + +static const char *const mca_bank_name[] = { + "Load-store unit", + "Instruction fetch unit", + "Combined unit", + "Reserved", + "Northbridge", + "Execution unit", + "Floating point unit" +}; + +void check_mca(void) +{ + int i; + msr_t msr; + int num_banks; + + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; + + if (is_warm_reset()) { + for (i = 0 ; i < num_banks ; i++) { + if (i == 3) /* Reserved in Family 15h */ + continue; + + msr = rdmsr(MC0_STATUS + (i * 4)); + if (msr.hi || msr.lo) { + int core = cpuid_ebx(1) >> 24; + + printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", + core, i, mca_bank_name[i]); + + printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_ADDR + (i * 4)); + printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_MISC + (i * 4)); + printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_CTL + (i * 4)); + printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_CTL_MASK + i); + printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", + i, msr.hi, msr.lo); + } + } + } + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0 ; i < num_banks ; i++) + wrmsr(MC0_STATUS + (i * 4), msr); +} -- To view, visit https://review.coreboot.org/28475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64 Gerrit-Change-Number: 28475 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit September 2018