coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86: Add BERT region support functions
by Martin Roth (Code Review) 06 Sep '18

06 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28470 ) Change subject: arch/x86: Add BERT region support functions ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/28470/2/src/arch/x86/acpi_bert_storage.c File src/arch/x86/acpi_bert_storage.c: https://review.coreboot.org/#/c/28470/2/src/arch/x86/acpi_bert_storage.c@350 PS2, Line 350: 3 is this CPER_IA32X64_CTX_64BIT_EX? https://review.coreboot.org/#/c/28470/2/src/arch/x86/acpi_bert_storage.c@399 PS2, Line 399: cpuid_eax use "struct cpuid_result" and cpuid() instead of calling cpuid 4 times? https://review.coreboot.org/#/c/28470/2/src/arch/x86/acpi_bert_storage.c@519 PS2, Line 519: *start = NULL; Add a printf stating that the weak function was called and that a full implementation must be added? printk(BIOS_ERR, "Error: %s not implemented. BERT region generation disabled", __func__); https://review.coreboot.org/#/c/28470/2/src/arch/x86/include/arch/bert_stor… File src/arch/x86/include/arch/bert_storage.h: https://review.coreboot.org/#/c/28470/2/src/arch/x86/include/arch/bert_stor… PS2, Line 88: acpi_hest_generic_data_nth Why make this inline? -- To view, visit https://review.coreboot.org/28470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9 Gerrit-Change-Number: 28470 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 06 Sep 2018 01:40:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: x86/acpi: Add APEI definitions
by Martin Roth (Code Review) 06 Sep '18

06 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28469 ) Change subject: x86/acpi: Add APEI definitions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Gerrit-Change-Number: 28469 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Sep 2018 00:47:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/include: Add CPER definitions
by Martin Roth (Code Review) 06 Sep '18

06 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28468 ) Change subject: src/include: Add CPER definitions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Gerrit-Change-Number: 28468 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Sep 2018 00:46:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nocturne: Do not send eSPI interrupt for MKBP events
by Enrico Granata (Code Review) 06 Sep '18

06 Sep '18

Enrico Granata has uploaded this change for review. ( https://review.coreboot.org/28524 Change subject: nocturne: Do not send eSPI interrupt for MKBP events ...................................................................... nocturne: Do not send eSPI interrupt for MKBP events On Nocturne, we plan to use the GPIO IRQ as the means of communicating MKBP event information from the EC. On such hardware, do not send the MKBP eSPI interrupt. Change-Id: I7e7f5def9dbc170913d67dca7c7cc12da8c4efbb Signed-off-by: Enrico Granata <egranata(a)chromium.org> --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28524/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 453a6d7..4b77604 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -362,8 +362,10 @@ // MKBP interrupt. Method (_Q1B, 0, NotSerialized) { +#ifndef EC_NO_MKBP_SYNC_NOTIFY Store ("EC: MKBP", Debug) Notify (CREC, 0x80) +#endif } // TABLET mode switch Event diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h index 7e16801..be81fec 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h @@ -79,4 +79,6 @@ #define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ #define EC_ENABLE_CBAS_DEVICE /* Enable "Base Attached Switch" device */ +#define EC_NO_MKBP_SYNC_NOTIFY /* Do not send eSPI interrupt for MKBP event */ + #endif /* __MAINBOARD_EC_H__ */ -- To view, visit https://review.coreboot.org/28524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e7f5def9dbc170913d67dca7c7cc12da8c4efbb Gerrit-Change-Number: 28524 Gerrit-PatchSet: 1 Gerrit-Owner: Enrico Granata <egranata(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
by Nick Vaccaro (Code Review) 06 Sep '18

06 Sep '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/28424 ) Change subject: soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree ...................................................................... Patch Set 2: Is there an associated CL for fsp code to add support for CmdTriStateDis that would be needed to support this change? -- To view, visit https://review.coreboot.org/28424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Gerrit-Change-Number: 28424 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Sep 2018 23:56:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: NOT_FOR_MERGE: Add code to dump BERT region contents
by build bot (Jenkins) (Code Review) 06 Sep '18

06 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28480 ) Change subject: NOT_FOR_MERGE: Add code to dump BERT region contents ...................................................................... Patch Set 2: (150 comments) https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c File src/soc/amd/stoneyridge/bertdump.c: https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 46: static const char *acpi_severity[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 65: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 68: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 71: check & X86_PROC_CHK_OPERATION_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 74: check & X86_PROC_CHK_LEVEL_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 76: printk(0, " e Context Corrupt = %x %s\n", !!(check & X86_PROC_CHK_CTX_CORRUPT), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 77: check & X86_PROC_CHK_CONTEXT_CORPT_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 79: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 80: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 82: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 83: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 85: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 86: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 88: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 89: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 92: check & X86_PROC_CHK_PART_TYPE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 94: printk(0, " e Time Out = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 95: check & X86_PROC_CHK_TIMEOUT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 98: check & X86_PROC_CHK_ADDR_SPACE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 104: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 107: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 109: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_MS_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 110: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 112: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_MS_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 113: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 115: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_MS_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 116: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 118: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_MS_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 119: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 122: static const char *check_guid_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 147: printk(0, " ___ CPER IA32/x64 Processor Error (Check) Information @0x%p - 0x%p (size 0x%zx) ___\n", err, err + 1, sizeof(*err)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 148: printk(0, " e Structure Type GUID = %s\n", check_guid_name(err->type)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 151: printk(0, " e Validation Bits = %llx\n", err->validation); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 153: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 154: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 155: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 156: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 158: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 159: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 160: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 161: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 163: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 164: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 165: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 166: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 167: | X86_PROC_CHK_PART_TYPE_VALID | X86_PROC_CHK_TIMEOUT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 168: | X86_PROC_CHK_ADDR_SPACE_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 170: x86_mschkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 171: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 172: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 179: static const char *context_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 210: printk(0, " ___ CPER IA32/x64 Processor Context Information @0x%p - 0x%p (size 0x%zx) ___\n", ctx, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 211: (u8 *)ctx + ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 212: ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 213: printk(0, " t Context Type = %x %s\n", ctx->type, context_name(ctx->type)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 214: printk(0, " t Array Size = %x\n", ctx->array_size); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 216: printk(0, " t MM Address = %llx\n", ctx->mmap_addr); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 224: printk(0, " t %08x_%08x\n", (u32)(*(array + i) >> 32), (u32)*(array + i)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 233: int errs = (ia32->validation & I32X64SEC_VALID_ERRNUM_MASK) >> I32X64SEC_VALID_ERRNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 234: int ctxs = (ia32->validation & I32X64SEC_VALID_CTXNUM_MASK) >> I32X64SEC_VALID_CTXNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 236: printk(0, " ___ CPER IA32/x64 Processor Error @0x%p sizeof(proc error section struct) is 0x%zx/%zd) ___\n", ia32, sizeof(*ia32), sizeof(*ia32)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 237: printk(0, " x Validation Bits = %llx\n", ia32->validation); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 240: printk(0, " x Processor APIC ID = %llx %s\n", ia32->apicid, ia32->validation & I32X64SEC_VALID_LAPIC ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 241: printk(0, " x Processor CPUID = EAX = %x %s\n", (u32)ia32->cpuid[0], ia32->validation & I32X64SEC_VALID_CPUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 242: printk(0, " x EBX = %x\n", (u32)ia32->cpuid[1]); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 243: printk(0, " x ECX = %x\n", (u32)ia32->cpuid[2]); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 244: printk(0, " x EDX = %x\n", (u32)ia32->cpuid[3]); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 248: adder += parse_x86_error_info((cper_ia32x64_proc_error_info_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 251: adder += parse_x86_context_info((cper_ia32x64_context_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 256: static size_t parse_cper_structure_generic(cper_proc_generic_error_section_t *gen) line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 258: printk(0, " ___ CPER Generic Processor Error @0x%p sizeof(generic error struct) is 0x%zx/%zd\n", gen, sizeof(*gen), sizeof(*gen)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 259: printk(0, " c Validation Bits = %llx\n", gen->validation); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 260: printk(0, " c Processor Type = %x %s\n", gen->proc_type, gen->validation & GENPROC_VALID_PROC_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 261: printk(0, " c Processor ISA = %x %s\n", gen->proc_isa, gen->validation & GENPROC_VALID_PROC_ISA ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 262: printk(0, " c Processor Error Type = %x %s\n", gen->error_type, gen->validation & GENPROC_VALID_PROC_ERR_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 263: printk(0, " c Operation = %x %s\n", gen->operation, gen->validation & GENPROC_VALID_OPERATION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 264: printk(0, " c Flags = %x %s\n", gen->flags, gen->validation & GENPROC_VALID_FLAGS ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 265: printk(0, " c Level = %x %s\n", gen->level, gen->validation & GENPROC_VALID_LEVEL ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 266: printk(0, " c CPU Version Info = %llx %s\n", gen->cpu_version, gen->validation & GENPROC_VALID_CPU_VERSION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 267: printk(0, " c CPU Brand String = %s %s\n", gen->cpu_brand_string, gen->validation & GENPROC_VALID_CPU_BRAND ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 268: printk(0, " c Processor ID = %llx %s\n", gen->proc_id, gen->validation & GENPROC_VALID_CPU_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 269: printk(0, " c Target Address = %llx %s\n", gen->target_addr, gen->validation & GENPROC_VALID_TGT_ADDR ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 270: printk(0, " c Requestor Identifier = %llx %s\n", gen->requestor_id, gen->validation & GENPROC_VALID_REQR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 271: printk(0, " c Responder Identifier = %llx %s\n", gen->responder_id, gen->validation & GENPROC_VALID_RSPR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 272: printk(0, " c Instruction IP = %llx %s\n", gen->instruction_ip, gen->validation & GENPROC_VALID_INSTR_IP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 296: return sizeof(acpi_hest_generic_data_v300_t) + entry->data_length; line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 301: static const char *guids382[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 319: if(!guidcmp(&guid, &CPER_SEC_PROC_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 321: if(!guidcmp(&guid, &CPER_SEC_PROC_IA32X64_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 323: if(!guidcmp(&guid, &CPER_SEC_PROC_ARM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 325: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 327: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM2_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 329: if(!guidcmp(&guid, &CPER_SEC_PCIE_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 331: if(!guidcmp(&guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 333: if(!guidcmp(&guid, &CPER_SEC_PCI_X_BUS_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 335: if(!guidcmp(&guid, &CPER_SEC_PCI_DEV_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 337: if(!guidcmp(&guid, &CPER_SEC_DMAR_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 339: if(!guidcmp(&guid, &CPER_SEC_DMAR_VT_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 341: if(!guidcmp(&guid, &CPER_SEC_DMAR_IOMMU_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 351: printk(0, " ___ 382 found @0x%p sizeof(%s) = 0x%zx/%zd ___\n", entry, entry->revision == 0x300 ? "v3" : "old-type", line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 352: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t), line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 353: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 354: printk(0, " 3 Section Type GUID = %s\n", guid382_name(entry->section_type)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 357: printk(0, " 3 Severity = %x: %s\n", entry->error_severity, acpi_sev(entry->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 358: printk(0, " 3 Revision = %x\n", entry->revision); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 359: printk(0, " 3 Validation = %x\n", entry->validation_bits); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 361: printk(0, " 3 Error Data Length = %x\n", entry->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 362: printk(0, " 3 FRU ID = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 363: printk(0, " 3 FRU text = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID_TEXT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 365: /* I can cheat on x300 because I know only diff is timestamp */ line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 370: entry->timestamp.hour, entry->timestamp.min, entry->timestamp.sec, line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 371: entry->validation_bits & ACPI_GENERROR_VALID_TIMESTAMP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 375: /* each table-382 entry should contain 0 or 1 cper structure at its end */ line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 378: parse_cper_structure((void *)(entry + 1), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 380: parse_cper_structure((void *)((u8 *)entry + sizeof(acpi_hest_generic_data_t)), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 384: entry = (acpi_hest_generic_data_v300_t *)((u8 *)entry + entry382_size(entry)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 400: static acpi_hest_generic_data_v300_t *ptr382_from_bert_entry(acpi_generic_error_status_t *bert_data) line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 403: return (acpi_hest_generic_data_v300_t *)((u8 *)bert_data + sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 429: printk(0, "***** BERT storage at 0x%p - 0x%p (%zd) *****\n", bert_base, (u8 *)bert_base + size, size); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 431: while(offset < size) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 432: entries = (bert_data->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) >> GENERIC_ERR_STS_ENTRY_COUNT_SHIFT; line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 433: printk(0, " ___ BERT entry @0x%p - (sizeof(status)=0x%zx/%zd) ___\n", bert_data, sizeof(*bert_data), sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 434: printk(0, " b Block Status = %x\n", bert_data->block_status); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 436: bert_data->block_status & BIT(0) ? " uncorrectable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 437: bert_data->block_status & BIT(1) ? " correctable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 438: bert_data->block_status & BIT(2) ? " mult-uncorrected" : "", line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 439: bert_data->block_status & BIT(3) ? " mult-corrected" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 441: printk(0, " b Raw Data Offset = %x\n", bert_data->raw_data_offset); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 442: printk(0, " b Raw Data Length = %x\n", bert_data->raw_data_length); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 443: printk(0, " b Data Length = %x\n", bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 444: printk(0, " b Error Severity = %x: %s\n", bert_data->error_severity, acpi_sev(bert_data->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 445: if (bert_data->data_length && bert_data->data_length < sizeof(acpi_hest_generic_data_v300_t)) line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 447: bert_data->data_length, sizeof(acpi_hest_generic_data_v300_t)); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 448: if (bert_data->raw_data_length && bert_data->raw_data_offset < sizeof(*bert_data) + bert_data->data_length) line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 450: bert_data->raw_data_offset, sizeof(*bert_data), bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 453: /* can have zero or more data entries, of type 382 and/or of raw */ line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 454: gen382 = ptr382_from_bert_entry(bert_data); // todo: this only handles a single 382 entry line over 80 characters https://review.coreboot.org/#/c/28480/2/src/soc/amd/stoneyridge/bertdump.c@… PS2, Line 463: bert_data = (acpi_generic_error_status_t *)((u8 *)bert_data + offset); line over 80 characters -- To view, visit https://review.coreboot.org/28480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ecf920499a662db34a332e9df05e4ee2383b6d4 Gerrit-Change-Number: 28480 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Sep 2018 22:39:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/include: Add CPER definitions
by Marshall Dawson (Code Review) 06 Sep '18

06 Sep '18

Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28468 to look at the new patch set (#2). Change subject: src/include: Add CPER definitions ...................................................................... src/include: Add CPER definitions Add definitions from the UEFI appendix on Common Platform Error Record (appx. N in revision 2.7-A). The structures and fields defined are the minimum required for generating ACPI Boot Error Record data in a subsequent patch. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/include/cper.h 1 file changed, 507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28468/2 -- To view, visit https://review.coreboot.org/28468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Gerrit-Change-Number: 28468 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: x86/acpi: Add APEI definitions
by Marshall Dawson (Code Review) 06 Sep '18

06 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28469 to look at the new patch set (#2). Change subject: x86/acpi: Add APEI definitions ...................................................................... x86/acpi: Add APEI definitions Add ACPI Platform Error Interfaces definitions that will be used for building a BERT table region in a subsequent patch. Two tables are defined: the Generic Error Status Block, Generic Error Data Entry. For reference, see the ACPI specification 6.2-A tables 381 and 382. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28469/2 -- To view, visit https://review.coreboot.org/28469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Gerrit-Change-Number: 28469 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: arch/x86: Add BERT region support functions
by Marshall Dawson (Code Review) 06 Sep '18

06 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28470 to look at the new patch set (#2). Change subject: arch/x86: Add BERT region support functions ...................................................................... arch/x86: Add BERT region support functions Add code for generating the region pointed to in an ACPI Boot Error Record Table. The BERT region must be reported as Reserved to the OSPM, so this code calls out to a system-specific region locator. cbmem is reported as type 16 and is not usable for the BERT region. Events reported via BERT are Generic Error Data, and are constructed as follows (see ACPI and UEFI specs for reference): * Each event begins with a Generic Error Status Block, which may contain zero or more Generic Data Entries * Each Generic Data Entry is identifiable by its Section Type field, and the data structures associated are also in the UEFI spec. * The GUIDs are listed in the Section Type field of the CPER Section Descriptor structure. BERT doesn't use this structure but simply uses its GUIDs. * Data structures used in the Generic Data Entry are named as Error Sections in the UEFI spec. * Some sections may optionally include a variable number of additional structures, e.g. an IA32/X64 processor error can report error information as well as machine contexts. It is worth noting that the Linux kernel (as of v4.4) does not attempt to parse IA32/X64 sections, and opts to hexdump them instead. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/Kconfig M src/arch/x86/Makefile.inc A src/arch/x86/acpi_bert_storage.c A src/arch/x86/include/arch/bert_storage.h 4 files changed, 716 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28470/2 -- To view, visit https://review.coreboot.org/28470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9 Gerrit-Change-Number: 28470 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: x86/acpi: Add BERT table
by Marshall Dawson (Code Review) 06 Sep '18

06 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28472 to look at the new patch set (#2). Change subject: x86/acpi: Add BERT table ...................................................................... x86/acpi: Add BERT table Create a structure for the Boot Error Record Table, and a generic table generator function. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28472/2 -- To view, visit https://review.coreboot.org/28472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538 Gerrit-Change-Number: 28472 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2018