Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
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Patch Set 29:

(2 comments)

https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@164
PS29, Line 164: 	if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
line over 80 characters


https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@189
PS29, Line 189: 	
trailing whitespace



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Gerrit-Change-Number: 27972
Gerrit-PatchSet: 29
Gerrit-Owner: Xiang Wang <[e-mail]>
Gerrit-Reviewer: Jonathan Neuschäfer <[e-mail]>
Gerrit-Reviewer: Paul Menzel <[e-mail]>
Gerrit-Reviewer: Philipp Hug <[e-mail]>
Gerrit-Reviewer: Ronald G. Minnich <[e-mail]>
Gerrit-Reviewer: Shawn Chang <[e-mail]>
Gerrit-Reviewer: Xiang Wang <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Reviewer: ron minnich (1001188)
Gerrit-Comment-Date: Sat, 01 Sep 2018 15:12:28 +0000
Gerrit-HasComments: Yes
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