[coreboot-gerrit] Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
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Patch Set 29:

(2 comments)

https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@164
PS29, Line 164: 	if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
line over 80 characters

https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@189
PS29, Line 189: 	
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