
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 29: (2 comments) https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@164 PS29, Line 164: if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) { line over 80 characters https://review.coreboot.org/#/c/27972/29/src/arch/riscv/misaligend.c@189 PS29, Line 189: trailing whitespace -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 29 Gerrit-Owner: Xiang Wang <wxjstz@126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich@gmail.com> Gerrit-Reviewer: Shawn Chang <citypw@gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz@126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Sat, 01 Sep 2018 15:12:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No