Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28743 )
Change subject: soc/intel/cannonlake: Add ACPI entry for LAN
......................................................................
soc/intel/cannonlake: Add ACPI entry for LAN
Add ACPI DSDT entry for integrated Gigabit LAN controller.
Change-Id: I15bf1d4065894531871380b3318f553b637f4a97
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Reviewed-on: https://review.coreboot.org/28743
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
A src/soc/intel/cannonlake/acpi/pch_glan.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
2 files changed, 33 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Duncan Laurie: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/cannonlake/acpi/pch_glan.asl
new file mode 100644
index 0000000..260dd44
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/pch_glan.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017-2108 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Gigabit Ethernet Controller 0:1f.6 */
+
+Device (GLAN)
+{
+ Name (_ADR, 0x001f0006)
+
+ Name (_S0W, 3)
+
+ Name (_PRW, Package() {GPE0_PME_B0, 4})
+
+ Method (_DSW, 3) {}
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index e4f29b6..6fac398 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
* (Written by Bora Guvendik <bora.guvendik(a)intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -48,3 +48,6 @@
/* CNVi */
#include "cnvi.asl"
+
+/* GBe 0:1f.6 */
+#include "pch_glan.asl"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I15bf1d4065894531871380b3318f553b637f4a97
Gerrit-Change-Number: 28743
Gerrit-PatchSet: 2
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27616 )
Change subject: payloads/tianocore: ignore whitespace change when applying patches
......................................................................
payloads/tianocore: ignore whitespace change when applying patches
This change is required to apply patch
06_CorebootPayloadPkg_keep_cb_table since conflict in white space
between patch and target file in edk2 makes patch rejected while
building under coreboot-sdk:1.52.
Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5
Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com>
Reviewed-on: https://review.coreboot.org/27616
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-by: Martin Roth <martinroth(a)google.com>
---
M payloads/external/tianocore/Makefile
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
Patrick Rudolph: Looks good to me, but someone else must approve
diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
index c280fe1b..747ee47 100644
--- a/payloads/external/tianocore/Makefile
+++ b/payloads/external/tianocore/Makefile
@@ -69,7 +69,7 @@
for patch in $(CURDIR)/patches/*.patch; do \
echo "Applying $$patch"; \
cd $(project_dir); \
- git am --keep-cr $$patch || \
+ git am --keep-cr --ignore-space-change $$patch || \
( echo " Error when applying patches.\n"; git am --abort; exit 1; ); \
done; \
if ! [ "$(TAG-y)" = "origin/master" ] ; then \
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5
Gerrit-Change-Number: 27616
Gerrit-PatchSet: 2
Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com>
Gerrit-Reviewer: Krystian Hebel (1002088)
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28787
Change subject: mediatek/mt8183: Add USB support
......................................................................
mediatek/mt8183: Add USB support
This patch implements SoC-specific defines of mt8183 and link the
common code to support USB.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1224cf24f92b07f3c1814f1cbfef96aafa5a992b
Signed-off-by: Jumin Li <jumin.li(a)mediatek.com>
---
M src/soc/mediatek/mt8183/Makefile.inc
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/usb.h
3 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/28787/1
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 8fece79..c5e8120 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -36,6 +36,7 @@
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += ../common/timer.c
ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+ramstage-y += ../common/usb.c
ramstage-y += ../common/wdt.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index de7eb1f..5527e6e 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -37,6 +37,8 @@
SPI3_BASE = IO_PHYS + 0x01013000,
SPI4_BASE = IO_PHYS + 0x01014000,
SPI5_BASE = IO_PHYS + 0x01015000,
+ SSUSB_MAC_BASE = IO_PHYS + 0x01200000,
+ SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00,
IOCFG_RT_BASE = IO_PHYS + 0x01C50000,
IOCFG_RM_BASE = IO_PHYS + 0x01D20000,
IOCFG_RB_BASE = IO_PHYS + 0x01D30000,
@@ -45,6 +47,7 @@
IOCFG_BL_BASE = IO_PHYS + 0x01E90000,
IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
+ SSUSB_SIF_BASE = IO_PHYS + 0x01F40300,
SMI_BASE = IO_PHYS + 0x04019000,
};
diff --git a/src/soc/mediatek/mt8183/include/soc/usb.h b/src/soc/mediatek/mt8183/include/soc/usb.h
new file mode 100644
index 0000000..505958f
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/usb.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_USB_H
+#define SOC_MEDIATEK_MT8183_USB_H
+
+#include <soc/usb_common.h>
+
+struct ssusb_sif_port {
+ struct sif_u2_phy_com u2phy;
+ u32 reserved0[64*5];
+ struct sif_u3phyd u3phyd;
+ u32 reserved1[64];
+ struct sif_u3phya u3phya;
+ struct sif_u3phya_da u3phya_da;
+ u32 reserved2[64 * 3];
+};
+check_member(ssusb_sif_port, u3phyd, 0x600);
+check_member(ssusb_sif_port, u3phya, 0x800);
+check_member(ssusb_sif_port, u3phya_da, 0x900);
+check_member(ssusb_sif_port, reserved2, 0xa00);
+_Static_assert(sizeof(struct ssusb_sif_port) == 0xD00,
+ "ssusb_sif_port size is wrong!");
+
+#define USB_PORT_NUMBER 1
+
+#endif
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I1224cf24f92b07f3c1814f1cbfef96aafa5a992b
Gerrit-Change-Number: 28787
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/28784 )
Change subject: cpu/intel/microcode: Replace numbers with macros
......................................................................
Patch Set 1:
Can you please provide a more meaningful commit message. At least mention that "numbers" in this case means MSR addresses.
--
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Gerrit-MessageType: comment
Gerrit-Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a
Gerrit-Change-Number: 28784
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Comment-Date: Fri, 28 Sep 2018 08:18:46 +0000
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