coreboot-gerrit September 2018

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Change in coreboot[master]: soc/intel/cannonlake: Add ACPI entry for LAN
by Patrick Georgi (Code Review) 28 Sep '18

28 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28743 ) Change subject: soc/intel/cannonlake: Add ACPI entry for LAN ...................................................................... soc/intel/cannonlake: Add ACPI entry for LAN Add ACPI DSDT entry for integrated Gigabit LAN controller. Change-Id: I15bf1d4065894531871380b3318f553b637f4a97 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/28743 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/intel/cannonlake/acpi/pch_glan.asl M src/soc/intel/cannonlake/acpi/southbridge.asl 2 files changed, 33 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/cannonlake/acpi/pch_glan.asl new file mode 100644 index 0000000..260dd44 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/pch_glan.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017-2108 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Gigabit Ethernet Controller 0:1f.6 */ + +Device (GLAN) +{ + Name (_ADR, 0x001f0006) + + Name (_S0W, 3) + + Name (_PRW, Package() {GPE0_PME_B0, 4}) + + Method (_DSW, 3) {} +} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index e4f29b6..6fac398 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. + * Copyright (C) 2017-2018 Intel Corp. * (Written by Bora Guvendik <bora.guvendik(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -48,3 +48,6 @@ /* CNVi */ #include "cnvi.asl" + +/* GBe 0:1f.6 */ +#include "pch_glan.asl" -- To view, visit https://review.coreboot.org/28743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I15bf1d4065894531871380b3318f553b637f4a97 Gerrit-Change-Number: 28743 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/poppy/variants/rammus: Modify VR setting
by Patrick Georgi (Code Review) 28 Sep '18

28 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28695 ) Change subject: mainboard/google/poppy/variants/rammus: Modify VR setting ...................................................................... mainboard/google/poppy/variants/rammus: Modify VR setting We refer to Intel Doc#594883. The recommended Ac/Dc loadline values are as below: # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| AcLoadline | 14.4 | 4.2 | 5.7 | 4.47 | #| DcLoadline | 14.0 | 4.17 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ BUG=b:112167318 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I2d83d835ec841ac4cc811a0a69f74d203d5ea173 Signed-off-by: statham_chu <statham_chu(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28695 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/rammus/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 7b851ac..b750cb8 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -83,8 +83,8 @@ #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | - #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | + #| AcLoadline | 14.4 | 4.2 | 5.7 | 4.47 | + #| DcLoadline | 14.0 | 4.17 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, @@ -96,8 +96,8 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 1500, - .dc_loadline = 1430, + .ac_loadline = 1440, + .dc_loadline = 1400, }" register "domain_vr_config[VR_IA_CORE]" = "{ @@ -110,8 +110,8 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 570, - .dc_loadline = 483, + .ac_loadline = 420, + .dc_loadline = 417, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ @@ -124,7 +124,7 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 550, + .ac_loadline = 570, .dc_loadline = 420, }" @@ -138,8 +138,8 @@ .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, - .ac_loadline = 550, - .dc_loadline = 420, + .ac_loadline = 447, + .dc_loadline = 430, }" # Enable Root port 1. -- To view, visit https://review.coreboot.org/28695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I2d83d835ec841ac4cc811a0a69f74d203d5ea173 Gerrit-Change-Number: 28695 Gerrit-PatchSet: 6 Gerrit-Owner: Statham Chu <statham_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Statham Chu <statham_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-CC: Jerry Chou <jerry_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com>

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Change in coreboot[master]: payloads/tianocore: ignore whitespace change when applying patches
by Patrick Georgi (Code Review) 28 Sep '18

28 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27616 ) Change subject: payloads/tianocore: ignore whitespace change when applying patches ...................................................................... payloads/tianocore: ignore whitespace change when applying patches This change is required to apply patch 06_CorebootPayloadPkg_keep_cb_table since conflict in white space between patch and target file in edk2 makes patch rejected while building under coreboot-sdk:1.52. Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5 Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/27616 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index c280fe1b..747ee47 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -69,7 +69,7 @@ for patch in $(CURDIR)/patches/*.patch; do \ echo "Applying $$patch"; \ cd $(project_dir); \ - git am --keep-cr $$patch || \ + git am --keep-cr --ignore-space-change $$patch || \ ( echo " Error when applying patches.\n"; git am --abort; exit 1; ); \ done; \ if ! [ "$(TAG-y)" = "origin/master" ] ; then \ -- To view, visit https://review.coreboot.org/27616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5 Gerrit-Change-Number: 27616 Gerrit-PatchSet: 2 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel (1002088) Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/kukui: configure USB
by Tristan Hsieh (Code Review) 28 Sep '18

28 Sep '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28788 Change subject: google/kukui: configure USB ...................................................................... google/kukui: configure USB configure USB BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/28788/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 9190ee7..e1d8f5f 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/usb.h> static void configure_emmc(void) { @@ -31,9 +32,15 @@ gpio_set_pull(emmc_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); } +static void configure_usb(void) +{ + setup_usb_host(); +} + static void mainboard_init(struct device *dev) { configure_emmc(); + configure_usb(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/28788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e Gerrit-Change-Number: 28788 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mediatek/mt8183: Add USB support
by Tristan Hsieh (Code Review) 28 Sep '18

28 Sep '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28787 Change subject: mediatek/mt8183: Add USB support ...................................................................... mediatek/mt8183: Add USB support This patch implements SoC-specific defines of mt8183 and link the common code to support USB. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1224cf24f92b07f3c1814f1cbfef96aafa5a992b Signed-off-by: Jumin Li <jumin.li(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/usb.h 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/28787/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 8fece79..c5e8120 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -36,6 +36,7 @@ ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index de7eb1f..5527e6e 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -37,6 +37,8 @@ SPI3_BASE = IO_PHYS + 0x01013000, SPI4_BASE = IO_PHYS + 0x01014000, SPI5_BASE = IO_PHYS + 0x01015000, + SSUSB_MAC_BASE = IO_PHYS + 0x01200000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, IOCFG_RT_BASE = IO_PHYS + 0x01C50000, IOCFG_RM_BASE = IO_PHYS + 0x01D20000, IOCFG_RB_BASE = IO_PHYS + 0x01D30000, @@ -45,6 +47,7 @@ IOCFG_BL_BASE = IO_PHYS + 0x01E90000, IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, + SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, SMI_BASE = IO_PHYS + 0x04019000, }; diff --git a/src/soc/mediatek/mt8183/include/soc/usb.h b/src/soc/mediatek/mt8183/include/soc/usb.h new file mode 100644 index 0000000..505958f --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/usb.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_USB_H +#define SOC_MEDIATEK_MT8183_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64*5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); +_Static_assert(sizeof(struct ssusb_sif_port) == 0xD00, + "ssusb_sif_port size is wrong!"); + +#define USB_PORT_NUMBER 1 + +#endif -- To view, visit https://review.coreboot.org/28787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1224cf24f92b07f3c1814f1cbfef96aafa5a992b Gerrit-Change-Number: 28787 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mediatek: Refactor USB code among similar SoCs
by Tristan Hsieh (Code Review) 28 Sep '18

28 Sep '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28786 Change subject: mediatek: Refactor USB code among similar SoCs ...................................................................... mediatek: Refactor USB code among similar SoCs Refactor USB code which will be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I06fefb4149a489be991e13ddf624082d11e31765 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/soc/mediatek/common/include/soc/usb_common.h A src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/include/soc/usb.h M src/soc/mediatek/mt8173/usb.c 5 files changed, 351 insertions(+), 293 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28786/1 diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h new file mode 100644 index 0000000..8a36c6a --- /dev/null +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_USB_COMMON_H +#define SOC_MEDIATEK_USB_COMMON_H + +#include <stddef.h> + +/* ip_pw_ctrl0 */ +#define CTRL0_IP_SW_RST (0x1 << 0) + +/* ip_pw_ctrl1 */ +#define CTRL1_IP_HOST_PDN (0x1 << 0) + +/* ip_pw_sts1 */ +#define STS1_U3_MAC_RST (0x1 << 16) +#define STS1_SYS125_RST (0x1 << 10) +#define STS1_REF_RST (0x1 << 8) +#define STS1_SYSPLL_STABLE (0x1 << 0) + +/* ip_pw_sts2 */ +#define STS2_U2_MAC_RST (0x1 << 0) + +/* ip_xhci_cap */ +#define CAP_U3_PORT_NUM(p) ((p) & 0xff) +#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) + +/* u3_ctrl_p */ +#define CTRL_U3_PORT_HOST_SEL (0x1 << 2) +#define CTRL_U3_PORT_PDN (0x1 << 1) +#define CTRL_U3_PORT_DIS (0x1 << 0) + +/* u2_ctrl_p */ +#define CTRL_U2_PORT_HOST_SEL (0x1 << 2) +#define CTRL_U2_PORT_PDN (0x1 << 1) +#define CTRL_U2_PORT_DIS (0x1 << 0) + +struct ssusb_ippc_regs { + u32 ip_pw_ctr0; + u32 ip_pw_ctr1; + u32 ip_pw_ctr2; + u32 ip_pw_ctr3; + u32 ip_pw_sts1; + u32 ip_pw_sts2; + u32 reserved0[3]; + u32 ip_xhci_cap; + u32 reserved1[2]; + u64 u3_ctrl_p[4]; + u64 u2_ctrl_p[6]; +}; + +/* U2PHY_COM USBPHYACR5 */ +#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12) +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) +#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11) + +/* U2PHY_COM USBPHYACR6 */ +#define PA6_RG_U2_ISO_EN (0x1 << 31) +#define PA6_RG_U2_BC11_SW_EN (0x1 << 23) +#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) +#define PA6_RG_U2_SQTH (0xf << 0) +#define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0) + +/* U2PHY_COM U2PHYACR4 */ +#define P2C_RG_USB20_GPIO_CTL (0x1 << 9) +#define P2C_USB20_GPIO_MODE (0x1 << 8) +#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) + +/* U2PHY_COM U2PHYDTM0 */ +#define P2C_FORCE_UART_EN (0x1 << 26) +#define P2C_FORCE_DATAIN (0x1 << 23) +#define P2C_FORCE_DM_PULLDOWN (0x1 << 21) +#define P2C_FORCE_DP_PULLDOWN (0x1 << 20) +#define P2C_FORCE_XCVRSEL (0x1 << 19) +#define P2C_FORCE_SUSPENDM (0x1 << 18) +#define P2C_FORCE_TERMSEL (0x1 << 17) +#define P2C_RG_DATAIN (0xf << 10) +#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) +#define P2C_RG_DMPULLDOWN (0x1 << 7) +#define P2C_RG_DPPULLDOWN (0x1 << 6) +#define P2C_RG_XCVRSEL (0x3 << 4) +#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) +#define P2C_RG_SUSPENDM (0x1 << 3) +#define P2C_RG_TERMSEL (0x1 << 2) +#define P2C_DTM0_PART_MASK \ + (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ + P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ + P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ + P2C_RG_TERMSEL) + +/* U2PHY_COM U2PHYDTM1 */ +#define P2C_RG_UART_EN (0x1 << 16) +#define P2C_RG_VBUSVALID (0x1 << 5) +#define P2C_RG_SESSEND (0x1 << 4) +#define P2C_RG_AVALID (0x1 << 2) + +/* U3PHYA PHYA_REG0 */ +#define P3A_RG_U3_VUSB10_ON (1 << 5) + +/* U3PHYA PHYA_REG6 */ +#define P3A_RG_TX_EIDLE_CM (0xf << 28) +#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) + +/* U3PHYA PHYA_REG9 */ +#define P3A_RG_RX_DAC_MUX (0x1f << 1) +#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) + +/* U3PHYA_DA REG0 */ +#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10) +#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) + +/* U3PHYD CDR1 */ +#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24) +#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) +#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8) +#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) + +struct sif_u2_phy_com { + u32 reserved0[5]; + u32 usbphyacr5; + u32 usbphyacr6; + u32 u2phyacr3; + u32 u2phyacr4; + u32 reserved1[17]; + u32 u2phydtm0; + u32 u2phydtm1; + u32 reserved2[36]; /* 0x70 - 0xff */ +}; +check_member(sif_u2_phy_com, u2phydtm0, 0x68); + +struct sif_u3phyd { + u32 reserved0[23]; + u32 phyd_cdr1; + u32 reserved1[40]; +}; + +struct sif_u3phya { + u32 phya_reg0; + u32 reserved0[5]; + u32 phya_reg6; + u32 reserved1[2]; + u32 phya_reg9; + u32 reserved2[54]; +}; + +struct sif_u3phya_da { + u32 reg0; + u32 reserved[63]; +}; + +/* + * This is defined as weak no-ops that can be overridden by legacy SOCs. Some + * legacy SOCs need specific settings before init USB. And we expect future + * SOCs will not need it. + */ +void mtk_usb_prepare(void); + +void setup_usb_host(void); + +#endif diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c new file mode 100644 index 0000000..ceeea19 --- /dev/null +++ b/src/soc/mediatek/common/usb.c @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <compiler.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/usb.h> +#include <timer.h> + +#define USBTAG "[SSUSB] " +#define u3p_msg(fmt, arg...) printk(BIOS_INFO, USBTAG fmt, ##arg) +#define u3p_err(fmt, arg...) printk(BIOS_ERR, USBTAG fmt, ##arg) + +static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE); +static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE); + +static void phy_index_power_on(int index) +{ + struct ssusb_sif_port *phy = phy_ports + index; + + if (!index) { + /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ + setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); + /* power domain iso disable */ + clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); + } + /* switch to USB function. (system register, force ip into usb mode) */ + clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); + clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); + if (!index) + clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); + + /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ + clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | + P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); + + /* DP/DM BC1.1 path Disable */ + clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); + /* improve Rx sensitivity */ + clrsetbits_le32(&phy->u2phy.usbphyacr6, + PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); + /* OTG Enable */ + setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); + + clrsetbits_le32(&phy->u3phya_da.reg0, + P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); + + clrsetbits_le32(&phy->u3phya.phya_reg9, + P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); + + if (!index) { + /* disable Change 100uA current from SSUSB */ + clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); + } + + clrsetbits_le32(&phy->u3phya.phya_reg6, + P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); + + clrsetbits_le32(&phy->u3phyd.phyd_cdr1, + P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc)); + clrsetbits_le32(&phy->u3phyd.phyd_cdr1, + P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3)); + + clrsetbits_le32(&phy->u2phy.u2phydtm1, + P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); + + /* USB 2.0 slew rate calibration */ + clrsetbits_le32(&phy->u2phy.usbphyacr5, + PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); +} + +static void u3phy_power_on(void) +{ + for (size_t i = 0; i < USB_PORT_NUMBER; i++) + phy_index_power_on(i); +} + +static int check_ip_clk_status(void) +{ + int u3_port_num; + u32 check_bits; + u32 sts1, sts2; + struct stopwatch sw; + + u3_port_num = CAP_U3_PORT_NUM(read32(&ippc_regs->ip_xhci_cap)); + + check_bits = STS1_SYSPLL_STABLE | STS1_REF_RST | STS1_SYS125_RST; + check_bits |= (u3_port_num ? STS1_U3_MAC_RST : 0); + + stopwatch_init_usecs_expire(&sw, 50000); + + do { + if (stopwatch_expired(&sw)) { + u3p_err("usb clocks are not stable!!!\n"); + return -1; + } + + sts1 = read32(&ippc_regs->ip_pw_sts1) & check_bits; + sts2 = read32(&ippc_regs->ip_pw_sts2) & STS2_U2_MAC_RST; + } while ((sts1 != check_bits) || !sts2); + + return 0; +} + +static int u3phy_ports_enable(void) +{ + int i; + u32 value; + int u3_port_num; + int u2_port_num; + + value = read32(&ippc_regs->ip_xhci_cap); + u3_port_num = CAP_U3_PORT_NUM(value); + u2_port_num = CAP_U2_PORT_NUM(value); + u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num); + + /* power on host ip */ + clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN); + + /* power on and enable all u3 ports */ + for (i = 0; i < u3_port_num; i++) { + clrsetbits_le32(&ippc_regs->u3_ctrl_p[i], + CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, + CTRL_U3_PORT_HOST_SEL); + } + + /* power on and enable all u2 ports */ + for (i = 0; i < u2_port_num; i++) { + clrsetbits_le32(&ippc_regs->u2_ctrl_p[i], + CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, + CTRL_U2_PORT_HOST_SEL); + } + return check_ip_clk_status(); +} + +static inline void ssusb_soft_reset(void) +{ + /* reset whole ip */ + setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); + clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); +} + +__weak void mtk_usb_prepare(void) { /* do nothing */ } + +void setup_usb_host(void) +{ + int ret; + + u3p_msg("Setting up USB HOST controller...\n"); + + mtk_usb_prepare(); + ssusb_soft_reset(); + ret = u3phy_ports_enable(); + if (ret) { + u3p_err("%s fail to enable ports\n", __func__); + return; + } + u3phy_power_on(); + u3p_msg("phy power-on done.\n"); +} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 73048f4..e125e03 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -80,7 +80,7 @@ ramstage-y += ../common/pll.c pll.c ramstage-y += rtc.c -ramstage-y += usb.c +ramstage-y += ../common/usb.c usb.c ramstage-y += ddp.c ramstage-y += dsi.c diff --git a/src/soc/mediatek/mt8173/include/soc/usb.h b/src/soc/mediatek/mt8173/include/soc/usb.h index 646b077..8a6f61a 100644 --- a/src/soc/mediatek/mt8173/include/soc/usb.h +++ b/src/soc/mediatek/mt8173/include/soc/usb.h @@ -16,147 +16,7 @@ #ifndef SOC_MEDIATEK_MT8173_USB_H #define SOC_MEDIATEK_MT8173_USB_H -/* ip_pw_ctrl0 */ -#define CTRL0_IP_SW_RST (0x1 << 0) - -/* ip_pw_ctrl1 */ -#define CTRL1_IP_HOST_PDN (0x1 << 0) - -/* ip_pw_sts1 */ -#define STS1_U3_MAC_RST (0x1 << 16) -#define STS1_SYS125_RST (0x1 << 10) -#define STS1_REF_RST (0x1 << 8) -#define STS1_SYSPLL_STABLE (0x1 << 0) - -/* ip_pw_sts2 */ -#define STS2_U2_MAC_RST (0x1 << 0) - -/* ip_xhci_cap */ -#define CAP_U3_PORT_NUM(p) ((p) & 0xff) -#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) - -/* u3_ctrl_p */ -#define CTRL_U3_PORT_HOST_SEL (0x1 << 2) -#define CTRL_U3_PORT_PDN (0x1 << 1) -#define CTRL_U3_PORT_DIS (0x1 << 0) - -/* u2_ctrl_p */ -#define CTRL_U2_PORT_HOST_SEL (0x1 << 2) -#define CTRL_U2_PORT_PDN (0x1 << 1) -#define CTRL_U2_PORT_DIS (0x1 << 0) - -struct ssusb_ippc_regs { - u32 ip_pw_ctr0; - u32 ip_pw_ctr1; - u32 ip_pw_ctr2; - u32 ip_pw_ctr3; - u32 ip_pw_sts1; - u32 ip_pw_sts2; - u32 reserved0[3]; - u32 ip_xhci_cap; - u32 reserved1[2]; - u64 u3_ctrl_p[4]; - u64 u2_ctrl_p[6]; -}; - -/* U2PHY_COM USBPHYACR5 */ -#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12) -#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) -#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11) - -/* U2PHY_COM USBPHYACR6 */ -#define PA6_RG_U2_ISO_EN (0x1 << 31) -#define PA6_RG_U2_BC11_SW_EN (0x1 << 23) -#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) -#define PA6_RG_U2_SQTH (0xf << 0) -#define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0) - -/* U2PHY_COM U2PHYACR4 */ -#define P2C_RG_USB20_GPIO_CTL (0x1 << 9) -#define P2C_USB20_GPIO_MODE (0x1 << 8) -#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) - -/* U2PHY_COM U2PHYDTM0 */ -#define P2C_FORCE_UART_EN (0x1 << 26) -#define P2C_FORCE_DATAIN (0x1 << 23) -#define P2C_FORCE_DM_PULLDOWN (0x1 << 21) -#define P2C_FORCE_DP_PULLDOWN (0x1 << 20) -#define P2C_FORCE_XCVRSEL (0x1 << 19) -#define P2C_FORCE_SUSPENDM (0x1 << 18) -#define P2C_FORCE_TERMSEL (0x1 << 17) -#define P2C_RG_DATAIN (0xf << 10) -#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) -#define P2C_RG_DMPULLDOWN (0x1 << 7) -#define P2C_RG_DPPULLDOWN (0x1 << 6) -#define P2C_RG_XCVRSEL (0x3 << 4) -#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) -#define P2C_RG_SUSPENDM (0x1 << 3) -#define P2C_RG_TERMSEL (0x1 << 2) -#define P2C_DTM0_PART_MASK \ - (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ - P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ - P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ - P2C_RG_TERMSEL) - -/* U2PHY_COM U2PHYDTM1 */ -#define P2C_RG_UART_EN (0x1 << 16) -#define P2C_RG_VBUSVALID (0x1 << 5) -#define P2C_RG_SESSEND (0x1 << 4) -#define P2C_RG_AVALID (0x1 << 2) - -/* U3PHYA PHYA_REG0 */ -#define P3A_RG_U3_VUSB10_ON (1 << 5) - -/* U3PHYA PHYA_REG6 */ -#define P3A_RG_TX_EIDLE_CM (0xf << 28) -#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) - -/* U3PHYA PHYA_REG9 */ -#define P3A_RG_RX_DAC_MUX (0x1f << 1) -#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) - -/* U3PHYA_DA REG0 */ -#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10) -#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) - -/* U3PHYD CDR1 */ -#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24) -#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) -#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8) -#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) - -struct sif_u2_phy_com { - u32 reserved0[5]; - u32 usbphyacr5; - u32 usbphyacr6; - u32 u2phyacr3; - u32 u2phyacr4; - u32 reserved1[17]; - u32 u2phydtm0; - u32 u2phydtm1; - u32 reserved2[36]; /* 0x70 - 0xff */ -}; -check_member(sif_u2_phy_com, u2phydtm0, 0x68); - -struct sif_u3phyd { - u32 reserved0[23]; - u32 phyd_cdr1; - u32 reserved1[40]; -}; - -struct sif_u3phya { - u32 phya_reg0; - u32 reserved0[5]; - u32 phya_reg6; - u32 reserved1[2]; - u32 phya_reg9; - u32 reserved2[54]; -}; - -struct sif_u3phya_da { - u32 reg0; - u32 reserved[63]; -}; +#include <soc/usb_common.h> struct ssusb_sif_port { struct sif_u2_phy_com u2phy; @@ -170,9 +30,9 @@ check_member(ssusb_sif_port, u3phya, 0x300); check_member(ssusb_sif_port, u3phya_da, 0x400); check_member(ssusb_sif_port, reserved1, 0x500); -_Static_assert(sizeof(struct ssusb_sif_port) == 0x800, \ +_Static_assert(sizeof(struct ssusb_sif_port) == 0x800, "ssusb_sif_port size is wrong!"); -void setup_usb_host(void); +#define USB_PORT_NUMBER 2 #endif diff --git a/src/soc/mediatek/mt8173/usb.c b/src/soc/mediatek/mt8173/usb.c index 1dccfc9..a61a64b 100644 --- a/src/soc/mediatek/mt8173/usb.c +++ b/src/soc/mediatek/mt8173/usb.c @@ -13,158 +13,10 @@ * GNU General Public License for more details. */ -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <soc/addressmap.h> #include <soc/pll.h> #include <soc/usb.h> -#include <timer.h> -#define USBTAG "[SSUSB] " -#define u3p_msg(fmt, arg...) printk(BIOS_INFO, USBTAG fmt, ##arg) -#define u3p_err(fmt, arg...) printk(BIOS_ERR, USBTAG fmt, ##arg) - -static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE); -static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE); - -static void phy_index_power_on(int index) +void mtk_usb_prepare(void) { - struct ssusb_sif_port *phy = phy_ports + index; - - if (!index) { - /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ - setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); - /* power domain iso disable */ - clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); - } - /* switch to USB function. (system register, force ip into usb mode) */ - clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); - clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); - if (!index) - clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); - - /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ - clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | - P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); - - /* DP/DM BC1.1 path Disable */ - clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); - /* improve Rx sensitivity */ - clrsetbits_le32(&phy->u2phy.usbphyacr6, - PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); - /* OTG Enable */ - setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); - - clrsetbits_le32(&phy->u3phya_da.reg0, - P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); - - clrsetbits_le32(&phy->u3phya.phya_reg9, - P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); - - if (!index) { - /* [mt8173]disable Change 100uA current from SSUSB */ - clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); - } - - clrsetbits_le32(&phy->u3phya.phya_reg6, - P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); - - clrsetbits_le32(&phy->u3phyd.phyd_cdr1, - P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc)); - clrsetbits_le32(&phy->u3phyd.phyd_cdr1, - P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3)); - - clrsetbits_le32(&phy->u2phy.u2phydtm1, - P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); - - /* USB 2.0 slew rate calibration */ - clrsetbits_le32(&phy->u2phy.usbphyacr5, - PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); -} - -static void u3phy_power_on(void) -{ - phy_index_power_on(0); - phy_index_power_on(1); -} - -static int check_ip_clk_status(void) -{ - int u3_port_num; - u32 check_bits; - u32 sts1, sts2; - struct stopwatch sw; - - u3_port_num = CAP_U3_PORT_NUM(read32(&ippc_regs->ip_xhci_cap)); - - check_bits = STS1_SYSPLL_STABLE | STS1_REF_RST | STS1_SYS125_RST; - check_bits |= (u3_port_num ? STS1_U3_MAC_RST : 0); - - stopwatch_init_usecs_expire(&sw, 50000); - - do { - if (stopwatch_expired(&sw)) { - u3p_err("usb clocks are not stable!!!\n"); - return -1; - } - - sts1 = read32(&ippc_regs->ip_pw_sts1) & check_bits; - sts2 = read32(&ippc_regs->ip_pw_sts2) & STS2_U2_MAC_RST; - } while ((sts1 != check_bits) || !sts2); - - return 0; -} - -static int u3phy_ports_enable(void) -{ - int i; - u32 value; - int u3_port_num; - int u2_port_num; - - value = read32(&ippc_regs->ip_xhci_cap); - u3_port_num = CAP_U3_PORT_NUM(value); - u2_port_num = CAP_U2_PORT_NUM(value); - u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num); - - /* power on host ip */ - clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN); - - /* power on and enable all u3 ports */ - for (i = 0; i < u3_port_num; i++) { - clrsetbits_le32(&ippc_regs->u3_ctrl_p[i], - CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL); - } - - /* power on and enable all u2 ports */ - for (i = 0; i < u2_port_num; i++) { - clrsetbits_le32(&ippc_regs->u2_ctrl_p[i], - CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL); - } - return check_ip_clk_status(); -} - -static inline void ssusb_soft_reset(void) -{ - /* reset whole ip */ - setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); - clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); -} - -void setup_usb_host(void) -{ - int ret; - - u3p_msg("Setting up USB HOST controller...\n"); - mt_pll_enable_ssusb_clk(); - ssusb_soft_reset(); - ret = u3phy_ports_enable(); - if (ret) { - u3p_err("%s fail to enable ports\n", __func__); - return; - } - u3phy_power_on(); - u3p_msg("phy power-on done.\n"); } -- To view, visit https://review.coreboot.org/28786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I06fefb4149a489be991e13ddf624082d11e31765 Gerrit-Change-Number: 28786 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: cpu/intel/microcode: Replace MSR addresses with macros
by Elyes HAOUAS (Code Review) 28 Sep '18

28 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28784 to look at the new patch set (#2). Change subject: cpu/intel/microcode: Replace MSR addresses with macros ...................................................................... cpu/intel/microcode: Replace MSR addresses with macros Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28784/2 -- To view, visit https://review.coreboot.org/28784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Gerrit-Change-Number: 28784 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for L...
by Seunghwan Kim (Code Review) 28 Sep '18

28 Sep '18

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/28785 Change subject: mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE sku ...................................................................... mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE sku BUG=none BRANCH=poppy TEST=Built and passed on reliability test with modified coreboot Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/28785/1 diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index b9f6314..bacf1a4 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -86,6 +86,11 @@ cfg->usb2_ports[4].tx_emp_enable = USB2_PRE_EMP_ON; cfg->usb2_ports[4].pre_emp_bias = USB2_BIAS_56MV; cfg->usb2_ports[4].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; + + /* Override SlowSlewRate settings */ + cfg->SlowSlewRateForIa = 0; + cfg->SlowSlewRateForGt = 0; + cfg->SlowSlewRateForSa = 0; break; default: -- To view, visit https://review.coreboot.org/28785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54 Gerrit-Change-Number: 28785 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: cpu/intel/microcode: Replace numbers with macros
by Werner Zeh (Code Review) 28 Sep '18

28 Sep '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/28784 ) Change subject: cpu/intel/microcode: Replace numbers with macros ...................................................................... Patch Set 1: Can you please provide a more meaningful commit message. At least mention that "numbers" in this case means MSR addresses. -- To view, visit https://review.coreboot.org/28784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Gerrit-Change-Number: 28784 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 28 Sep 2018 08:18:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: cpu/intel/microcode: Replace numbers with macros
by Elyes HAOUAS (Code Review) 28 Sep '18

28 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28784 Change subject: cpu/intel/microcode: Replace numbers with macros ...................................................................... cpu/intel/microcode: Replace numbers with macros Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28784/1 diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 8cfcb95..0dd9a5b 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -103,7 +103,7 @@ msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; - wrmsr(0x79, msr); + wrmsr(IA32_BIOS_UPDT_TRIG, msr); #if !defined(__ROMCC__) printk(BIOS_DEBUG, "microcode: updated to revision " @@ -162,9 +162,9 @@ /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; - wrmsr(0x8B, msr); + wrmsr(IA32_BIOS_SIGN_ID, msr); eax = cpuid_eax(1); - msr = rdmsr(0x8B); + msr = rdmsr(IA32_BIOS_SIGN_ID); rev = msr.hi; x86_model = (eax >> 4) & 0x0f; x86_family = (eax >> 8) & 0x0f; @@ -172,7 +172,7 @@ pf = 0; if ((x86_model >= 5) || (x86_family > 6)) { - msr = rdmsr(0x17); + msr = rdmsr(IA32_PLATFORM_ID); pf = 1 << ((msr.hi >> 18) & 7); } #if !defined(__ROMCC__) -- To view, visit https://review.coreboot.org/28784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Gerrit-Change-Number: 28784 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit September 2018