coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: increase touchscreen reset delay
by Nick Vaccaro (Code Review) 30 Sep '18

30 Sep '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/28803 Change subject: mb/google/poppy/variant/nocturne: increase touchscreen reset delay ...................................................................... mb/google/poppy/variant/nocturne: increase touchscreen reset delay Increase the reset delay for the touchscreen to 10 seconds. BUG=b:116857433 TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, log in and execute the following two commands: echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind and verify the bind command does not echo back a "-bash: echo: write error: No such device" error. Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/28803/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 70a379c..c6a18f7 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -291,7 +291,7 @@ register "generic.speed" = "I2C_SPEED_FAST_PLUS" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" - register "generic.reset_delay_ms" = "1" + register "generic.reset_delay_ms" = "10" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" -- To view, visit https://review.coreboot.org/28803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Gerrit-Change-Number: 28803 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Fix spelling mistake
by Subrata Banik (Code Review) 29 Sep '18

29 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28802 Change subject: soc/intel/skylake: Fix spelling mistake ...................................................................... soc/intel/skylake: Fix spelling mistake Make correct spelling for THERMAL_IRQ macro in irq.h file. Change-Id: I83593822e2abbb07e60fc336b774199fea3b368f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/irq.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28802/1 diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl index eb10b36..95be776 100644 --- a/src/soc/intel/skylake/acpi/pci_irqs.asl +++ b/src/soc/intel/skylake/acpi/pci_irqs.asl @@ -58,7 +58,7 @@ /* D20: xHCI, OTG, Thermal, Camera */ Package () { 0x0014FFFF, 0, 0, XHCI_IRQ }, Package () { 0x0014FFFF, 1, 0, OTG_IRQ }, - Package () { 0x0014FFFF, 2, 0, THRMAL_IRQ }, + Package () { 0x0014FFFF, 2, 0, THERMAL_IRQ }, Package () { 0x0014FFFF, 3, 0, CIO_INTD_IRQ }, /* D19: Integrated Sensor Hub */ Package () { 0x0013FFFF, 0, 0, ISH_IRQ }, diff --git a/src/soc/intel/skylake/include/soc/irq.h b/src/soc/intel/skylake/include/soc/irq.h index fda8142..cdc620f 100644 --- a/src/soc/intel/skylake/include/soc/irq.h +++ b/src/soc/intel/skylake/include/soc/irq.h @@ -86,7 +86,7 @@ #define XHCI_IRQ 16 #define OTG_IRQ 17 -#define THRMAL_IRQ 18 +#define THERMAL_IRQ 18 #define CIO_INTA_IRQ 16 #define CIO_INTD_IRQ 19 #define ISH_IRQ 20 diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 146fcda..7b3e1bd 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -208,7 +208,7 @@ PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), /* Thermal Subsystem */ DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ), + PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), /* Camera IO Host Controller */ DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), -- To view, visit https://review.coreboot.org/28802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I83593822e2abbb07e60fc336b774199fea3b368f Gerrit-Change-Number: 28802 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Replace white space with tab
by Subrata Banik (Code Review) 29 Sep '18

29 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28801 Change subject: soc/intel/skylake: Replace white space with tab ...................................................................... soc/intel/skylake: Replace white space with tab This patch unified line indentation. Change-Id: Ife3396e36a0684490d9ed9b31b4c0a543a3e3d24 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/acpi/pcie.asl 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28801/1 diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 13b2dc1..84cb437 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -249,7 +249,7 @@ Device (RP09) { - Name (_ADR, 0x001D0000) + Name (_ADR, 0x001D0000) OperationRegion (RPCS, PCI_Config, 0x4c, 4) Field (RPCS, AnyAcc, NoLock, Preserve) @@ -258,15 +258,15 @@ RPPN, 8, /* Root Port Number */ } - Method (_PRT) - { + Method (_PRT) + { Return (IRQM (RPPN)) - } + } } Device (RP10) { - Name (_ADR, 0x001D0001) + Name (_ADR, 0x001D0001) OperationRegion (RPCS, PCI_Config, 0x4c, 4) Field (RPCS, AnyAcc, NoLock, Preserve) @@ -275,15 +275,15 @@ RPPN, 8, /* Root Port Number */ } - Method (_PRT) - { + Method (_PRT) + { Return (IRQM (RPPN)) - } + } } Device (RP11) { - Name (_ADR, 0x001D0002) + Name (_ADR, 0x001D0002) OperationRegion (RPCS, PCI_Config, 0x4c, 4) Field (RPCS, AnyAcc, NoLock, Preserve) @@ -292,10 +292,10 @@ RPPN, 8, /* Root Port Number */ } - Method (_PRT) - { + Method (_PRT) + { Return (IRQM (RPPN)) - } + } } Device (RP12) @@ -309,8 +309,8 @@ RPPN, 8, /* Root Port Number */ } - Method (_PRT) - { + Method (_PRT) + { Return (IRQM (RPPN)) - } + } } -- To view, visit https://review.coreboot.org/28801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife3396e36a0684490d9ed9b31b4c0a543a3e3d24 Gerrit-Change-Number: 28801 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add PCIE ASL entry
by Subrata Banik (Code Review) 29 Sep '18

29 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28800 Change subject: soc/intel/cannonlake: Add PCIE ASL entry ...................................................................... soc/intel/cannonlake: Add PCIE ASL entry This patch creates _PRT entires for each PCIE root port devices. TEST=Able to see PCIE wake device in cat /proc/acpi/wake list Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/cannonlake/acpi/pcie.asl M src/soc/intel/cannonlake/acpi/southbridge.asl 2 files changed, 385 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28800/1 diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl new file mode 100644 index 0000000..69e16ca --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -0,0 +1,382 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 2b34df5..ff323c4 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -41,6 +41,9 @@ /* PCH HDA */ #include "pch_hda.asl" +/* PCIE Ports */ +#include "pcie.asl" + /* Serial IO */ #include "serialio.asl" -- To view, visit https://review.coreboot.org/28800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 Gerrit-Change-Number: 28800 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI...
by Subrata Banik (Code Review) 29 Sep '18

29 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28799 Change subject: soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices ...................................................................... soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/cannonlake/acpi/irqlinks.asl M src/soc/intel/cannonlake/acpi/pci_irqs.asl M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/cannonlake/include/soc/irq.h 4 files changed, 417 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/28799/1 diff --git a/src/soc/intel/cannonlake/acpi/irqlinks.asl b/src/soc/intel/cannonlake/acpi/irqlinks.asl new file mode 100644 index 0000000..0403ea0 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/irqlinks.asl @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * PIRQ routing control is in PCR ITSS region. + * + * Due to what appears to be an ACPI interpreter bug we do not use + * the PCRB() method here as it may not be defined yet because the method + * definiton depends on the order of the include files in pch.asl. + * + * https://bugs.acpica.org/show_bug.cgi?id=1201 + */ +OperationRegion (ITSS, SystemMemory, + Add (PCR_ITSS_PIRQA_ROUT, + Add (CONFIG_PCR_BASE_ADDRESS, + ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) +Field (ITSS, ByteAcc, NoLock, Preserve) +{ + PIRA, 8, /* PIRQA Routing Control */ + PIRB, 8, /* PIRQB Routing Control */ + PIRC, 8, /* PIRQC Routing Control */ + PIRD, 8, /* PIRQD Routing Control */ + PIRE, 8, /* PIRQE Routing Control */ + PIRF, 8, /* PIRQF Routing Control */ + PIRG, 8, /* PIRQG Routing Control */ + PIRH, 8, /* PIRQH Routing Control */ +} + +Name (IREN, 0x80) /* Interrupt Routing Enable */ +Name (IREM, 0x0f) /* Interrupt Routing Mask */ + +Device (LNKA) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 1) + + Method (_CRS, 0, Serialized) + { + Name (RTLA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {11} + }) + CreateWordField (RTLA, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0) + + Return (RTLA) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRA, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKB) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 2) + + Method (_CRS, 0, Serialized) + { + Name (RTLB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {10} + }) + CreateWordField (RTLB, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0) + + Return (RTLB) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRB, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKC) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 3) + + Method (_CRS, 0, Serialized) + { + Name (RTLC, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {11} + }) + CreateWordField (RTLC, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0) + + Return (RTLC) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRC, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKD) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 4) + + Method (_CRS, 0, Serialized) + { + Name (RTLD, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {11} + }) + CreateWordField (RTLD, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0) + + Return (RTLD) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRD, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKE) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 5) + + Method (_CRS, 0, Serialized) + { + Name (RTLE, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {11} + }) + CreateWordField (RTLE, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0) + + Return (RTLE) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRE, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKF) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 6) + + Method (_CRS, 0, Serialized) + { + Name (RTLF, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {11} + }) + CreateWordField (RTLF, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0) + + Return (RTLF) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRF, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKG) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 7) + + Method (_CRS, 0, Serialized) + { + Name (RTLG, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {11} + }) + CreateWordField (RTLG, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0) + + Return (RTLG) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRG, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKH) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 8) + + Method (_CRS, 0, Serialized) + { + Name (RTLH, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {11} + }) + CreateWordField (RTLH, 1, IRQ0) + Store (Zero, IRQ0) + + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0) + + Return (RTLH) + } + + Method (_STA, 0, Serialized) + { + If (And (^^PIRH, ^^IREN)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index eeed667..d346ce2 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. + * Copyright (C) 2017-2018 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -15,85 +15,127 @@ * GNU General Public License for more details. */ -Method(_PRT) +#include <soc/irq.h> + +Name (PICP, Package () { + /* PCI Bridge */ + /* cAVS, SMBus, GbE, Nothpeak */ + Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, + Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, + Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, + Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, + /* SerialIo and SCS */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* PCI Express Port 9-16 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + /* eMMC */ + Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, + /* SerialIo */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* SATA controller */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 2, 0, IDER_IRQ }, + Package(){0x0016FFFF, 3, 0, KT_IRQ }, + /* SerialIo */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, + Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, + /* Integrated Sensor Hub */ + Package(){0x0013FFFF, 0, 0, ISH_IRQ }, + /* Thermal */ + Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, + /* Host Bridge */ + /* Root Port D1F0 */ + Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, + Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, + Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, + Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Nothpeak */ + Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D32: Can't use PIC*/ + /* D29: PCI Express Port 9-16 */ + Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D25: Can't use PIC*/ + /* D23 */ + Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D21: Can't use PIC*/ + /* D20: xHCI, OTG, SRAM, CNVi WiFi */ + Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D19: Can't use PIC*/ + /* Thermal */ + Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* P.E.G. Root Port D1F0 */ + Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 }, +}) + +Method (_PRT) { - Return(Package() { - - // PCI Bridge - // cAVS, SMBus, GbE, Nothpeak - Package(){0x001FFFFF, 0, 0, 16 }, - Package(){0x001FFFFF, 1, 0, 17 }, - Package(){0x001FFFFF, 2, 0, 18 }, - Package(){0x001FFFFF, 3, 0, 19 }, - // SerialIo and SCS - Package(){0x001EFFFF, 0, 0, 20 }, - Package(){0x001EFFFF, 1, 0, 21 }, - Package(){0x001EFFFF, 2, 0, 22 }, - Package(){0x001EFFFF, 3, 0, 23 }, - // PCI Express Port 9-16 - Package(){0x001DFFFF, 0, 0, 16 }, - Package(){0x001DFFFF, 1, 0, 17 }, - Package(){0x001DFFFF, 2, 0, 18 }, - Package(){0x001DFFFF, 3, 0, 19 }, - // PCI Express Port 1-8 - Package(){0x001CFFFF, 0, 0, 16 }, - Package(){0x001CFFFF, 1, 0, 17 }, - Package(){0x001CFFFF, 2, 0, 18 }, - Package(){0x001CFFFF, 3, 0, 19 }, - // PCI Express Port 17-20 - Package(){0x001BFFFF, 0, 0, 16 }, - Package(){0x001BFFFF, 1, 0, 17 }, - Package(){0x001BFFFF, 2, 0, 18 }, - Package(){0x001BFFFF, 3, 0, 19 }, - // eMMC - Package(){0x001AFFFF, 0, 0, 16 }, - Package(){0x001AFFFF, 1, 0, 17 }, - Package(){0x001AFFFF, 2, 0, 18 }, - Package(){0x001AFFFF, 3, 0, 19 }, - // SerialIo - Package(){0x0019FFFF, 0, 0, 32 }, - Package(){0x0019FFFF, 1, 0, 33 }, - Package(){0x0019FFFF, 2, 0, 34 }, - // SATA controller - Package(){0x0017FFFF, 0, 0, 16 }, - // CSME (HECI, IDE-R, Keyboard and Text redirection - Package(){0x0016FFFF, 0, 0, 16 }, - Package(){0x0016FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 2, 0, 18 }, - Package(){0x0016FFFF, 3, 0, 19 }, - // SerialIo - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - // CNL: D20: xHCI, OTG, CNVi WiFi, SDcard - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - // Integrated Sensor Hub - Package(){0x0013FFFF, 0, 0, 20 }, - // Thermal, UFS, SerialIo SPI 2 - Package(){0x0012FFFF, 0, 0, 16 }, - Package(){0x0012FFFF, 1, 0, 24 }, - Package(){0x0012FFFF, 2, 0, 18 }, - Package(){0x0012FFFF, 3, 0, 19 }, - - // Host Bridge - // Root Port D1F0 - Package(){0x0001FFFF, 0, 0, 16 }, - Package(){0x0001FFFF, 1, 0, 17 }, - Package(){0x0001FFFF, 2, 0, 18 }, - Package(){0x0001FFFF, 3, 0, 19 }, - // Root Port D1F1 - // Root Port D1F2 - // IGFX Device - Package(){0x0002FFFF, 0, 0, 16 }, - // Thermal Device - Package(){0x0004FFFF, 0, 0, 16 }, - // IPU Device - Package(){0x0005FFFF, 0, 0, 16 }, - // GNA Device - Package(){0x0008FFFF, 0, 0, 16 }, - }) + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } } diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 6fac398..2b34df5 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -15,6 +15,13 @@ * GNU General Public License for more details. */ +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +/* Interrupt Routing */ +#include "irqlinks.asl" /* PCI IRQ assignment */ #include "pci_irqs.asl" diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 5b6715f..61f4025 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -87,8 +87,9 @@ #define XHCI_IRQ 16 #define OTG_IRQ 17 -#define THRMAL_IRQ 16 -#define CNViWIFI_IRQ 16 +#define PMC_SRAM_IRQ 18 +#define THERMAL_IRQ 16 +#define CNViWIFI_IRQ 19 #define UFS_IRQ 16 #define CIO_INTA_IRQ 16 #define CIO_INTD_IRQ 19 @@ -101,6 +102,6 @@ #define IGFX_IRQ 16 #define SA_THERMAL_IRQ 16 -#define SKYCAM_IRQ 16 -#define GMM_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ -- To view, visit https://review.coreboot.org/28799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Gerrit-Change-Number: 28799 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: src/Kconfig: Drop a superfluous word
by Angel Pons (Code Review) 29 Sep '18

29 Sep '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28798 ) Change subject: src/Kconfig: Drop a superfluous word ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d658e57d52f79c77be08599b9e525a46e30f732 Gerrit-Change-Number: 28798 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 29 Sep 2018 19:00:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD
by Sathyanarayana Nujella (Code Review) 29 Sep '18

29 Sep '18

Sathyanarayana Nujella has posted comments on this change. ( https://review.coreboot.org/28797 ) Change subject: mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD ...................................................................... Patch Set 4: Code-Review+1 Thank you Furquan for sharing generic driver and its configuration. -- To view, visit https://review.coreboot.org/28797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e Gerrit-Change-Number: 28797 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 29 Sep 2018 18:57:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/generic: Add support for providing DSD properties
by Sathyanarayana Nujella (Code Review) 29 Sep '18

29 Sep '18

Sathyanarayana Nujella has posted comments on this change. ( https://review.coreboot.org/28796 ) Change subject: drivers/generic: Add support for providing DSD properties ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/28796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ca6614f1ef322397618676bbf6da898bef18990 Gerrit-Change-Number: 28796 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 29 Sep 2018 18:56:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD
by Nick Vaccaro (Code Review) 29 Sep '18

29 Sep '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/28797 ) Change subject: mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/28797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e Gerrit-Change-Number: 28797 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 29 Sep 2018 17:46:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: drivers/generic: Add support for providing DSD properties
by Nick Vaccaro (Code Review) 29 Sep '18

29 Sep '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/28796 ) Change subject: drivers/generic: Add support for providing DSD properties ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/28796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ca6614f1ef322397618676bbf6da898bef18990 Gerrit-Change-Number: 28796 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 29 Sep 2018 17:46:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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