coreboot-gerrit September 2018

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Change in coreboot[master]: soc/intel/common/block/hda: Enable static scanning of devices under HDA
by Furquan Shaikh (Code Review) 29 Sep '18

29 Sep '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28807 Change subject: soc/intel/common/block/hda: Enable static scanning of devices under HDA ...................................................................... soc/intel/common/block/hda: Enable static scanning of devices under HDA This change sets scan_bus operation for HDA to scan_static_bus to allow enumeration of static devices under HDA. BUG=b:112888584 Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/hda/hda.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/28807/1 diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 97efba2..2409b75 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -68,6 +68,7 @@ .init = &hda_init, #endif .ops_pci = &pci_dev_ops_pci, + .scan_bus = &scan_static_bus, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/28807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4 Gerrit-Change-Number: 28807 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/.../hda: Add and use config for initialization of HDA codecs
by Furquan Shaikh (Code Review) 29 Sep '18

29 Sep '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28806 Change subject: soc/intel/.../hda: Add and use config for initialization of HDA codecs ...................................................................... soc/intel/.../hda: Add and use config for initialization of HDA codecs Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for initialization of HDA codecs only. This prevents adding of any static devices under the HDA device node. However, there can be boards which want to add devices under HDA node without performing any codec initialization using the HDA. This change: 1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can be set explicitly by the boards that want to perform code initialization. 2. Uses newly added config option is used to guard the initialization functions for the codec. Rest of the device operations can still be used by all the other boards without having to use HDA codec initialization. 3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in kblrvp which was the only board enabling HDA codec initialization using common block code. 4. Original config SOC_INTEL_COMMON_BLOCK_HDA is selected for skylake SoC. Above changes need to be bundled and pushed in as a single change in order to avoid breaking existing users. BUG=b:112888584 Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/intel/kblrvp/Kconfig M src/soc/intel/common/block/hda/Kconfig M src/soc/intel/common/block/hda/hda.c M src/soc/intel/skylake/Kconfig 4 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28806/1 diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index aed8297..bf17c4b 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -8,7 +8,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 select SOC_INTEL_SKYLAKE select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 select MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/common/block/hda/Kconfig b/src/soc/intel/common/block/hda/Kconfig index ca415bc..a2209ab 100644 --- a/src/soc/intel/common/block/hda/Kconfig +++ b/src/soc/intel/common/block/hda/Kconfig @@ -2,3 +2,9 @@ bool help Intel Processor common High Definition Audio driver support + +config SOC_INTEL_COMMON_BLOCK_HDA_VERB + bool + depends on SOC_INTEL_COMMON_BLOCK_HDA + help + Enable initialization of HDA codecs. diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 3f87fcc..97efba2 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -22,6 +22,7 @@ #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) static void codecs_init(uint8_t *base, u32 codec_mask) { int i; @@ -57,12 +58,15 @@ codecs_init(base, codec_mask); } } +#endif static struct device_operations hda_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) .init = &hda_init, +#endif .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6a5dc07..e368dec 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -61,6 +61,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI + select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMM -- To view, visit https://review.coreboot.org/28806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c Gerrit-Change-Number: 28806 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: cpu/intel/car: Fix typo
by Elyes HAOUAS (Code Review) 29 Sep '18

29 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28805 Change subject: cpu/intel/car: Fix typo ...................................................................... cpu/intel/car: Fix typo Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28805/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f47e812..9a433d6 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -55,7 +55,7 @@ wrmsr jnz clear_fixed_mtrr - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */ diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index b3bf230..121d169 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -43,7 +43,7 @@ wrmsr jnz clear_fixed_mtrr - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 316d452..eb5e490 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -53,7 +53,7 @@ wrmsr jnz clear_fixed_mtrr - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */ -- To view, visit https://review.coreboot.org/28805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Gerrit-Change-Number: 28805 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: Documentation: Add basic flashing tutorial for Lenovo
by Philipp Deppenwiese (Code Review) 29 Sep '18

29 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27852 ) Change subject: Documentation: Add basic flashing tutorial for Lenovo ...................................................................... Documentation: Add basic flashing tutorial for Lenovo * Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- A Documentation/flash_tutorial/ext_power.md A Documentation/flash_tutorial/ext_standalone.md A Documentation/flash_tutorial/flash_ic_diode.svg A Documentation/flash_tutorial/flash_ic_no_diode.svg A Documentation/flash_tutorial/index.md A Documentation/flash_tutorial/int_flashrom.md A Documentation/flash_tutorial/no_ext_power.md M Documentation/index.md M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/flashlayout_xx20.svg A Documentation/mainboard/lenovo/flashlayout_xx30.svg A Documentation/mainboard/lenovo/t420.md A Documentation/mainboard/lenovo/t430.md A Documentation/mainboard/lenovo/t4xx_series.md A Documentation/mainboard/lenovo/xx20_series.md A Documentation/mainboard/lenovo/xx30_series.md 16 files changed, 616 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/Documentation/flash_tutorial/ext_power.md b/Documentation/flash_tutorial/ext_power.md new file mode 100644 index 0000000..542ccfd --- /dev/null +++ b/Documentation/flash_tutorial/ext_power.md @@ -0,0 +1,28 @@ +# Flashing firmware externally supplying direct power + +**WARNING:** Never use a high current rated power supply, like PC ATX power + supply. It'll literally melt your PCB traces on short circuit. + +On some mainboards the flash IC Vcc pin is connected to a diode, which prevents +powering the rest of the board. + +![][flash_ic_diode] + +Please have a look at the mainboard specific documentation for details. + +On those boards it's safe to use a programmer and supply power externally. + +**WARNING:** Verify that you apply the correct voltage! + +## USB programmer +USB programmers are usually current limited by the host USB hub. On USB 2.0 +ports the limit is 500mA, which is sufficient to power the flash. Those are +the best choice as they are stateless and have a fast power on reset cycle. + +## Single board computers (like BeagleBone Black / RPi) +Be careful when connecting a flash chip, especially when using a Pomona +test-clip. A short circuit or overcurrent (250mA) causes a brown-out reset, +resulting in a reboot of the running operating system (and possible loss of +remote shell). + +[flash_ic_diode]: flash_ic_diode.svg diff --git a/Documentation/flash_tutorial/ext_standalone.md b/Documentation/flash_tutorial/ext_standalone.md new file mode 100644 index 0000000..3a676ce --- /dev/null +++ b/Documentation/flash_tutorial/ext_standalone.md @@ -0,0 +1,23 @@ +# Flashing firmware standalone + +If none of the other methods work, there are three possibilities: + +## Desolder +You must remove or desolder the flash IC before you can flash it. +It's recommended to solder a socket in place of the flash IC. + +When flashing the IC, always connect all input pins. +If in doubt, pull /WP, /HOLD, /RESET and alike up towards Vcc. + +## SPI flash emulator +If you are a developer, you might want to use an [EM100Pro] instead, which sets +the onboard flash on hold, and allows to run custom firmware. +It provides a very fast development cycle without actually writing to flash. + +## SPI flash overwrite +It is possible to set the onboard flash on hold and use another flash chip. +Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC +low, and /HOLD of your replacement flash IC high. + + +[EM100Pro]: https://www.dediprog.com/product/EM100Pro diff --git a/Documentation/flash_tutorial/flash_ic_diode.svg b/Documentation/flash_tutorial/flash_ic_diode.svg new file mode 100644 index 0000000..22cd872 --- /dev/null +++ b/Documentation/flash_tutorial/flash_ic_diode.svg @@ -0,0 +1,61 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="4cm" height="3cm" viewBox="311 435 68 45" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <g> + <rect style="fill: #ffffff" x="322.125" y="451.034" width="37.75" height="26.6444"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="322.125" y="451.034" width="37.75" height="26.6444"/> + <text font-size="4.51549" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="341" y="465.734"> + <tspan x="341" y="465.734"></tspan> + </text> + </g> + <line style="fill: none; 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You need to buy a flash programmer, that +exposes the same interface as your flash IC (likely SPI). + +Please also have a look at the mainboard-specific documentation for details. + +After exposing the firmware flash IC, read the schematics and use one of the +possible methods: + +* [Flashing firmware standalone](ext_standalone.md) +* [Flashing firmware externally supplying direct power](ext_power.md) +* [Flashing firmware externally without supplying direct power](no_ext_power.md) + +**WARNING:** Using the wrong method or accidentally using the wrong pinout might + permanently damage your hardware! + +## Using a layout file +On platforms where the flash IC is shared with other components you might want +to write only a part of the flash IC. On Intel for example there are IFD, ME and +GBE which don't need to be updated to install coreboot. +To make [flashrom] only write the *bios* region, leaving Intel ME and Intel IFD +untouched, you can use a layout file, which can be created using ifdtool + +```bash +ifdtool -f rom.layout coreboot.rom +``` + +and looks similar to: + +``` +00000000:00000fff fd +00500000:00bfffff bios +00003000:004fffff me +00001000:00002fff gbe +``` + +By specifying *-l* and *-i* [flashrom] writes a single region: +```bash +flashrom -l rom.layout -i bios -w coreboot.rom -p <programmer> +``` + +## Using an IFD to determine the layout +flashrom version 1.0 supports reading the layout from the IFD (first 4KiB of +the ROM). You don't need to manually specify a layout it, but it only works +under the following conditions: + +* Only available on Intel ICH7+ +* There's only one flash IC when flashing externally + +```bash +flashrom --ifd -i bios -w coreboot.rom -p <programmer> +``` + +**TODO** explain FMAP regions, normal/fallback mechanism, flash lock mechanisms + +[flashrom]: https://www.flashrom.org/Flashrom diff --git a/Documentation/flash_tutorial/int_flashrom.md b/Documentation/flash_tutorial/int_flashrom.md new file mode 100644 index 0000000..28b534b --- /dev/null +++ b/Documentation/flash_tutorial/int_flashrom.md @@ -0,0 +1,19 @@ +# Flashing firmware internally + +**WARNING:** If you flash a broken firmware and have no recovery mechanism, you + must use the **external method** to flash a working firmware again. + +## Using flashrom +This method does only work on Linux, if it isn't locked down. +You may also need to boot with 'iomem=relaxed' in the kernel command +line if CONFIG_IO_STRICT_DEVMEM is set. + + +For more details please also check [flashrom's wiki]. +Use the programmer *internal* to flash *coreboot.rom* internally: + +```bash +flashrom -p internal -w coreboot.rom +``` + +[flashrom's wiki]: https://www.flashrom.org/Flashrom diff --git a/Documentation/flash_tutorial/no_ext_power.md b/Documentation/flash_tutorial/no_ext_power.md new file mode 100644 index 0000000..b97ba4c --- /dev/null +++ b/Documentation/flash_tutorial/no_ext_power.md @@ -0,0 +1,22 @@ +# Flashing firmware externally supplying no power + +On some mainboards the flash IC's Vcc pin is connected to the internal +power-rail, powering the entire board if the flash IC is powered externally. +Likely it powers other chips which access the flash IC, preventing the external +programmer from reading/writing the chip. It also violates the components' +power sequence, bringing the ICs into an undefined state. + +![][flash_ic_no_diode] + +Please have a look at the mainboard specific documentation for details. + +On those boards it's recommended to use a programmer without supplying power +externally. + +The key to read and write the flash IC is to put the machine into *S3* sleep- +state or *S5* sleep-state *maybe* with Wake-On-LAN enabled. +Another option that sometimes works is to keep the device in reset. This method requires +knowledge of the board schematics and might require hardware modifications. +Use a multimeter to make sure the flash IC is powered in those sleep states. + +[flash_ic_no_diode]: flash_ic_no_diode.svg diff --git a/Documentation/index.md b/Documentation/index.md index b20eedc..e69f2ea 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -23,3 +23,4 @@ * [Vendorcode-specific documentation](vendorcode/index.md) * [Utilities](util.md) * [Release notes for past releases](releases/index.md) +* [Flashing firmware tutorial](flash_tutorial/index.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 45eb217..c346a3b 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -26,6 +26,20 @@ - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +## Lenovo + +- [T4xx common](lenovo/t4xx_series.md) + +### Sandy Bridge series + +- [T420](lenovo/t420.md) +- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md) + +### Ivy Bridge series + +- [T430](lenovo/t430.md) +- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) + ## SiFive - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) diff --git a/Documentation/mainboard/lenovo/flashlayout_xx20.svg b/Documentation/mainboard/lenovo/flashlayout_xx20.svg new file mode 100644 index 0000000..8884ac3 --- /dev/null +++ b/Documentation/mainboard/lenovo/flashlayout_xx20.svg @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="10cm" height="8cm" viewBox="265 -156 186 159" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 380.877 -151.013 C 401.876,-151.013 379.377,-73.513 400.627,-72.513"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.377 -0.763268 C 395.238,-0.763268 387.016,-72.763 400.877,-72.763"/> + <text font-size="10.1598" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="406.127" y="-68.513"> + <tspan x="406.127" y="-68.513">Flash #0</tspan> + </text> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.223 -0.537117 C 402.222,-0.537117 379.285,28.8102 399.872,27.8376"/> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 382.176 54.9128 C 396.037,54.9128 385.445,27.9997 399.548,27.8376"/> + <text font-size="10.1598" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="407.157" y="30.2529"> + <tspan x="407.157" y="30.2529">Flash #1</tspan> + </text> + <text font-size="6.77333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="266.591" y="54.9733"> + <tspan x="266.591" y="54.9733">0xc00000</tspan> + </text> + <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke-dasharray: 4; stroke: #000000" x1="305.271" y1="-1.2113" x2="378.831" y2="-1.17038"/> +</svg> diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md new file mode 100644 index 0000000..ff7a0a9 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420.md @@ -0,0 +1,16 @@ +# Lenovo T420 + +## Flashing instructions +You have to disassemble the whole device, as the flash IC is on the bottom +of the mainboard. + +For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and + +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md +[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md new file mode 100644 index 0000000..787246f --- /dev/null +++ b/Documentation/mainboard/lenovo/t430.md @@ -0,0 +1,15 @@ +# Lenovo T430 + +## Flashing instructions +You have to disassemble the whole device, as the flash ICs are on the bottom +of the mainboard. + +For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +Steps to access the flash IC are described here [T4xx series]. + +[T4xx series]: t4xx_series.md +[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md diff --git a/Documentation/mainboard/lenovo/t4xx_series.md b/Documentation/mainboard/lenovo/t4xx_series.md new file mode 100644 index 0000000..23fe0fb --- /dev/null +++ b/Documentation/mainboard/lenovo/t4xx_series.md @@ -0,0 +1,20 @@ +# Lenovo T4xx series disassembly instructions + +A skilled engineer takes around 40 minutes to disassemble, flash and reassemble +the whole device. + +# Steps to access the flash IC: + +* Unplug the main battery +* Remove the harddisk, CDROM, ExpressCard, SIM-card, SDcard, SmartCard, ... +* Open the bottom flap and remove the keyboard screw +* Remove the keyboard +* Remove the screen +* Remove the top enclosure +* Remove the CMOS battery +* Remove the speakers +* Remove WWAN and WIFI card +* Remove the CPU fan +* Unplug the power cable +* Remove the bottom enclosure +* Flip the mainboard and remove the main frame diff --git a/Documentation/mainboard/lenovo/xx20_series.md b/Documentation/mainboard/lenovo/xx20_series.md new file mode 100644 index 0000000..976a29b --- /dev/null +++ b/Documentation/mainboard/lenovo/xx20_series.md @@ -0,0 +1,48 @@ +# Lenovo Sandy Bridge series + +## Flashing coreboot +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Socketed flash | no | ++---------------------+--------------------+ +| Size | 8 MiB | ++---------------------+--------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| Write protection | No | ++---------------------+--------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------+ +| Internal flashing | Yes | ++---------------------+--------------------+ +``` + +## Installation instructions +* Update the EC firmware, as there's no support for EC updates in coreboot. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will destroy your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract BLOBs from vendor firmware. + If you want to flash the whole chip, you need BLOBs when building + coreboot. +* The shipped *Flash layout* allocates 3MiB to the BIOS region, which is the space + usable by coreboot. +* ROM chip size should be set to 8MiB. + +```eval_rst +Please also have a look at :doc:`../../flash_tutorial/index`. +``` + +## Flash layout +There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions. +On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS +region. The update is then written into the EC once. + +![][fl] + +[fl]: flashlayout_xx20.svg + diff --git a/Documentation/mainboard/lenovo/xx30_series.md b/Documentation/mainboard/lenovo/xx30_series.md new file mode 100644 index 0000000..e65a3f2 --- /dev/null +++ b/Documentation/mainboard/lenovo/xx30_series.md @@ -0,0 +1,76 @@ +# Lenovo Ivy Bridge series + +## Flashing coreboot +```eval_rst ++---------------------+--------------------------------+ +| Type | Value | ++=====================+================================+ +| Socketed flash | no | ++---------------------+--------------------------------+ +| Size | 8 MiB + 4MiB | ++---------------------+--------------------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------------------+ +| Package | SOIC-8 | ++---------------------+--------------------------------+ +| Write protection | No | ++---------------------+--------------------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------------------+ +| Internal flashing | Yes | ++---------------------+--------------------------------+ +``` + +## Installation instructions +* Update the EC firmware, as there's no support for EC updates in coreboot. +* Do **NOT** accidently swap pins or power on the board while a SPI flasher + is connected. It will permanently brick your device. +* It's recommended to only flash the BIOS region. In that case you don't + need to extract BLOBs from vendor firmware. + If you want to flash the whole chip, you need BLOBs when building + coreboot. +* The *Flash layout* shows that by default 7MiB of space are available for + the use with coreboot. +* In that case you only want to use a part of the BIOS region that must not + exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB. +* ROM chip size should be set to 12MiB. + +```eval_rst +Please also have a look at :doc:`../../flash_tutorial/index`. +``` + +## Splitting the coreboot.rom + +To split the coreboot.rom into two images (one for the 8MiB and one for the +4 MiB flash IC), run the following commands: + +```bash +dd of=top.rom bs=1M if=build/coreboot.rom skip=8 +dd of=bottom.rom bs=1M if=build/coreboot.rom count=8 +``` + +That gives one ROM for each flash IC, where *top.rom* is the upper part of the +flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part +of the flash image, that resides on the 8 MiB flash. + +## Dumping a full ROM + +If you flash externally you need to read both flash chips to get two images +(one for the 8MiB and one for the 4 MiB flash IC), and then run the following +command to concatenate the files: + +```bash +cat bottom.rom top.rom > firmware.rom +``` + +## Flash layout +There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and +BIOS region. These two flash ICs appear as a single 12MiB when flashing +internally. +On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS +region. The update is then written into the EC once. + +![][fl] + +[fl]: flashlayout_xx30.svg + -- To view, visit https://review.coreboot.org/27852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Gerrit-Change-Number: 27852 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: Documentation: Add basic flashing tutorial for Lenovo
by Philipp Deppenwiese (Code Review) 29 Sep '18

29 Sep '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27852 ) Change subject: Documentation: Add basic flashing tutorial for Lenovo ...................................................................... Patch Set 10: Code-Review+2 Looks good for the first version. We can later move it to specific section -- To view, visit https://review.coreboot.org/27852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Gerrit-Change-Number: 27852 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Sun, 30 Sep 2018 03:20:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Describe recommonmark's auto_toc_tree
by Philipp Deppenwiese (Code Review) 29 Sep '18

29 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28427 ) Change subject: Documentation: Describe recommonmark's auto_toc_tree ...................................................................... Documentation: Describe recommonmark's auto_toc_tree Explain recommonmark's auto_toc_tree and give an example to make writing documentation easier. Show an example what happens if the document isn't included in any toctree. Change-Id: I4938d8d292ea890caec6d396b4fa04da65e398f4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/28427 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Tom Hiller: Looks good to me, but someone else must approve diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index d57244a..0ba17e3 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -74,6 +74,32 @@ +------------+------------+-----------+ ``` #just a code block is enough +## TocTree + +To make sure that all documents are included into the final documentation, you +must reference each document from at least one *toctree*. The *toctree* must +only reference files in the same folder or in subfolders ! +To create a toctree, simply use a bullet list or numbered list with a single +reference. References in regular text aren't considered as *toctree* . +This feature is enabled by recommonmark's *enable_auto_toc_tree* . + +**Example toctree:** + +``` +* [Chapter 1](chapter1.md) +* [Chapter 2](chapter2.md) +* [Subchapter](sub/index.md) +``` + +``` +1. [Chapter 1](chapter1.md) +2. [Chapter 2](chapter2.md) +``` + +If you do only reference the document, but do not include it in any toctree, +you'll see the following warning: +**WARNING: document isn't included in any toctree** + [coreboot]: https://coreboot.org [Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation [shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild -- To view, visit https://review.coreboot.org/28427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I4938d8d292ea890caec6d396b4fa04da65e398f4 Gerrit-Change-Number: 28427 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: Documentation: Describe recommonmark's auto_toc_tree
by Philipp Deppenwiese (Code Review) 29 Sep '18

29 Sep '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28427 ) Change subject: Documentation: Describe recommonmark's auto_toc_tree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4938d8d292ea890caec6d396b4fa04da65e398f4 Gerrit-Change-Number: 28427 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 Sep 2018 03:18:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Disable auto_doc_ref
by Philipp Deppenwiese (Code Review) 29 Sep '18

29 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28550 ) Change subject: Documentation: Disable auto_doc_ref ...................................................................... Documentation: Disable auto_doc_ref According to recommonmark's documentation the enable_auto_doc_ref is deprecated. This is not true, as it's broken with Sphinx 1.6+ commit 12d639873953847de31ec99742b42e50e89ed58c. recommonmark bug report is here: https://github.com/rtfd/recommonmark/issues/73 Instead of using this feature, which doesn't support top level directories in the relative document path anyway, use the TOC tree or inline RST code. Disable auto_doc_ref and document how to reference documents. Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/28550 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Documentation/conf.py M Documentation/getting_started/writing_documentation.md 2 files changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Tom Hiller: Looks good to me, but someone else must approve diff --git a/Documentation/conf.py b/Documentation/conf.py index ff1ad9d..07868fa 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -183,7 +183,7 @@ from recommonmark.transform import AutoStructify app.add_config_value('recommonmark_config', { 'enable_auto_toc_tree': True, - 'enable_auto_doc_ref': True, + 'enable_auto_doc_ref': False, # broken in Sphinx 1.6+ 'enable_eval_rst': True, 'url_resolver': lambda url: '/' + url }, True) diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 027def9..d57244a 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -20,6 +20,9 @@ You will also need python-recommonmark for sphinx to be able to handle markdown documenation. +The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and +recommonmark 0.4.0. + ### Optional Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly! @@ -47,6 +50,11 @@ 12. Shouldn't cover implementation details; for details, the code is the reference. +## Referencing markdown documents + +Starting with Sphinx 1.6 recommonmark's *auto_doc_ref* feature is broken. +To reference documents use the TOC tree or inline RST code. + ## Markdown and Tables Under Sphinx markdown tables are not supported. Therefore you can use following -- To view, visit https://review.coreboot.org/28550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283 Gerrit-Change-Number: 28550 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: Documentation: Disable auto_doc_ref
by Philipp Deppenwiese (Code Review) 29 Sep '18

29 Sep '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28550 ) Change subject: Documentation: Disable auto_doc_ref ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283 Gerrit-Change-Number: 28550 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Sep 2018 03:18:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Documentation: add description for util/pmh7tool
by Philipp Deppenwiese (Code Review) 29 Sep '18

29 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28368 ) Change subject: Documentation: add description for util/pmh7tool ...................................................................... Documentation: add description for util/pmh7tool Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> Reviewed-on: https://review.coreboot.org/28368 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M Documentation/util.md M util/README.md A util/pmh7tool/description.md 3 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Tom Hiller: Looks good to me, but someone else must approve diff --git a/Documentation/util.md b/Documentation/util.md index 72355e3..59f2c3b 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -77,6 +77,9 @@ * __nvidia__ - nvidia blob parsers * __nvramtool__ - Reads and writes coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM. `C` +* __pmh7tool__ - Dumps, reads and writes PMH7 registers on Lenovo +ThinkPads. PMH7 is used for switching on and off the power of some +devices on the board such as dGPU. `C` * __post__ - Userspace utility that can be used to test POST cards. `C` * __qualcomm__ - CMM script to debug Qualcomm coreboot environments. `CMM` diff --git a/util/README.md b/util/README.md index 69ed11e..7cdb5e5 100644 --- a/util/README.md +++ b/util/README.md @@ -75,6 +75,9 @@ * __nvidia__ - nvidia blob parsers * __nvramtool__ - Reads and writes coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM. `C` +* __pmh7tool__ - Dumps, reads and writes PMH7 registers on Lenovo +ThinkPads. PMH7 is used for switching on and off the power of some +devices on the board such as dGPU. `C` * __post__ - Userspace utility that can be used to test POST cards. `C` * __qualcomm__ - CMM script to debug Qualcomm coreboot environments. `CMM` diff --git a/util/pmh7tool/description.md b/util/pmh7tool/description.md new file mode 100644 index 0000000..57290e3 --- /dev/null +++ b/util/pmh7tool/description.md @@ -0,0 +1 @@ +Dumps, reads and writes PMH7 registers on Lenovo ThinkPads. PMH7 is used for switching on and off the power of some devices on the board such as dGPU. `C` -- To view, visit https://review.coreboot.org/28368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09 Gerrit-Change-Number: 28368 Gerrit-PatchSet: 4 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit September 2018