coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/pch: Select Kconfig for ITSS polarity configuration
by build bot (Jenkins) (Code Review) 28 Sep '18

28 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28790 ) Change subject: soc/intel/common/pch: Select Kconfig for ITSS polarity configuration ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28790/2/src/soc/intel/common/block/gpio/Kco… File src/soc/intel/common/block/gpio/Kconfig: https://review.coreboot.org/#/c/28790/2/src/soc/intel/common/block/gpio/Kco… PS2, Line 14: # Each bit represents IRQx Active High Polarity Disable configuration: trailing whitespace -- To view, visit https://review.coreboot.org/28790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81e75e17ceb23c364b78300c3950144be1580700 Gerrit-Change-Number: 28790 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 Sep 2018 15:51:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
by Subrata Banik (Code Review) 28 Sep '18

28 Sep '18

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/28791 ) Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers ...................................................................... soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/itss.h 3 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/28791/2 -- To view, visit https://review.coreboot.org/28791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Gerrit-Change-Number: 28791 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
by Subrata Banik (Code Review) 28 Sep '18

28 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28791 Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers ...................................................................... soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/itss.h 3 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/28791/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9d9ca01..6a7cc17 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -21,19 +21,29 @@ #include <device/pci.h> #include <fsp/util.h> #include <intelblocks/chip.h> +#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <soc/acpi.h> #include <soc/interrupt.h> #include <soc/irq.h> +#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> void soc_init_pre_device(void *chip_info) { + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Perform silicon specific init. */ intel_silicon_init(); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + } void soc_fsp_load(void) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index c2c0745..980b7e6 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -30,6 +30,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/chip.h> +#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -38,6 +39,7 @@ #include <soc/interrupt.h> #include <soc/iomap.h> #include <soc/irq.h> +#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -168,8 +170,16 @@ void soc_init_pre_device(void *chip_info) { + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* swap enabled PCI ports in device tree if needed */ pcie_override_devicetree_after_silicon_init(); } diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h index 5ff9bb1..e6eb8b0 100644 --- a/src/soc/intel/skylake/include/soc/itss.h +++ b/src/soc/intel/skylake/include/soc/itss.h @@ -16,6 +16,9 @@ #ifndef SOC_INTEL_SKL_ITSS_H #define SOC_INTEL_SKL_ITSS_H +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) -- To view, visit https://review.coreboot.org/28791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Gerrit-Change-Number: 28791 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers
by Subrata Banik (Code Review) 28 Sep '18

28 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28792 Change subject: soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers ...................................................................... soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/include/soc/itss.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/28792/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 34a2fe0..fadd5f8 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -22,9 +22,11 @@ #include <fsp/util.h> #include <intelblocks/acpi.h> #include <intelblocks/chip.h> +#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> +#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> @@ -134,11 +136,18 @@ void soc_init_pre_device(void *chip_info) { + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h index 06dcc2e..0d8b2ca 100644 --- a/src/soc/intel/cannonlake/include/soc/itss.h +++ b/src/soc/intel/cannonlake/include/soc/itss.h @@ -16,6 +16,9 @@ #ifndef SOC_INTEL_CNL_ITSS_H #define SOC_INTEL_CNL_ITSS_H +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) -- To view, visit https://review.coreboot.org/28792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3 Gerrit-Change-Number: 28792 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/pch: Select Kconfig for ITSS polarity configuration
by Subrata Banik (Code Review) 28 Sep '18

28 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28790 Change subject: soc/intel/common/pch: Select Kconfig for ITSS polarity configuration ...................................................................... soc/intel/common/pch: Select Kconfig for ITSS polarity configuration This patch selects Kconfig for Intel Core Platform in order to ensure proper ITSS IPCx programming. Change-Id: I81e75e17ceb23c364b78300c3950144be1580700 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/pch/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28790/1 diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index 6d712e9..1811e25 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -10,8 +10,7 @@ help This option enables GPIO debug messages -# Used in small core SOCs to invert the polarity as ITSS only takes -# active high signals +# Use to invert the polarity as ITSS only takes active high signals config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG depends on SOC_INTEL_COMMON_BLOCK_GPIO bool diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 1157eb4..2bf6d68 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -23,6 +23,7 @@ select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG select SOC_INTEL_COMMON_BLOCK_GRAPHICS select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C -- To view, visit https://review.coreboot.org/28790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I81e75e17ceb23c364b78300c3950144be1580700 Gerrit-Change-Number: 28790 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: libpayload/drivers/usb/uhci: Fix regression
by build bot (Jenkins) (Code Review) 28 Sep '18

28 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23686 ) Change subject: libpayload/drivers/usb/uhci: Fix regression ...................................................................... Patch Set 3: (9 comments) https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… File payloads/libpayload/drivers/usb/uhci.c: https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 346: maxlen (min (mlen, len)) << TD_MAXLEN_SHIFT | space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 346: maxlen (min (mlen, len)) << TD_MAXLEN_SHIFT | space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 436: fill_schedule (&tds[i], ep, min (size, maxpsize), buf, space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 436: fill_schedule (&tds[i], ep, min (size, maxpsize), buf, space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 443: UHCI_INST (ep->dev->controller)->qh_data->elementlinkptr = space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 444: virt_to_phys (tds) & ~(FLISTP_QH | FLISTP_TERMINATE); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 445: td_t *td = wait_for_completed_qh (ep->dev->controller, space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 446: UHCI_INST (ep->dev->controller)->qh_data); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/23686/3/payloads/libpayload/drivers/usb/uhc… PS3, Line 448: td_dump (td); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/23686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I823521e24f6f9e04c86d36fda751c449cd884ce3 Gerrit-Change-Number: 23686 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 Sep 2018 13:18:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi/winbond: Add function to lock flash's status register
by build bot (Jenkins) (Code Review) 28 Sep '18

28 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28697 ) Change subject: drivers/spi/winbond: Add function to lock flash's status register ...................................................................... Patch Set 5: (8 comments) https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@540 PS5, Line 540: const enum spi_flash_status_reg_lockdown mode, code indent should use tabs where possible https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@541 PS5, Line 541: const bool non_volatile) code indent should use tabs where possible https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@555 PS5, Line 555: val = (union status_reg1_bp3){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}' https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@556 PS5, Line 556: mask = (union status_reg1_bp3){ .srp0 = 1 }.u; space required after that close brace '}' https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@558 PS5, Line 558: val = (union status_reg1_bp4){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}' https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@559 PS5, Line 559: mask = (union status_reg1_bp4){ .srp0 = 1 }.u; space required after that close brace '}' https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@566 PS5, Line 566: val = (union status_reg2){ .srp1 = !!(mode & 2) }.u; space required after that close brace '}' https://review.coreboot.org/#/c/28697/5/src/drivers/spi/winbond.c@567 PS5, Line 567: mask = (union status_reg2){ .srp1 = 1 }.u; space required after that close brace '}' -- To view, visit https://review.coreboot.org/28697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90e0fcdcf531b53c0fc1ffcfdb3b5ab522f088f5 Gerrit-Change-Number: 28697 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 Sep 2018 10:59:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review) 28 Sep '18

28 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 22: (7 comments) https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c@33 PS22, Line 33: #define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c@502 PS22, Line 502: val = (union status_reg1_bp3){ .bp = bp, .tb = tb, .sec = 0 }.u; space required after that close brace '}' https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c@503 PS22, Line 503: mask = (union status_reg1_bp3){ .bp = ~0, .tb = 1, .sec = 1 }.u; space required after that close brace '}' https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c@505 PS22, Line 505: val = (union status_reg1_bp4){ .bp = bp, .tb = tb }.u; space required after that close brace '}' https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c@506 PS22, Line 506: mask = (union status_reg1_bp4){ .bp = ~0, .tb = 1 }.u; space required after that close brace '}' https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c@513 PS22, Line 513: val = (union status_reg2){ .cmp = cmp }.u; space required after that close brace '}' https://review.coreboot.org/#/c/25105/22/src/drivers/spi/winbond.c@514 PS22, Line 514: mask = (union status_reg2){ .cmp = 1 }.u; space required after that close brace '}' -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 22 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Sep 2018 10:59:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium/cn81xx/spi: Add function to return SPI clock
by Patrick Rudolph (Code Review) 28 Sep '18

28 Sep '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28789 Change subject: soc/cavium/cn81xx/spi: Add function to return SPI clock ...................................................................... soc/cavium/cn81xx/spi: Add function to return SPI clock Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/include/soc/spi.h M src/soc/cavium/cn81xx/spi.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28789/1 diff --git a/src/soc/cavium/cn81xx/include/soc/spi.h b/src/soc/cavium/cn81xx/include/soc/spi.h index bb69daa..33f0f29 100644 --- a/src/soc/cavium/cn81xx/include/soc/spi.h +++ b/src/soc/cavium/cn81xx/include/soc/spi.h @@ -29,6 +29,7 @@ const size_t speed_hz, const size_t idle_low, const size_t idle_cycles); +uint64_t spi_get_clock(const size_t bus); void spi_set_lsbmsb(const size_t bus, const size_t lsb_first); void spi_init_custom(const size_t bus, const size_t speed_hz, diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 5a5865e..6527f22 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -218,6 +218,27 @@ } /** + * Get current SPI clock frequency in Hz. + * + * @param bus The SPI bus to operate on + */ +uint64_t spi_get_clock(const size_t bus) +{ + union cavium_spi_cfg cfg; + + assert(bus < ARRAY_SIZE(cavium_spi_slaves)); + if (bus >= ARRAY_SIZE(cavium_spi_slaves)) + return 0; + + struct cavium_spi *regs = cavium_spi_slaves[bus].regs; + const uint64_t sclk = thunderx_get_io_clock(); + + cfg.u = read64(&regs->cfg); + + return (sclk / (2ULL * cfg.s.clkdiv)); +} + +/** * Set SPI LSB/MSB first. * * @param bus The SPI bus to operate on -- To view, visit https://review.coreboot.org/28789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8 Gerrit-Change-Number: 28789 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: soc/intel/cannonlake: Move SkipMpInit config to FSPM
by Patrick Georgi (Code Review) 28 Sep '18

28 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28740 ) Change subject: soc/intel/cannonlake: Move SkipMpInit config to FSPM ...................................................................... soc/intel/cannonlake: Move SkipMpInit config to FSPM SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit UPD, hence change the settings in coreboot side as well. The old options in SiliconInit get deprecated, so leave the code as is will be harmless. Make the changes limited to coffeelake itself. Change-Id: If968de78117068668e4f0006c412442c50658ba9 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/28740 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index ae1ba4d..8bdabbf 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -22,6 +22,7 @@ #include <compiler.h> #include <console/console.h> #include <fsp/util.h> +#include <intelblocks/chip.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> #include <memory_info.h> @@ -175,6 +176,9 @@ m_cfg->VmxEnable = 0; else m_cfg->VmxEnable = config->VmxEnable; +#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) + m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); +#endif } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/28740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If968de78117068668e4f0006c412442c50658ba9 Gerrit-Change-Number: 28740 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2018