coreboot-gerrit September 2018

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Change in coreboot[master]: amd/stoneyridge: Load AOAC and USB gnvs values
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28767 Change subject: amd/stoneyridge: Load AOAC and USB gnvs values ...................................................................... amd/stoneyridge: Load AOAC and USB gnvs values Indicate the devices that are enabled. This is somewhat rudimentary, but could be improved in a later patch (e.g. get settings from devicetree). Calculate values that may be used for reinitializing the xHCI firmware. Add the EHCI BAR's current base address to gnvs. BUG=b:77602074 Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28767/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 3239842..1085310 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -429,6 +429,11 @@ uint16_t wake_from; }; +#define XHCI_FW_SIG_OFFSET 0xc +#define XHCI_FW_ADDR_OFFSET 0x6 +#define XHCI_FW_SIZE_OFFSET 0x8 +#define XHCI_FW_BOOTRAM_SIZE 0x8000 + void enable_aoac_devices(void); void sb_enable_rom(void); void configure_stoneyridge_i2c(void); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 8984c40..b122f83 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -886,6 +886,50 @@ sb_clear_pm1_status(); } +static void set_sb_final_nvs(void) +{ + uintptr_t amdfw_rom; + uintptr_t xhci_fw; + uintptr_t fwaddr; + size_t fwsize; + const struct device *sd, *sata, *ehci; + + struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs == NULL) + return; + + gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); + gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); + gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); + gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); + /* Rely on these being in sync with devicetree */ + sd = dev_find_slot(0, SD_DEVFN); + gnvs->aoac.st_e = sd && sd->enabled ? 1 : 0; + sata = dev_find_slot(0, SATA_DEVFN); + gnvs->aoac.sd_e = sata && sata->enabled ? 1 : 0; + gnvs->aoac.espi = 1; + + amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); + xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); + + fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + gnvs->fw00 = 0; + gnvs->fw01 = ((32 * KiB) << 16) + 0; + gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; + gnvs->fw03 = fwsize << 16; + + ehci = dev_find_slot(0, EHCI1_DEVFN); + gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) + & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} + void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; @@ -893,6 +937,8 @@ if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); + + set_sb_final_nvs(); } /* -- To view, visit https://review.coreboot.org/28767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Gerrit-Change-Number: 28767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add USB settings to gnvs
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28766 Change subject: amd/stoneyridge: Add USB settings to gnvs ...................................................................... amd/stoneyridge: Add USB settings to gnvs A later patch will rely on two USB settings from the BIOS. Add these to the global_gnvs_t structure. The first is a data that will be used to locate the xHCI firmware for reloading after a resume. Although the existing calculations will be somewhat simple, keeping this on the coreboot side will help in the event multiple FWs are eventually in the build. The second item is a usable EHCI base address that may be programmed during S3 suspend and resume. At the time the PTS and WAK code runs, the BAR will be clear. BUG=b:77602074 Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28766/1 diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index f77d108..6d38d6b 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -65,6 +65,11 @@ , 2, ESPI, 1, // ESPI, 27 , 4, + FW00, 16, // 0x35 - xHCI FW ROM addr, boot RAM + FW01, 32, // 0x37 - xHCI FW RAM addr, boot RAM + FW02, 16, // 0x3B - xHCI FW ROM addr, Instruction RAM + FW03, 32, // 0x3D - xHCI FW RAM addr, Instruction RAM + EH10, 32, // 0x41 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 667f6ef..8fa3236 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -52,7 +52,12 @@ uint8_t tpsv; /* 0x2F - Passive Threshold */ uint8_t tmax; /* 0x30 - CPU Tj_max */ aoac_devs_t aoac; /* 0x31 - AOAC device enables */ - uint8_t unused[203]; + uint16_t fw00; /* 0x35 - XhciFwRomAddr_Rom, Boot RAM */ + uint32_t fw01; /* 0x37 - XhciFwRamAddr_Rom, Boot RAM sz/base */ + uint16_t fw02; /* 0x3B - XhciFwRomAddr_Ram, Instr RAM */ + uint32_t fw03; /* 0x3D - XhciFwRomAddr_Ram, Instr RAM sz/base */ + uint32_t eh10; /* 0x41 - EHCI BAR */ + uint8_t unused[187]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/28766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Gerrit-Change-Number: 28766 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Create gnvs entries for AOAC devices
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28765 Change subject: amd/stoneyridge: Create gnvs entries for AOAC devices ...................................................................... amd/stoneyridge: Create gnvs entries for AOAC devices A later patch will leverage AMD's ASL support for handling AOAC devices. This will gather coreboot's device enables from a bitwise field, where each bit corresponds to the register offset used to control each devices. Create an identical structure, and add it to the nvs ASL and global_nvs_t structure. BUG=b:77602074 Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 3 files changed, 42 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28765/1 diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index ba50e38..f77d108 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -47,6 +47,24 @@ TCRT, 8, // 0x2E - Critical Threshold TPSV, 8, // 0x2F - Passive Threshold TMAX, 8, // 0x30 - CPU Tj_max + , 5, // 0x31 - AOAC Device Enables + IC0E, 1, // I2C0, 5 + IC1E, 1, // I2C1, 6 + IC2E, 1, // I2C2, 7 + IC3E, 1, // I2C3, 8 + , 2, + UT0E, 1, // UART0, 11 + UT1E, 1, // UART1, 12 + , 2, + ST_E, 1, // SATA, 15 + , 2, + EHCE, 1, // EHCI, 18 + , 4, + XHCE, 1, // XCHI, 23 + SD_E, 1, // SD, 24 + , 2, + ESPI, 1, // ESPI, 27 + , 4, /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index bcac3a9..667f6ef 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -28,6 +28,7 @@ #include <compiler.h> #include <stdint.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <soc/southbridge.h> typedef struct global_nvs_t { /* Miscellaneous */ @@ -50,7 +51,8 @@ uint8_t tcrt; /* 0x2E - Critical Threshold */ uint8_t tpsv; /* 0x2F - Passive Threshold */ uint8_t tmax; /* 0x30 - CPU Tj_max */ - uint8_t unused[207]; + aoac_devs_t aoac; /* 0x31 - AOAC device enables */ + uint8_t unused[203]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f054b3b..3239842 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -400,6 +400,27 @@ int status; }; +typedef struct aoac_devs { + int unused1:5; + int ic0e:1; /* 5: I2C0 */ + int ic1e:1; /* 6: I2C1 */ + int ic2e:1; /* 7: I2C2 */ + int ic3e:1; /* 8: I2C3 */ + int unused2:2; + int ut0e:1; /* 11: UART0 */ + int ut1e:1; /* 12: UART0 */ + int unused3:2; + int st_e:1; /* 15: SATA */ + int unused4:2; + int ehce:1; /* 18: EHCI */ + int unused5:4; + int xhce:1; /* 23: xHCI */ + int sd_e:1; /* 24: SDIO */ + int unused6:2; + int espi:1; /* 27: ESPI */ + int unused7:4; +} __packed aoac_devs_t; + struct soc_power_reg { uint16_t pm1_sts; uint16_t pm1_en; -- To view, visit https://review.coreboot.org/28765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Gerrit-Change-Number: 28765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Make gnvs ASL whitespace consistent
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28764 Change subject: amd/stoneyridge: Make gnvs ASL whitespace consistent ...................................................................... amd/stoneyridge: Make gnvs ASL whitespace consistent The globalnvs.asl file had become mixed with tabs and spaces to align columns. Use all tabs to align the comments. BUG=b:BUG=b:77602074 Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/globalnvs.asl 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28764/1 diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 7e696aa..ba50e38 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -28,19 +28,19 @@ { /* Miscellaneous */ Offset (0x00), - PCNT, 8, // 0x00 - Processor Count - PPCM, 8, // 0x01 - Max PPC State - LIDS, 8, // 0x02 - LID State - PWRS, 8, // 0x03 - AC Power State - DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console - PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index - GPEI, 64, // 0x11 - 0x18 - GPE Wake Source - NHLA, 64, // 0x19 - 0x20 - NHLT Address - NHLL, 32, // 0x21 - 0x24 - NHLT Length - PRT0, 32, // 0x25 - 0x28 - PERST_0 Address - SCDP, 8, // 0x29 - SD_CD GPIO portid - SCDO, 8, // 0x2A - GPIO pad offset relative to the community + PCNT, 8, // 0x00 - Processor Count + PPCM, 8, // 0x01 - Max PPC State + LIDS, 8, // 0x02 - LID State + PWRS, 8, // 0x03 - AC Power State + DPTE, 8, // 0x04 - Enable DPTF + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console + PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index + GPEI, 64, // 0x11 - 0x18 - GPE Wake Source + NHLA, 64, // 0x19 - 0x20 - NHLT Address + NHLL, 32, // 0x21 - 0x24 - NHLT Length + PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SCDP, 8, // 0x29 - SD_CD GPIO portid + SCDO, 8, // 0x2A - GPIO pad offset relative to the community TMPS, 8, // 0x2B - Temperature Sensor ID TLVL, 8, // 0x2C - Throttle Level Limit FLVL, 8, // 0x2D - Current FAN Level -- To view, visit https://review.coreboot.org/28764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Gerrit-Change-Number: 28764 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in libgfxinit[master]: WIP: Add Kaby Lake PCI IDs
by Nico Huber (Code Review) 27 Sep '18

27 Sep '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28763 Change subject: WIP: Add Kaby Lake PCI IDs ...................................................................... WIP: Add Kaby Lake PCI IDs Change-Id: Ice05e07b016cebc7258a9790e38e079e63227a4b --- M common/hw-gfx-gma-config.ads.template 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/63/28763/1 diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index dba10aa..bdeeefb 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -333,7 +333,8 @@ function Is_Skylake_U (Device_Id : Word16) return Boolean is (Device_Id = 16#1906# or Device_Id = 16#1916# or Device_Id = 16#1923# or - Device_Id = 16#1926# or Device_Id = 16#1927#); + Device_Id = 16#1926# or Device_Id = 16#1927# or + Device_Id = 16#5906# or Device_Id = 16#5916# or Device_Id = 16#5917#); -- Rather catch too much here than too little, -- it's only used to distinguish generations. @@ -360,7 +361,9 @@ when Skylake => ((Device_Id and 16#ffc3#) = 16#1902# or (Device_Id and 16#ffcf#) = 16#190b# or (Device_Id and 16#ffcf#) = 16#190d# or - (Device_Id and 16#fff9#) = 16#1921#) and + (Device_Id and 16#fff9#) = 16#1921# or + (Device_Id and 16#ffe3#) = 16#5902# or + (Device_Id and 16#fff1#) = 16#5911#) and (case CPU_Var is when Normal => not Is_Skylake_U (Device_Id), when ULT => Is_Skylake_U (Device_Id))); -- To view, visit https://review.coreboot.org/28763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ice05e07b016cebc7258a9790e38e079e63227a4b Gerrit-Change-Number: 28763 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names
by build bot (Jenkins) (Code Review) 27 Sep '18

27 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28751 ) Change subject: soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28751/2/src/soc/intel/fsp_broadwell_de/cpu.c File src/soc/intel/fsp_broadwell_de/cpu.c: https://review.coreboot.org/#/c/28751/2/src/soc/intel/fsp_broadwell_de/cpu.… PS2, Line 148: for (i = 0; i < num_banks; i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/28751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Gerrit-Change-Number: 28751 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 14:03:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/commom/block/i2c: Make I2C controller out of reset
by Subrata Banik (Code Review) 27 Sep '18

27 Sep '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28762 Change subject: soc/intel/commom/block/i2c: Make I2C controller out of reset ...................................................................... soc/intel/commom/block/i2c: Make I2C controller out of reset This patch ensures I2C controllers are out of reset without any assumptions. BUG=b:116191230 BRANCH=none TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT at reset (by reading Bit 0-1 as 3) Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/i2c/i2c.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/28762/1 diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 11bd018..917a060 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. + * Copyright 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -140,8 +140,11 @@ /* dev -> bar0 */ res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) + if (res) { + /* Take device out of reset */ + lpss_reset_release(res->base); return res->base; + } return (uintptr_t)NULL; } -- To view, visit https://review.coreboot.org/28762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc Gerrit-Change-Number: 28762 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: siemens/mc_apl1: Activate clock spreading for PTN3460
by Werner Zeh (Code Review) 27 Sep '18

27 Sep '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/28761 ) Change subject: siemens/mc_apl1: Activate clock spreading for PTN3460 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/28761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Gerrit-Change-Number: 28761 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 13:17:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl1: Activate clock spreading for PTN3460
by Mario Scheithauer (Code Review) 27 Sep '18

27 Sep '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/28761 ) Change subject: siemens/mc_apl1: Activate clock spreading for PTN3460 ...................................................................... Patch Set 3: I missed this, sorry. -- To view, visit https://review.coreboot.org/28761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Gerrit-Change-Number: 28761 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 12:35:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl1: Activate clock spreading for PTN3460
by Mario Scheithauer (Code Review) 27 Sep '18

27 Sep '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28761 to look at the new patch set (#3). Change subject: siemens/mc_apl1: Activate clock spreading for PTN3460 ...................................................................... siemens/mc_apl1: Activate clock spreading for PTN3460 In order to minimize Electromagnetic Interference (EMI) on the LVDS interface driven by PTN3460, clock spreading must be activated for mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal frequency. Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/28761/3 -- To view, visit https://review.coreboot.org/28761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Gerrit-Change-Number: 28761 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2018