coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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886 discussions

Change in coreboot[master]: payloads/Kconfig: do not show compression menu for FIT
by Patrick Georgi (Code Review) 26 Sep '18

26 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28732 ) Change subject: payloads/Kconfig: do not show compression menu for FIT ...................................................................... payloads/Kconfig: do not show compression menu for FIT FIT payloads do not support compression. Currently this would thrown an error like the following: E: FIT images don't support whole-image compression, compress the kernel component instead! With this patch, menuconfig will correctly *not* show payload compression for FIT payloads, and this will correctly set compression to NONE. Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef Signed-off-by: Andrea Barberio <insomniac(a)slackware.it> Reviewed-on: https://review.coreboot.org/28732 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M payloads/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/payloads/Kconfig b/payloads/Kconfig index 5e76ebe..8e05df3 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -64,7 +64,7 @@ choice prompt "Payload compression algorithm" default COMPRESSED_PAYLOAD_LZMA - depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT + depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT help Choose the compression algorithm for the chosen payloads. You can choose between LZMA and LZ4. -- To view, visit https://review.coreboot.org/28732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef Gerrit-Change-Number: 28732 Gerrit-PatchSet: 2 Gerrit-Owner: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/intel/model_206ax: detect number of MCE banks
by Patrick Georgi (Code Review) 26 Sep '18

26 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28443 ) Change subject: cpu/intel/model_206ax: detect number of MCE banks ...................................................................... cpu/intel/model_206ax: detect number of MCE banks My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset only 7. This causes Linux to spuriously log errors during boot and S3 resume. Fix this by reading the real value from the right MSR. Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com> Reviewed-on: https://review.coreboot.org/28443 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tristan Corrick <tristan(a)corrick.kiwi> Reviewed-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes HAOUAS: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Tristan Corrick: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 7cb4069..98203b6 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -39,6 +39,7 @@ #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401 +#define IA32_MCG_CAP 0x179 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 75631c1..3cc8d82 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,10 +414,14 @@ { msr_t msr; int i; + int num_banks; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ - for (i = 0; i < 7; i++) + for (i = 0; i < num_banks; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -- To view, visit https://review.coreboot.org/28443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Gerrit-Change-Number: 28443 Gerrit-PatchSet: 3 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/block: Don't use device_t
by Patrick Georgi (Code Review) 26 Sep '18

26 Sep '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28694 ) Change subject: soc/intel/common/block: Don't use device_t ...................................................................... soc/intel/common/block: Don't use device_t Use of device_t is deprecated. Change-Id: Id82059898844fbe20665250062b67652d6cc1f9e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28694 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index 197268b..050d93a 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -155,7 +155,7 @@ * This function returns a 1 or 0 depending on whether disable_busmaster * needs to be done for the specified device on S5 entry */ -int smihandler_soc_disable_busmaster(device_t dev); +int smihandler_soc_disable_busmaster(pci_devfn_t dev); /* SMI handlers that should be serviced in SCI mode too. */ uint32_t smihandler_soc_get_sci_mask(void); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index c6f9692..e4c13dd 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -46,7 +46,7 @@ return; } -__weak int smihandler_soc_disable_busmaster(device_t dev) +__weak int smihandler_soc_disable_busmaster(pci_devfn_t dev) { return 1; } -- To view, visit https://review.coreboot.org/28694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id82059898844fbe20665250062b67652d6cc1f9e Gerrit-Change-Number: 28694 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Martin Roth (Code Review) 26 Sep '18

26 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28690 ) Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" This reverts commit aef592d9b66aa18d83b0a211ead26013ff1f7d98. Reason for revert: Use values from driver instead of hardcoding in firmware (b:113303916) Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> Reviewed-on: https://review.coreboot.org/28690 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Enrico Granata <egranata(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Enrico Granata: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 109d2b6..37edd8a 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -334,13 +334,6 @@ register "desc" = ""SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A18_IRQ)" register "device_present_gpio" = "GPP_B20" - register "property_count" = "2" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""STH9321,reg_prox_ctrl6"" - register "property_list[0].integer" = "75" - register "property_list[1].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[1].name" = ""STH9321,reg_prox_ctrl7"" - register "property_list[1].integer" = "99" device i2c 28 on end end end # I2C #2 -- To view, visit https://review.coreboot.org/28690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 4 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl1: Make the DDR memory swizzle data configurable
by Werner Zeh (Code Review) 26 Sep '18

26 Sep '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/28730 ) Change subject: siemens/mc_apl1: Make the DDR memory swizzle data configurable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Gerrit-Change-Number: 28730 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Sep 2018 13:08:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl1: Make the DDR memory swizzle data configurable
by Mario Scheithauer (Code Review) 26 Sep '18

26 Sep '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/28730 ) Change subject: siemens/mc_apl1: Make the DDR memory swizzle data configurable ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28730/1/src/mainboard/siemens/mc_apl1/romst… File src/mainboard/siemens/mc_apl1/romstage.c: https://review.coreboot.org/#/c/28730/1/src/mainboard/siemens/mc_apl1/romst… PS1, Line 80: sz > You could just have used (size_t)DQ_BITS_PER_DQS here directly as you have to break the line anyway […] Done -- To view, visit https://review.coreboot.org/28730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Gerrit-Change-Number: 28730 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Sep 2018 13:06:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl1: Make the DDR memory swizzle data configurable
by Mario Scheithauer (Code Review) 26 Sep '18

26 Sep '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28730 to look at the new patch set (#2). Change subject: siemens/mc_apl1: Make the DDR memory swizzle data configurable ...................................................................... siemens/mc_apl1: Make the DDR memory swizzle data configurable In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/romstage.c M src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc M src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h A src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c 4 files changed, 142 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28730/2 -- To view, visit https://review.coreboot.org/28730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Gerrit-Change-Number: 28730 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl1: Add new mainboard variant mc_apl2
by Werner Zeh (Code Review) 26 Sep '18

26 Sep '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/28735 ) Change subject: siemens/mc_apl1: Add new mainboard variant mc_apl2 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Gerrit-Change-Number: 28735 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Sep 2018 12:46:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl1: Add new mainboard variant mc_apl2
by Mario Scheithauer (Code Review) 26 Sep '18

26 Sep '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/28735 ) Change subject: siemens/mc_apl1: Add new mainboard variant mc_apl2 ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/28735/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28735/1//COMMIT_MSG@10 PS1, Line 10: contains > "contains" or "is based on" Done https://review.coreboot.org/#/c/28735/1/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig: https://review.coreboot.org/#/c/28735/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 8: select DRIVER_SIEMENS_NC_F > We do not need the IO based UART here. […] Done https://review.coreboot.org/#/c/28735/1/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c: https://review.coreboot.org/#/c/28735/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 32: /* Set Master Enable for on-board PCI device. */ : dev = dev_find_device(PCI_VENDO > This is not needed as well but we can get rid of it in one of the next commits. You're right. We should go the same way as with the baseboard. -- To view, visit https://review.coreboot.org/28735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Gerrit-Change-Number: 28735 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Sep 2018 12:37:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl1: Add new mainboard variant mc_apl2
by Mario Scheithauer (Code Review) 26 Sep '18

26 Sep '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28735 to look at the new patch set (#2). Change subject: siemens/mc_apl1: Add new mainboard variant mc_apl2 ...................................................................... siemens/mc_apl1: Add new mainboard variant mc_apl2 This mainboard is based on mc_apl1 and uses a SMARC module. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c 6 files changed, 197 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28735/2 -- To view, visit https://review.coreboot.org/28735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Gerrit-Change-Number: 28735 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2018