coreboot-gerrit September 2018

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Change in coreboot[master]: vboot/S3_RESUME: should not check VBOOT_STARTS_IN_BOOTBLOCK
by Joel Kitching (Code Review) 26 Sep '18

26 Sep '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28750 Change subject: vboot/S3_RESUME: should not check VBOOT_STARTS_IN_BOOTBLOCK ...................................................................... vboot/S3_RESUME: should not check VBOOT_STARTS_IN_BOOTBLOCK BUG=b:114018226 TEST=None Change-Id: I6840c45604535089fa8410f03c69702bec91218f Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28750/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index a0e6a32..e56e590 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -310,7 +310,6 @@ * does verification of memory init and thus must ensure it resumes with * the same slot that it booted from. */ if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && - IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && vboot_platform_is_resuming()) ctx.flags |= VB2_CONTEXT_S3_RESUME; -- To view, visit https://review.coreboot.org/28750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6840c45604535089fa8410f03c69702bec91218f Gerrit-Change-Number: 28750 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: tpm2/tlcl_send_startup: correct TPM2_Startup error logic
by Joel Kitching (Code Review) 26 Sep '18

26 Sep '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28749 Change subject: tpm2/tlcl_send_startup: correct TPM2_Startup error logic ...................................................................... tpm2/tlcl_send_startup: correct TPM2_Startup error logic BUG=b:114018226 TEST=None Change-Id: Iffad582d5c19252dde1c9dc97fc7fd145944a3b3 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/tpm/tss/tcg-2.0/tss.c 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28749/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 7db746f..e6ec57c 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -61,14 +61,13 @@ startup.startup_type = type; response = tpm_process_command(TPM2_Startup, &startup); - if (response && response->hdr.tpm_code && - (response->hdr.tpm_code != TPM_RC_INITIALIZE)) { - printk(BIOS_INFO, "%s: Startup return code is %x\n", - __func__, response->hdr.tpm_code); - return TPM_E_IOERROR; + if (response && (response->hdr.tpm_code == 0 || + response->hdr.tpm_code == TPM_RC_INITIALIZE)) { + return TPM_SUCCESS; } - return TPM_SUCCESS; - + printk(BIOS_INFO, "%s: Startup return code is %x\n", + __func__, response->hdr.tpm_code); + return TPM_E_IOERROR; } uint32_t tlcl_resume(void) -- To view, visit https://review.coreboot.org/28749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iffad582d5c19252dde1c9dc97fc7fd145944a3b3 Gerrit-Change-Number: 28749 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: tpm/tpm_setup: fail on invalid result from tlcl_resume
by Joel Kitching (Code Review) 26 Sep '18

26 Sep '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28748 Change subject: tpm/tpm_setup: fail on invalid result from tlcl_resume ...................................................................... tpm/tpm_setup: fail on invalid result from tlcl_resume BUG=b:114018226 TEST=None Change-Id: I8f5df2b0119d35e4000fe62bf1bba6ca07f925f3 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/tpm/tspi/tspi.c 1 file changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28748/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 950e930..7782943 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -100,10 +100,24 @@ /* Handle special init for S3 resume path */ if (s3flag) { result = tlcl_resume(); - if (result == TPM_E_INVALID_POSTINIT) - printk(BIOS_INFO, "TPM: Already initialized.\n"); + switch (result) { + case TPM_SUCCESS: + break; - return TPM_SUCCESS; + case TPM_E_INVALID_POSTINIT: + /* + * We're on a platform where the TPM maintains power + * in S3, so it's already initialized. + */ + printk(BIOS_INFO, "TPM: Already initialized.\n"); + result = TPM_SUCCESS; + break; + + default: + printk(BIOS_ERR, "TPM: Resume failed.\n"); + break; + + goto out; } result = tlcl_startup(); -- To view, visit https://review.coreboot.org/28748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8f5df2b0119d35e4000fe62bf1bba6ca07f925f3 Gerrit-Change-Number: 28748 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: mb/google/octopus: Touchpad I2C CLK (405.25KHz)over spec(＜400KHz)
by Peichao Li (Code Review) 26 Sep '18

26 Sep '18

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/28747 Change subject: mb/google/octopus: Touchpad I2C CLK (405.25KHz)over spec(＜400KHz) ...................................................................... mb/google/octopus: Touchpad I2C CLK (405.25KHz)over spec(＜400KHz) Need to tune I2C bus 6 clock frequency under the 400KHz Bug=116543001 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 399.1KHz Change-Id: I95b535a6b429fc34961a4953004a1c51e53a9be6 Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/phaser/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28747/1 diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index f2824d8..2f6915e 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/28747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I95b535a6b429fc34961a4953004a1c51e53a9be6 Gerrit-Change-Number: 28747 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>

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Change in coreboot[master]: cpu: Use "cpu/x86/msr.h" for common IA-32 MSRs
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28744 ) Change subject: cpu: Use "cpu/x86/msr.h" for common IA-32 MSRs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ie454841b69d24026926041c22ab5118fbfb05a69 Gerrit-Change-Number: 28744 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28745 ) Change subject: nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I45b52bbeb2f81f4c064bba92286c3f61daba9612 Gerrit-Change-Number: 28745 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel: Use "cpu/x86/msr.h" for common IA-32 MSRs
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28746 ) Change subject: soc/intel: Use "cpu/x86/msr.h" for common IA-32 MSRs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Id9ef2dadca74f9f49d6711bd74235ed53c8a6500 Gerrit-Change-Number: 28746 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel: Use "cpu/x86/msr.h" for common IA-32 MSRs
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28746 Change subject: soc/intel: Use "cpu/x86/msr.h" for common IA-32 MSRs ...................................................................... soc/intel: Use "cpu/x86/msr.h" for common IA-32 MSRs Also correct IA-32 MSRs names. Change-Id: Id9ef2dadca74f9f49d6711bd74235ed53c8a6500 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/romstage/cache_as_ram.inc M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/ramstage.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/msr.h M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_baytrail/ramstage.c M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/ramstage.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/msr.h 28 files changed, 56 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/28746/1 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index caa3bbf..928679f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -54,7 +54,7 @@ REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), /* Disable support for MONITOR and MWAIT instructions */ - REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), + REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0), #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 689d4d5..dd60345 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -16,7 +16,6 @@ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -24,8 +23,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 486f5a3..e9925a2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -108,7 +108,7 @@ stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index dcb6296..9969d5d 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -17,6 +17,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/msr.h> #include "fmap_config.h" @@ -35,7 +36,6 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e -#define MCG_CAP_MSR 0x179 /* Save the BIST result. */ movl %eax, %ebp @@ -64,7 +64,7 @@ post_code(0x22) /* Zero the variable MTRRs. */ - movl $MCG_CAP_MSR, %ecx + movl $IA32_MCG_CAP, %ecx rdmsr movzx %al, %ebx /* First variable MTRR. */ diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 66fde22..f9c3014 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -60,9 +60,9 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ @@ -74,7 +74,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 85b04ac..5383fdf 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -175,7 +175,7 @@ msr_t msr_value; /* Need to make sure that all cores have microcode loaded. */ - msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID); + msr_value = rdmsr(IA32_BIOS_SIGN_ID); if (msr_value.hi == 0) intel_microcode_load_unlocked(pattrs->microcode_patch); diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 47e9bcd..ec0cbe3 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -17,8 +17,6 @@ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 -#define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -26,8 +24,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 20c09d5..a12db80 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -112,7 +112,7 @@ stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index b05a007..72dbca5 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -67,14 +67,14 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable Burst Mode */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi = 0; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of @@ -91,7 +91,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* ENV_SMM */ diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index ee1fd52..4c1b3fd 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -546,10 +546,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 41ce17c..c93d292 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,9 +18,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -32,26 +29,16 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRRphysBase_MSR 0x1f4 #define EMRRphysMask_MSR 0x1f5 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_EMRRphysBase_MSR 0x2f4 #define UNCORE_EMRRphysMask_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ba87045..1fdaf69 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -18,6 +18,7 @@ #include <chip.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> @@ -126,10 +127,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); } static void configure_c_states(void) diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 6617d7f..e3bd5f6 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -20,13 +20,6 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f9 #define MSR_VR_MISC_CONFIG2 0x636 #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 684f827..17b8dc0 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -17,6 +17,7 @@ #include <commonlib/helpers.h> #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h> @@ -306,7 +307,7 @@ wrmsr /* Set CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ wrmsr @@ -339,7 +340,7 @@ post_code(0x27) /* Cache is populated. Use mask 1 that will block evicts */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ or $1, %edx /* select mask 1 */ @@ -410,7 +411,7 @@ */ shl %cl, %eax subl $0x02, %eax - movl $MSR_IA32_L3_MASK_1, %ecx + movl $IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -419,12 +420,12 @@ * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $MSR_IA32_L3_MASK_2, %ecx + mov $IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set MSR_IA32_PQR_ASSOC = 0x02 + * Set IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -432,7 +433,7 @@ * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -444,11 +445,11 @@ cld rep stosl /* - * Set MSR_IA32_PQR_ASSOC = 0x01 + * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 86feddc..a4d16e8 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -15,6 +15,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/cr.h> #include <intelblocks/msr.h> @@ -80,7 +81,7 @@ wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr @@ -101,7 +102,7 @@ wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a049..ebbdabd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -95,7 +95,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -115,7 +115,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -135,7 +135,7 @@ perf_ctl.lo = msr.lo & 0xff00; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e1fc431..b7fe904 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,13 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK (1) -#define FEATURE_ENABLE_VMX (1 << 2) -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ @@ -46,16 +39,13 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) -#define IA32_MCG_CAP 0x179 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define MSR_IA32_PERF_CTL 0x199 -#define IA32_MISC_ENABLE 0x1a0 -/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ +/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 @@ -76,8 +66,6 @@ #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 -#define IA32_MC0_CTL 0x400 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) #define MSR_PKG_POWER_SKU_UNIT 0x606 @@ -122,11 +110,8 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -#define MSR_IA32_PQR_ASSOC 0x0c8f -/* MSR bits 33:32 encode slot number 0-3 */ -#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) -#define MSR_IA32_L3_MASK_1 0x0c91 -#define MSR_IA32_L3_MASK_2 0x0c92 +#define IA32_L3_MASK_1 0x0c91 +#define IA32_L3_MASK_2 0x0c92 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b7b5550..676fab7 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -44,9 +44,9 @@ /* Enable speed step. */ if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 4d1ac70..082117c 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -18,12 +18,8 @@ #ifndef _DENVERTON_NS_MSR_H_ #define _DENVERTON_NS_MSR_H_ -#define MSR_PLATFORM_ID 0x17 #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -35,26 +31,16 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index ea1d790..6a2ce1a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -16,13 +16,10 @@ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index fc50e64..f4cdaa8 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -107,7 +107,7 @@ stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 1e32262..4c91b0a 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -74,7 +74,7 @@ "Bay Trail-D (Desktop)", "Bay Trail-M (Mobile)", }; - msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID); + msr_t platform_id = rdmsr(IA32_PLATFORM_ID); uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK; printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ? diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index 66fde22..f9c3014 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -60,9 +60,9 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ @@ -74,7 +74,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index a50c839..a10e504 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -128,11 +128,10 @@ static void configure_mca(void) { msr_t msr; - const unsigned int mcg_cap_msr = 0x179; int i; int num_banks; - msr = rdmsr(mcg_cap_msr); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; /* TODO(adurbin): This should only be done on a cold boot. Also, some @@ -140,14 +139,17 @@ every bank. */ msr.lo = msr.hi = 0; for (i = 0; i < num_banks; i++) { - wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr); - wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr); - wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr); + /* Clear the machine check status */ + wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr); + wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr); } msr.lo = msr.hi = 0xffffffff; - for (i = 0; i < num_banks; i++) - wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr); + for (i = 0; i < num_banks; i++) { + /* Initialize machine checks */ + wrmsr(IA32_MC0_CTL + (i * 4), msr); + } } static void broadwell_de_core_init(struct device *cpu) diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index 6b87061..ed42fdf 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -18,12 +18,9 @@ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce -#define IA32_PERF_CTL 0x199 #define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_IA32_MC0_STATUS 0x400 #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 #define MSR_CONFIG_TDP_NOMINAL 0x648 diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c index 7165080..7b94268 100644 --- a/src/soc/intel/fsp_broadwell_de/ramstage.c +++ b/src/soc/intel/fsp_broadwell_de/ramstage.c @@ -76,7 +76,7 @@ printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 417c4bc..605dc00 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -353,10 +353,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 780f94f..6da9325 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -24,13 +24,6 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_DELAY_VALUE 0x13 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -- To view, visit https://review.coreboot.org/28746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id9ef2dadca74f9f49d6711bd74235ed53c8a6500 Gerrit-Change-Number: 28746 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28745 Change subject: nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs ...................................................................... nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs Also correct IA-32 MSRs names Change-Id: I45b52bbeb2f81f4c064bba92286c3f61daba9612 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/nehalem/early_init.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/28745/1 diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 0a9b408..1ebb2a5 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -110,11 +110,11 @@ m.lo = (m.lo & ~0xff) | reg8; wrmsr(IA32_PERF_CTL, m); - m = rdmsr(MSR_IA32_MISC_ENABLES); + m = rdmsr(IA32_MISC_ENABLE); m.hi &= ~0x00000040; m.lo |= 0x10000; - wrmsr(MSR_IA32_MISC_ENABLES, m); + wrmsr(IA32_MISC_ENABLE, m); } m = rdmsr(MSR_FSB_CLOCK_VCC); @@ -124,9 +124,9 @@ m.lo = (m.lo & ~0xff) | reg8; wrmsr(IA32_PERF_CTL, m); - m = rdmsr(MSR_IA32_MISC_ENABLES); + m = rdmsr(IA32_MISC_ENABLE); m.lo |= 0x10000; - wrmsr(MSR_IA32_MISC_ENABLES, m); + wrmsr(IA32_MISC_ENABLE, m); } void nehalem_early_initialization(int chipset_type) -- To view, visit https://review.coreboot.org/28745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I45b52bbeb2f81f4c064bba92286c3f61daba9612 Gerrit-Change-Number: 28745 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: cpu: Use "cpu/x86/msr.h" for common IA-32 MSRs
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28744 Change subject: cpu: Use "cpu/x86/msr.h" for common IA-32 MSRs ...................................................................... cpu: Use "cpu/x86/msr.h" for common IA-32 MSRs Also correct IA-32 MSRs names Change-Id: Ie454841b69d24026926041c22ab5118fbfb05a69 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/common_init.c M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/common.c M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/intel/speedstep/speedstep.c M src/cpu/intel/turbo/turbo.c M src/cpu/via/nano/nano_init.c M src/cpu/via/nano/update_ucode.c M src/cpu/via/nano/update_ucode.h M src/cpu/x86/pae/pgtbl.c M src/cpu/x86/sipi_vector.S M src/include/cpu/intel/l2_cache.h M src/include/cpu/intel/speedstep.h M src/include/cpu/intel/turbo.h 25 files changed, 41 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28744/1 diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 8dd8559..02eb0e2 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -20,10 +20,6 @@ #include <cpu/x86/msr.h> #include "common.h" -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) - void set_vmx(void) { struct cpuid_result regs; @@ -105,7 +101,7 @@ config->version = version; - msr.addrl = MSR_IA32_HWP_CAPABILITIES; + msr.addrl = IA32_HWP_CAPABILITIES; /* * Highest Performance: @@ -141,7 +137,7 @@ msr.bit_offset = 8; config->regs[CPPC_GUARANTEED_PERF] = msr; - msr.addrl = MSR_IA32_HWP_REQUEST; + msr.addrl = IA32_HWP_REQUEST; /* * Desired Performance Register: @@ -182,7 +178,7 @@ */ config->regs[CPPC_COUNTER_WRAP] = unsupported; - msr.addrl = MSR_IA32_MPERF; + msr.addrl = IA32_MPERF; /* * Reference Performance Counter Register: @@ -192,7 +188,7 @@ msr.bit_offset = 0; config->regs[CPPC_REF_PERF_COUNTER] = msr; - msr.addrl = MSR_IA32_APERF; + msr.addrl = IA32_APERF; /* * Delivered Performance Counter Register: @@ -200,7 +196,7 @@ */ config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; - msr.addrl = MSR_IA32_HWP_STATUS; + msr.addrl = IA32_HWP_STATUS; /* * Performance Limited Register: @@ -210,7 +206,7 @@ msr.bit_offset = 2; config->regs[CPPC_PERF_LIMITED] = msr; - msr.addrl = MSR_IA32_PM_ENABLE; + msr.addrl = IA32_PM_ENABLE; /* * CPPC Enable Register: diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index e65b370..020b72d 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -20,25 +20,12 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 87daeac..5dfe016 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -21,25 +21,12 @@ /* Rangeley bus clock is fixed at 100MHz */ #define RANGELEY_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8498c1a..4ccb1c1 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -35,25 +35,12 @@ #define HASWELL_BCLK 100 #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 24de43e..9219839 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -649,10 +649,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0d9169b..ce5dac4 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -190,7 +190,7 @@ const u32 sub_cstates = cpuid_edx(5); - msr = rdmsr(IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 3); /* TM1 enable */ if (tm2) msr.lo |= (1 << 13); /* TM2 enable */ @@ -220,11 +220,11 @@ if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) msr.hi &= ~(1 << (38 - 32)); - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); if (eist) { msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index dd7bbc8..6bf21fd 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -56,7 +56,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f87ba77..11d86cd 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,26 +20,13 @@ /* Nehalem bus clock is fixed at 133MHz */ #define NEHALEM_BCLK 133 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 322e814..222c2ed 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -231,10 +231,10 @@ msr_t msr; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c index 9775efb..1e832c8 100644 --- a/src/cpu/intel/model_206ax/common.c +++ b/src/cpu/intel/model_206ax/common.c @@ -19,8 +19,6 @@ #include <cpu/x86/msr.h> #include "model_206ax.h" -#define IA32_PLATFORM_ID 0x17 - int get_platform_id(void) { msr_t msr; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 7cb4069..09aa484 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -20,25 +20,12 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 75631c1..09ec0bc 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -401,10 +401,10 @@ msr_t msr; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 96830c4..8d68b9e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -58,7 +58,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a1433f6..9dd1223 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -59,7 +59,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 #define IA32_PECI_CTL 0x5a0 static void configure_misc(void) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index cf68ecf..7cc2ce1 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -37,10 +37,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK_BIT (1 << 0) -#define SMRR_ENABLE (1 << 3) - struct ied_header { char signature[10]; u32 size; diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 441f2a3..43d5b5a 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -72,7 +72,7 @@ msr = rdmsr(MSR_FSB_CLOCK_VCC); if ((msr.hi & (1 << (63 - 32))) && /* supported and */ - !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { + !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { /* not disabled */ params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); params->turbo.is_turbo = 1; diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 5583c46..c31f4c0 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -68,7 +68,7 @@ cpuid_regs = cpuid(CPUID_LEAF_PM); turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); if (!turbo_cap && turbo_en) { @@ -97,9 +97,9 @@ /* Only possible if turbo is available but hidden */ if (get_turbo_state() == TURBO_DISABLED) { /* Clear Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi &= ~H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_ENABLED); @@ -115,9 +115,9 @@ msr_t msr; /* Set Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi |= H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_UNAVAILABLE); diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 62c6316..985a3c7 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -28,9 +28,6 @@ #define MODEL_NANO_3000_B0 0x8 #define MODEL_NANO_3000_B2 0xa -#define MSR_IA32_PERF_STATUS 0x00000198 -#define MSR_IA32_PERF_CTL 0x00000199 -#define MSR_IA32_MISC_ENABLE 0x000001a0 #define NANO_MYSTERIOUS_MSR 0x120e static void nano_finish_fid_vid_transition(void) @@ -41,7 +38,7 @@ int cnt = 0; do { udelay(16); - msr = rdmsr(MSR_IA32_PERF_STATUS); + msr = rdmsr(IA32_PERF_STATUS); cnt++; if (cnt > 128) { printk(BIOS_WARNING, @@ -61,7 +58,7 @@ { msr_t msr; /* Get voltage and frequency info */ - msr = rdmsr(MSR_IA32_PERF_STATUS); + msr = rdmsr(IA32_PERF_STATUS); u8 min_fid = (msr.hi >> 24); u8 max_fid = (msr.hi >> 8) & 0xff; u8 min_vid = (msr.hi >> 16) & 0xff; @@ -78,7 +75,7 @@ /* Set highest frequency and VID */ msr.lo = msr.hi; msr.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, msr); + wrmsr(IA32_PERF_CTL, msr); /* Wait for the transition to complete, otherwise, the CPU * might reset itself repeatedly */ nano_finish_fid_vid_transition(); @@ -96,9 +93,9 @@ { msr_t msr; /* Enable Powersaver */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable 6 bit or 7-bit VRM support * This MSR is not documented by VIA docs, other than setting these @@ -116,24 +113,24 @@ nano_set_max_fid_vid(); /* Enable TM3 */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= ( (1 << 3) | (1 << 13) ); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); u8 stepping = ( cpuid_eax(0x1) ) &0xf; if (stepping >= MODEL_NANO_3000_B0) { /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ msr.hi |= (1 << 0); /* C4e */ - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); } /* Lock on Powersaver */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 20); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); } static void nano_init(struct device *dev) diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 7c631a6..b8bfd7d 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -32,7 +32,7 @@ * not the header. The header is just there to help us. */ msr.lo = (unsigned int)(&(ucode->ucode_start)); msr.hi = 0; - wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + wrmsr(IA32_BIOS_UPDT_TRIG, msr); /* Let's see if we updated successfully */ msr = rdmsr(MSR_UCODE_UPDATE_STATUS); diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index 09f4d76..9a620ac 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -19,8 +19,6 @@ #include <console/console.h> #include <cpu/cpu.h> -#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 -#define MSR_IA32_BIOS_SIGN_ID 0x0000008b #define MSR_UCODE_UPDATE_STATUS 0x00001205 #define NANO_UCODE_SIGNATURE 0x53415252 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index cf6bf16..3c1a336 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -184,7 +184,7 @@ msr_t msr; msr.lo = pat; msr.hi = pat >> 32; - wrmsr(MSR_IA32_PAT, msr); + wrmsr(IA32_PAT, msr); } /* PAT encoding used in util/x86/x86_page_tables.go. It matches the linux diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba5ae3e..a7e4522 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -16,6 +16,7 @@ #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> +#include <cpu/x86/msr.h> /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into @@ -25,9 +26,6 @@ #define CODE_SEG 0x10 #define DATA_SEG 0x18 -#define IA32_UPDT_TRIG 0x79 -#define IA32_BIOS_SIGN_ID 0x8b - .section ".module_parameters", "aw", @progbits ap_start_params: gdtaddr: @@ -145,7 +143,7 @@ load_microcode: /* Load new microcode. */ - mov $IA32_UPDT_TRIG, %ecx + mov $IA32_BIOS_UPDT_TRIG, %ecx xor %edx, %edx mov %edi, %eax /* The microcode pointer is passed in pointing to the header. Adjust diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 35059ff..1303148 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -27,7 +27,6 @@ #ifndef __P6_L2_CACHE_H #define __P6_L2_CACHE_H -#define IA32_PLATFORM_ID 0x17 #define EBL_CR_POWERON 0x2A #define BBL_CR_D0 0x88 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 4b556b7..d357baf 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -35,11 +35,11 @@ /* Speedstep related MSRs */ -#define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STATUS 0x198 -#define IA32_PERF_CTL 0x199 -#define MSR_THERM2_CTL 0x19D -#define IA32_MISC_ENABLES 0x1A0 +#define IA32_PLATFORM_ID 0x017 +#define IA32_PERF_STATUS 0x198 +#define IA32_PERF_CTL 0x199 +#define MSR_THERM2_CTL 0x19D +#define IA32_MISC_ENABLE 0x1A0 #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 58f4831..0880ebb 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -20,7 +20,6 @@ #define CPUID_LEAF_PM 6 #define PM_CAP_TURBO_MODE (1 << 1) -#define MSR_IA32_MISC_ENABLES 0x1a0 /* Disable the Monitor Mwait FSM feature */ #define MONITOR_MWAIT_DIS_MASK 0x40000 -- To view, visit https://review.coreboot.org/28744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie454841b69d24026926041c22ab5118fbfb05a69 Gerrit-Change-Number: 28744 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit September 2018