coreboot-gerrit September 2018

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Change in coreboot[master]: src/vendorcode/amd/pi/00670F00/Lib: Remove folder
by Richard Spiegel (Code Review) 25 Sep '18

25 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28737 Change subject: src/vendorcode/amd/pi/00670F00/Lib: Remove folder ...................................................................... src/vendorcode/amd/pi/00670F00/Lib: Remove folder Now that the last dependency was resolved, remove AmdLib folder. BUG=b:112525011 TEST=Build and boot grunt. Change-Id: I3530857b872d0cb5ed2e3f3a294cc50b45ff6969 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/pi/heapmanager.c M src/soc/amd/stoneyridge/BiosCallOuts.c D src/vendorcode/amd/pi/00670F00/Lib/amdlib.c D src/vendorcode/amd/pi/00670F00/Lib/amdlib.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h 6 files changed, 0 insertions(+), 779 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28737/1 diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 54508fe..56bd866 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -19,7 +19,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <timer.h> -#include <amdlib.h> #include <amdblocks/BiosCallOuts.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index cbffb77..e6a0c46 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -13,7 +13,6 @@ #include <amdblocks/agesawrapper.h> -#include <amdlib.h> #include <arch/acpi.h> #include <amdblocks/BiosCallOuts.h> #include <cbmem.h> diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 9f74e8f..027ba4e 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -24,7 +24,6 @@ #include <stdlib.h> #include <amdblocks/agesawrapper.h> -#include <amdlib.h> #include <amdblocks/dimm_spd.h> #include "chip.h" #include <amdblocks/car.h> diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c deleted file mode 100644 index 8a4113f..0000000 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c +++ /dev/null @@ -1,573 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Library - * - * Contains interface to the AMD AGESA library - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Lib - * @e \$Revision: 48409 $ @e \$Date: 2011-03-08 11:19:40 -0600 (Tue, 08 Mar 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2011, Advanced Micro Devices, Inc. - * 2013 - 2014, Sage Electronic Engineering, LLC - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#include <AGESA.h> -#include <cpuRegisters.h> -#include "amdlib.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#if !defined(AMDLIB_OPTIMIZE) - #define AMDLIB_OPTIMIZE -#endif - -BOOLEAN -STATIC -GetPciMmioAddress ( - OUT UINT64 *MmioAddress, - OUT UINT32 *MmioSize, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -CpuidRead ( - IN UINT32 CpuidFcnAddress, - OUT CPUID_DATA *Value - ); - -UINT8 -ReadNumberOfCpuCores( - void - ); - -AMDLIB_OPTIMIZE -UINT8 -ReadIo8 ( - IN UINT16 Address - ) -{ - return __inbyte (Address); -} - -AMDLIB_OPTIMIZE -UINT16 -ReadIo16 ( - IN UINT16 Address - ) -{ - return __inword (Address); -} - -AMDLIB_OPTIMIZE -UINT32 -ReadIo32 ( - IN UINT16 Address - ) -{ - return __indword (Address); -} - -AMDLIB_OPTIMIZE -VOID -WriteIo8 ( - IN UINT16 Address, - IN UINT8 Data - ) -{ - __outbyte (Address, Data); -} - -AMDLIB_OPTIMIZE -VOID -WriteIo16 ( - IN UINT16 Address, - IN UINT16 Data - ) -{ - __outword (Address, Data); -} - -AMDLIB_OPTIMIZE -VOID -WriteIo32 ( - IN UINT16 Address, - IN UINT32 Data - ) -{ - __outdword (Address, Data); -} - -AMDLIB_OPTIMIZE -STATIC -UINT64 SetFsBase ( - UINT64 address - ) -{ - UINT64 hwcr; - hwcr = __readmsr (0xC0010015); - __writemsr (0xC0010015, hwcr | 1 << 17); - __writemsr (0xC0000100, address); - return hwcr; -} - -AMDLIB_OPTIMIZE -STATIC -VOID -RestoreHwcr ( - UINT64 - value - ) -{ - __writemsr (0xC0010015, value); -} - -AMDLIB_OPTIMIZE -UINT8 -Read64Mem8 ( - IN UINT64 Address - ) -{ - UINT8 dataRead; - UINT64 hwcrSave; - if ((Address >> 32) == 0) { - return *(volatile UINT8 *) (UINTN) Address; - } - hwcrSave = SetFsBase (Address); - dataRead = __readfsbyte (0); - RestoreHwcr (hwcrSave); - return dataRead; -} - -AMDLIB_OPTIMIZE -UINT16 -Read64Mem16 ( - IN UINT64 Address - ) -{ - UINT16 dataRead; - UINT64 hwcrSave; - if ((Address >> 32) == 0) { - return *(volatile UINT16 *) (UINTN) Address; - } - hwcrSave = SetFsBase (Address); - dataRead = __readfsword (0); - RestoreHwcr (hwcrSave); - return dataRead; -} - -AMDLIB_OPTIMIZE -UINT32 -Read64Mem32 ( - IN UINT64 Address - ) -{ - UINT32 dataRead; - UINT64 hwcrSave; - if ((Address >> 32) == 0) { - return *(volatile UINT32 *) (UINTN) Address; - } - hwcrSave = SetFsBase (Address); - dataRead = __readfsdword (0); - RestoreHwcr (hwcrSave); - return dataRead; - } - -AMDLIB_OPTIMIZE -VOID -Write64Mem8 ( - IN UINT64 Address, - IN UINT8 Data - ) -{ - if ((Address >> 32) == 0){ - *(volatile UINT8 *) (UINTN) Address = Data; - } - else { - UINT64 hwcrSave; - hwcrSave = SetFsBase (Address); - __writefsbyte (0, Data); - RestoreHwcr (hwcrSave); - } -} - -AMDLIB_OPTIMIZE -VOID -Write64Mem16 ( - IN UINT64 Address, - IN UINT16 Data - ) -{ - if ((Address >> 32) == 0){ - *(volatile UINT16 *) (UINTN) Address = Data; - } - else { - UINT64 hwcrSave; - hwcrSave = SetFsBase (Address); - __writefsword (0, Data); - RestoreHwcr (hwcrSave); - } -} - -AMDLIB_OPTIMIZE -VOID -Write64Mem32 ( - IN UINT64 Address, - IN UINT32 Data - ) -{ - if ((Address >> 32) == 0){ - *(volatile UINT32 *) (UINTN) Address = Data; - } - else { - UINT64 hwcrSave; - hwcrSave = SetFsBase (Address); - __writefsdword (0, Data); - RestoreHwcr (hwcrSave); - } -} - -AMDLIB_OPTIMIZE -VOID -LibAmdMsrRead ( - IN UINT32 MsrAddress, - OUT UINT64 *Value, - IN OUT AMD_CONFIG_PARAMS *ConfigPtr - ) -{ - *Value = __readmsr (MsrAddress); -} - -AMDLIB_OPTIMIZE -VOID -LibAmdMsrWrite ( - IN UINT32 MsrAddress, - IN UINT64 *Value, - IN OUT AMD_CONFIG_PARAMS *ConfigPtr - ) -{ - __writemsr (MsrAddress, *Value); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Read IO port - * - * - * @param[in] AccessWidth Access width - * @param[in] IoAddress IO port address - * @param[in] Value Pointer to save data - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdIoRead ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - OUT VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - switch (AccessWidth) { - case AccessWidth8: - case AccessS3SaveWidth8: - *(UINT8 *) Value = ReadIo8 (IoAddress); - break; - case AccessWidth16: - case AccessS3SaveWidth16: - *(UINT16 *) Value = ReadIo16 (IoAddress); - break; - case AccessWidth32: - case AccessS3SaveWidth32: - *(UINT32 *) Value = ReadIo32 (IoAddress); - break; - default: - ASSERT (FALSE); - break; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Write IO port - * - * - * @param[in] AccessWidth Access width - * @param[in] IoAddress IO port address - * @param[in] Value Pointer to data - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdIoWrite ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - IN CONST VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - switch (AccessWidth) { - case AccessWidth8: - case AccessS3SaveWidth8: - WriteIo8 (IoAddress, *(UINT8 *) Value); - break; - case AccessWidth16: - case AccessS3SaveWidth16: - WriteIo16 (IoAddress, *(UINT16 *) Value); - break; - case AccessWidth32: - case AccessS3SaveWidth32: - WriteIo32 (IoAddress, *(UINT32 *) Value); - break; - default: - ASSERT (FALSE); - break; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Read memory/MMIO - * - * - * @param[in] AccessWidth Access width - * @param[in] MemAddress Memory address - * @param[in] Value Pointer to data - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdMemRead ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - OUT VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - switch (AccessWidth) { - case AccessWidth8: - case AccessS3SaveWidth8: - *(UINT8 *) Value = Read64Mem8 (MemAddress); - break; - case AccessWidth16: - case AccessS3SaveWidth16: - *(UINT16 *) Value = Read64Mem16 (MemAddress); - break; - case AccessWidth32: - case AccessS3SaveWidth32: - *(UINT32 *) Value = Read64Mem32 (MemAddress); - break; - default: - ASSERT (FALSE); - break; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Write memory/MMIO - * - * - * @param[in] AccessWidth Access width - * @param[in] MemAddress Memory address - * @param[in] Value Pointer to data - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdMemWrite ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - IN CONST VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - - switch (AccessWidth) { - case AccessWidth8: - case AccessS3SaveWidth8: - Write64Mem8 (MemAddress, *((UINT8 *) Value)); - break; - case AccessWidth16: - case AccessS3SaveWidth16: - Write64Mem16 (MemAddress, *((UINT16 *) Value)); - break; - case AccessWidth32: - case AccessS3SaveWidth32: - Write64Mem32 (MemAddress, *((UINT32 *) Value)); - break; - default: - ASSERT (FALSE); - break; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Read PCI config space - * - * - * @param[in] AccessWidth Access width - * @param[in] PciAddress Pci address - * @param[in] Value Pointer to data - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdPciRead ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - OUT VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LegacyPciAccess; - UINT32 MMIOSize; - UINT64 RMWrite; - UINT64 RMWritePrevious; - UINT64 MMIOAddress; - - - ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); - if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, NULL)) { - // We need to convert our "portable" PCI address into a "real" PCI access - LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); - if (PciAddress.Address.Register <= 0xFF) { - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); - LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); - } else { - LibAmdMsrRead (NB_CFG, &RMWritePrevious, NULL); - RMWrite = RMWritePrevious | 0x0000400000000000; - LibAmdMsrWrite (NB_CFG, &RMWrite, NULL); - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); - LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); - LibAmdMsrWrite (NB_CFG, &RMWritePrevious, NULL); - } - //IDS_HDT_CONSOLE (LIB_PCI_RD, "~PCI RD %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - } else { - // Setup the MMIO address - ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); - MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); - LibAmdMemRead (AccessWidth, MMIOAddress, Value, NULL); - //IDS_HDT_CONSOLE (LIB_PCI_RD, "~MMIO RD %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Write PCI config space - * - * - * @param[in] AccessWidth Access width - * @param[in] PciAddress Pci address - * @param[in] Value Pointer to data - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdPciWrite ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN CONST VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LegacyPciAccess; - UINT32 MMIOSize; - UINT64 RMWrite; - UINT64 RMWritePrevious; - UINT64 MMIOAddress; - - - ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); - if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, NULL)) { - // We need to convert our "portable" PCI address into a "real" PCI access - LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); - if (PciAddress.Address.Register <= 0xFF) { - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); - LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); - } else { - LibAmdMsrRead (NB_CFG, &RMWritePrevious, NULL); - RMWrite = RMWritePrevious | 0x0000400000000000; - LibAmdMsrWrite (NB_CFG, &RMWrite, NULL); - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); - LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); - LibAmdMsrWrite (NB_CFG, &RMWritePrevious, NULL); - } - //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); - } else { - // Setup the MMIO address - ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); - MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); - LibAmdMemWrite (AccessWidth, MMIOAddress, Value, NULL); - //IDS_HDT_CONSOLE (LIB_PCI_WR, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); - //printk(BIOS_DEBUG, "LibAmdPciWrite mmio\n"); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get MMIO base address for PCI accesses - * - * @param[out] MmioAddress PCI MMIO base address - * @param[out] MmioSize Size of region in bytes - * @param[in] StdHeader Standard configuration header - * - * @retval TRUE MmioAddress/MmioSize are valid - */ -BOOLEAN -STATIC -GetPciMmioAddress ( - OUT UINT64 *MmioAddress, - OUT UINT32 *MmioSize, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN MmioIsEnabled; - UINT32 EncodedSize; - UINT64 LocalMsrRegister; - - MmioIsEnabled = FALSE; - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, NULL); - if ((LocalMsrRegister & BIT0) != 0) { - *MmioAddress = LocalMsrRegister & 0xFFFFFFFFFFF00000; - EncodedSize = (UINT32) ((LocalMsrRegister & 0x3C) >> 2); - *MmioSize = ((1 << EncodedSize) * 0x100000); - MmioIsEnabled = TRUE; - } - return MmioIsEnabled; -} diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h deleted file mode 100644 index fc97213..0000000 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h +++ /dev/null @@ -1,202 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Library - * - * Contains interface to the AMD AGESA library - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Lib - * @e \$Revision: 85030 $ @e \$Date: 2012-12-26 00:20:10 -0600 (Wed, 26 Dec 2012) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * 2013 - 2014, Sage Electronic Engineering, LLC - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - **/ - -#ifndef _AMD_LIB_H_ -#define _AMD_LIB_H_ - -#include <agesa_headers.h> - -#define IOCF8 0xCF8 -#define IOCFC 0xCFC - -// Reg Values for ReadCpuReg and WriteCpuReg -#define CR4_REG 0x04 -#define DR0_REG 0x10 -#define DR1_REG 0x11 -#define DR2_REG 0x12 -#define DR3_REG 0x13 -#define DR7_REG 0x17 - -// PROTOTYPES FOR amdlib32.asm -UINT8 -ReadIo8 ( - IN UINT16 Address - ); - -UINT16 -ReadIo16 ( - IN UINT16 Address - ); - -UINT32 -ReadIo32 ( - IN UINT16 Address - ); - -VOID -WriteIo8 ( - IN UINT16 Address, - IN UINT8 Data - ); - -VOID -WriteIo16 ( - IN UINT16 Address, - IN UINT16 Data - ); - -VOID -WriteIo32 ( - IN UINT16 Address, - IN UINT32 Data - ); - -UINT8 -Read64Mem8 ( - IN UINT64 Address - ); - -UINT16 -Read64Mem16 ( - IN UINT64 Address - ); - -UINT32 -Read64Mem32 ( - IN UINT64 Address - ); - -VOID -Write64Mem8 ( - IN UINT64 Address, - IN UINT8 Data - ); - -VOID -Write64Mem16 ( - IN UINT64 Address, - IN UINT16 Data - ); - -VOID -Write64Mem32 ( - IN UINT64 Address, - IN UINT32 Data - ); - -// MSR -VOID -LibAmdMsrRead ( - IN UINT32 MsrAddress, - OUT UINT64 *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdMsrWrite ( - IN UINT32 MsrAddress, - IN UINT64 *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -// IO -VOID -LibAmdIoRead ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - OUT VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdIoWrite ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - IN CONST VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -// Memory or MMIO -VOID -LibAmdMemRead ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - OUT VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdMemWrite ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - IN CONST VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -// PCI -VOID -LibAmdPciRead ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - OUT VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdPciWrite ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN CONST VOID *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -// CPUID -VOID -LibAmdCpuidRead ( - IN UINT32 CpuidFcnAddress, - OUT CPUID_DATA *Value, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h index 118473c..2d5de64 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h @@ -108,7 +108,6 @@ #endif #include "Fch.h" -#include "amdlib.h" #include "FchCommonCfg.h" #include "AmdFch.h" -- To view, visit https://review.coreboot.org/28737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3530857b872d0cb5ed2e3f3a294cc50b45ff6969 Gerrit-Change-Number: 28737 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/nocturne: Change IMX319 sensor link freq
by Lijian Zhao (Code Review) 25 Sep '18

25 Sep '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28736 Change subject: mb/google/nocturne: Change IMX319 sensor link freq ...................................................................... mb/google/nocturne: Change IMX319 sensor link freq Change link frequency of IMX319 from 360Mhz to 482.4 Mhz. Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28736/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl index ec4430d..1213270 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl @@ -105,7 +105,7 @@ Package () { 1, 2, 3, 4 } }, Package () { "link-frequencies", - Package() { 360000000 } + Package() { 482400000 } }, Package () { "remote-endpoint", Package() { \_SB.PCI0.CIO2, 0, 0 } -- To view, visit https://review.coreboot.org/28736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Gerrit-Change-Number: 28736 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Change in coreboot[master]: siemens/mc_apl1: Add new mainboard variant mc_apl2
by Mario Scheithauer (Code Review) 25 Sep '18

25 Sep '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28735 Change subject: siemens/mc_apl1: Add new mainboard variant mc_apl2 ...................................................................... siemens/mc_apl1: Add new mainboard variant mc_apl2 This mainboard is based on mc_apl1 and uses a SMARC module. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c 6 files changed, 201 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28735/1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 97ba66f..783207c 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -17,10 +17,12 @@ config VARIANT_DIR string default "mc_apl1" if BOARD_SIEMENS_MC_APL1 + default "mc_apl2" if BOARD_SIEMENS_MC_APL2 config MAINBOARD_PART_NUMBER string default "MC APL1" if BOARD_SIEMENS_MC_APL1 + default "MC APL2" if BOARD_SIEMENS_MC_APL2 config MAX_CPUS int diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 112bbb3..7f5f263 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -1,3 +1,7 @@ config BOARD_SIEMENS_MC_APL1 - bool "MC APL1" + bool "-> MC APL1" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL2 + bool "-> MC APL2" select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig new file mode 100644 index 0000000..fd5f2fd --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -0,0 +1,15 @@ + +if BOARD_SIEMENS_MC_APL2 + +config BOARD_SIEMENS_MC_APL2_VAR + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVERS_UART_8250IO + select DRIVER_SIEMENS_NC_FPGA + +config DEVICETREE + string + default "variants/mc_apl2/devicetree.cb" + +endif # BOARD_SIEMENS_MC_APL2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb new file mode 100644 index 0000000..42c4310 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -0,0 +1,109 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Disable all clkreq of PCIe root ports as SMARC interface do not + # have this pins. + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 on end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c new file mode 100644 index 0000000..cc377b5 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <hwilib.h> +#include <intelblocks/lpc_lib.h> +#include <timer.h> +#include <timestamp.h> +#include <baseboard/variants.h> + +void variant_mainboard_final(void) +{ + struct device *dev; + uint16_t cmd = 0; + + /* Enable additional I/O decoding range on LPC for COM 2 */ + lpc_open_pmio_window(0x2f8, 8); + + /* Set Master Enable for on-board PCI device. */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); + if (dev) { + cmd = pci_read_config16(dev, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, cmd); + } +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); -- To view, visit https://review.coreboot.org/28735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Gerrit-Change-Number: 28735 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: Documentation/lib/payloads/fit.md: Consistently indent with tabs
by Jonathan Neuschäfer (Code Review) 25 Sep '18

25 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28734 Change subject: Documentation/lib/payloads/fit.md: Consistently indent with tabs ...................................................................... Documentation/lib/payloads/fit.md: Consistently indent with tabs Sphinx displays a tab as four spaces, which makes code indented with eight spaces per level stand out. Format the example configuration file in fit.md consistently with tabs to make it look consistent everywhere. Change-Id: Ia1d4c44e68e5267bac1f0f558421c6a0c7a9329c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/lib/payloads/fit.md 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28734/1 diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index 22a50db..ac7b3e6 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -122,17 +122,17 @@ }; }; ramdisk-1 { - description = "Compressed Initramfs"; - data = /incbin/("initramfs.cpio.xz"); - type = "ramdisk"; - arch = "arm64"; - os = "linux"; - compression = "none"; - load = <00000000>; - entry = <00000000>; - hash-1 { - algo = "sha1"; - }; + description = "Compressed Initramfs"; + data = /incbin/("initramfs.cpio.xz"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "none"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "sha1"; + }; }; }; -- To view, visit https://review.coreboot.org/28734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia1d4c44e68e5267bac1f0f558421c6a0c7a9329c Gerrit-Change-Number: 28734 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

1 0

Change in coreboot[master]: vendorcode/amd/pi/00670F00/Proc/PspBaseLib: Remove folder
by Richard Spiegel (Code Review) 25 Sep '18

25 Sep '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28733 Change subject: vendorcode/amd/pi/00670F00/Proc/PspBaseLib: Remove folder ...................................................................... vendorcode/amd/pi/00670F00/Proc/PspBaseLib: Remove folder Now that PspBaseLib is no longer used, fully remove the folder. BUG=b:116579642 TEST=Build grunt Change-Id: I441b3f46e2312c12771766f87b25d1dc15ff3af0 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc D src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c D src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h D src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h 4 files changed, 0 insertions(+), 670 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28733/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index ad3955c..61d0480 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -43,8 +43,6 @@ BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU/Family BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch/Common -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib - AGESA_INC = -I$(obj) AGESA_INC += $(BINARY_PI_INC) @@ -90,8 +88,6 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS]) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) - classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c deleted file mode 100644 index 392dda6..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c +++ /dev/null @@ -1,315 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PSP Base Library - * - * Contains interface to the PSP library - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: PSP - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Filecode.h" - /* - * Header removed for coreboot. - * #include "Fch.h" - */ -#include "PspBaseLib.h" - -#define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE -#define PSP_BAR_TMP_BASE 0xFEA00000ul - -#define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF) -#define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F) -#define GET_PCI_FUNC(Reg) (((UINT32) Reg >> 8) & 0x7) -#define GET_PCI_OFFSET(Reg) ((UINT32)Reg & 0xFF) - -#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xB8 ///< Gnb Offset index for SMU mbox -#define PCI_CONFIG_SMU_INDIRECT_DATA 0xBC ///< Gnb Offset data for SMU mbox - -#define SMU_CC_PSP_FUSES_STATUS 0xC0018000ul ///< offset in GNB to find PSP fusing -#define SMU_CC_PSP_FUSES_SECURE BIT0 ///< BIT0 -#define SMU_CC_PSP_FUSES_FRA_ENABLE BIT1 ///< BIT1 -#define SMU_CC_PSP_FUSES_PROTO BIT2 ///< BIT2 -#define PLATFORM_SECURE_BOOT_EN BIT4 ///< BIT4 - - -#define PSP_BLANK_PART 0 ///< Blank part -#define PSP_PROTO_PART SMU_CC_PSP_FUSES_PROTO ///< Proto Part -#define PSP_NON_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_PCPU_DIS) ///< Non Secure Part -#define PSP_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< Secure Part -#define PSP_FRA_MODE (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< FRA Part - -#define PSP_MUTEX_REG0_OFFSET (24 * 4) ///< PSP Mutex0 register offset -#define PSP_MUTEX_REG1_OFFSET (25 * 4) ///< PSP Mutex1 register offset - -#ifndef OFFSET_OF -#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field)) -#endif - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -UINT32 -PspLibPciReadConfig ( - IN UINT32 Register - ) -{ - UINT32 Value; - PCI_ADDR PciAddr; - - Value = 0; - PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register)); - - LibAmdPciRead (AccessWidth32, PciAddr, &Value, NULL); - - return Value; -} - -VOID -PspLibPciWriteConfig ( - IN UINT32 Register, - IN UINT32 Value - ) -{ - PCI_ADDR PciAddr; - PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register)); - - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, NULL); - -} - -UINT32 -PspLibPciReadPspConfig ( - IN UINT16 Offset - ) -{ - return (PspLibPciReadConfig ((UINT32) (PSP_PCI_BDA + Offset))); -} - -VOID -PspLibPciWritePspConfig ( - IN UINT16 Offset, - IN UINT32 Value - ) -{ - PspLibPciWriteConfig ((UINT32) (PSP_PCI_BDA + Offset), Value); -} - -/// Structure for Program ID -typedef enum { - CZ_PROGRAM = 0x00, ///< Program ID for CZ - BR_PROGRAM = 0x01, ///< Program ID for BR - ST_PROGRAM = 0x02, ///< Program ID for ST - UNSUPPORTED_PROGRAM = 0xFF, ///< Program ID for unsupported -} PROGRAM_ID; - -static PROGRAM_ID -PspGetProgarmId ( - VOID - ) -{ - CPUID_DATA Cpuid; - - LibAmdCpuidRead (0x00000001, &Cpuid, NULL); - //Stoney CPUID 0x00670F00 or 0x00670F01 - if ((Cpuid.EAX_Reg >> 16) == 0x67) { - return ST_PROGRAM; - } else if ((Cpuid.EAX_Reg >> 16) == 0x66) { - if ((Cpuid.EAX_Reg & 0xF0) == 0x50) { - //Bristol CPUID 0x00660F51 - return BR_PROGRAM; - } else if ((Cpuid.EAX_Reg & 0xF0) == 0x00) { - //Carrizo CPUID 0x00660F00 or 0x00660F01 - return CZ_PROGRAM; - } - } - return UNSUPPORTED_PROGRAM; -} - -BOOLEAN -GetPspDirBase ( - IN OUT UINT32 *Address - ) -{ - UINTN i; - FIRMWARE_ENTRY_TABLE *FirmwareTableBase; - PROGRAM_ID ProgramId; - CONST UINT32 RomSigAddrTable[] = - { - 0xFFFA0000, // --> 512KB base - 0xFFF20000, // --> 1MB base - 0xFFE20000, // --> 2MB base - 0xFFC20000, // --> 4MB base - 0xFF820000, // --> 8MB base - 0xFF020000 // --> 16MB base - }; - - ProgramId = PspGetProgarmId (); - - for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) { - FirmwareTableBase = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i]; - // Search flash for unique signature 0x55AA55AA - if (FirmwareTableBase->Signature == FIRMWARE_TABLE_SIGNATURE) { - switch (ProgramId) { - case BR_PROGRAM: - case CZ_PROGRAM: - *Address = FirmwareTableBase->PspDirBase; - break; - case ST_PROGRAM: - *Address = FirmwareTableBase->NewPspDirBase; - break; - default: - *Address = FirmwareTableBase->PspDirBase; - break; - } - return TRUE; - } - } - return (FALSE); -} - -/** - Check if PSP device is present - - @retval BOOLEAN 0: PSP Disabled, 1: PSP Enabled - -**/ -BOOLEAN -CheckPspDevicePresent ( - VOID - ) -{ - UINT32 SecureFuseReg; - PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS); - SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA); - - if (SecureFuseReg &= SMU_CC_PSP_FUSES_PROTO) { - return (TRUE); - } - return (FALSE); -} - -BOOLEAN -PspBarInitEarly () -{ - UINT32 PspMmioSize; - UINT32 Value32; - - if (PspLibPciReadPspConfig (PSP_PCI_DEVID_REG) == 0xffffffff) { - return (FALSE); - } - - //Check if PSP BAR has been assigned, if not do the PSP BAR initialation - if (PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) == 0) { - /// Get PSP BAR1 Size - PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, 0xFFFFFFFF); - PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG); - PspMmioSize = ~PspMmioSize + 1; - /// Assign BAR3 Temporary Address - PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, PSP_BAR_TMP_BASE); - PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06); - - /// Enable GNB redirection to this space @todo use equate & also find proper fix - PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF); - PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR_TMP_BASE >> 8) | 3); - /// Enable MsixBarEn, Bar1En, Bar3En - PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34); - /// Capability chain update - Value32 = PspLibPciReadPspConfig (PSP_PCI_MIRRORCTRL1_REG); - Value32 &= ~D8F0x44_PmNxtPtrW_MASK; - Value32 |= 0xA4; - PspLibPciWritePspConfig (PSP_PCI_MIRRORCTRL1_REG, Value32); - } - - return (TRUE); -} - -/** - Return the PspMMIO MMIO location - - @param[in] PspMmio Pointer to Psp MMIO address - - @retval BOOLEAN 0: Error, 1 Success -**/ -BOOLEAN -GetPspBar3Addr ( - IN OUT UINT32 *PspMmio - ) -{ - UINT32 PciReg48; - UINT64 MsrPspAddr; - - if (CheckPspDevicePresent () == FALSE) { - return (FALSE); - } - - PciReg48 = PspLibPciReadPspConfig (PSP_PCI_EXTRAPCIHDR_REG); - if (PciReg48 & BIT12) { - // D8F0x48[12] Bar3Hide - LibAmdMsrRead (PSP_MSR_PRIVATE_BLOCK_BAR, &MsrPspAddr, NULL); - *PspMmio = (UINT32)MsrPspAddr; - } else { - *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) & 0xFFF00000; - } - - if ((*PspMmio) == 0xffffffff) { - return (FALSE); - } - - return (TRUE); -} diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h deleted file mode 100644 index 4a37f80..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PSP Base Library - * - * Contains interface to the PSP library - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: PSP - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include <check_for_wrapper.h> - -#ifndef _PSP_BASE_LIB_H_ -#define _PSP_BASE_LIB_H_ - -#include "AMD.h" -#include "amdlib.h" -#include "PspDirectory.h" - -#define PSP_PCI_SEG 0x00 ///< PSP Seg address -#define PSP_PCI_BUS 0x00 ///< PSP Bus address -#define PSP_PCI_DEV 0x08 ///< PSP Device address -#define PSP_PCI_FN 0x00 ///< PSP Fn address -#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8)) -#define GET_PSP_PCI_ADDR(Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset) - -#define PSP_PCI_DEVID_REG 0x00 ///< DevId -#define PSP_PCI_CMD_REG 0x04 ///< CmdReg -#define PSP_PCI_BAR1_REG 0x18 ///< Pci Bar1 -#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3 -#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl 1 -#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr -#define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability - -#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2ul ///< PSP Private Block Base Address (PSP_ADDR) - -#define D8F0x44_PmNxtPtrW_MASK 0xff - -#define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR -#define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset - -#define PMIO_INDEX_PORT 0xCD6 ///Pmio index port -#define PMIO_DATA_PORT 0xCD7 ///Pmio data port - -#define PMIO_REG62 0x62 ///PMIOx62 - -//====================================================================================== -// -// Define Mailbox Status field -// -//====================================================================================== -// -/// MBox Status MMIO space -/// -typedef struct { - UINT32 MboxInitialized:1; ///< Target will set this to 1 to indicate it is initialized (for ex. PSP/TPM ready) - UINT32 Error:1; ///< Target in adddtion to Done bit will also set this bit to indicate success/error on last command - UINT32 Terminated:1; ///< Target will set this bit if it aborted the command due to abort request - UINT32 Halt:1; ///< Target will set this error if there is critical error that require reset etc - UINT32 Recovery:1; ///< Target will set this error if some PSP entry point by PSP directory has been corrupted. - UINT32 Reserved:27; ///< Reserved -} MBOX_STATUS; - -// -// Above defined as bitmap -#define MBOX_STATUS_INITIALIZED 0x00000001ul ///< Mailbox Status: Initialized -#define MBOX_STATUS_ERROR 0x00000002ul ///< Mailbox Status: Error -#define MBOX_STATUS_ABORT 0x00000004ul ///< Mailbox Status: Abort -#define MBOX_STATUS_HALT 0x00000008ul ///< Mailbox Status: Halt -#define MBOX_STATUS_RECOVERY 0x00000010ul ///< Mailbox Status: Recovery required - - - -#define PSP_SMM_COMMUNICATION_TYPE_S3SCRIPT 0x1 ///< PspCommunicationType for S3 script - -/// PSP communication structure for S3SCRIPT -typedef struct { - UINT64 PspBar3PciAddr; /// PCI address for PSP BAR3 - UINT32 PspBar3Val; /// PCI register value for PSP BAR3 - UINT64 Pspx48PciAddr; /// PCI address for PSP Register 48 - UINT32 Pspx48Val; /// PCI register value for PSP Register 48 -} PSP_SMM_COMMUNICATION_S3SCRIPT; - -/// Union for PSP_SMM_COMMUNICATE_DATA -typedef union _PSP_SMM_COMMUNICATE_DATA { - PSP_SMM_COMMUNICATION_S3SCRIPT S3Script; ///< S3Script -} PSP_SMM_COMMUNICATE_DATA; - -/// PSP communication header -typedef struct { - UINT32 PspCommunicationType; ///< Type of smm communication buffer - PSP_SMM_COMMUNICATE_DATA Data; ///< Communication buffer -} PSP_SMM_COMMUNICATION_BUFFER; - - -UINT32 -PspLibPciReadConfig ( - IN UINT32 Register - ); - -VOID -PspLibPciWriteConfig ( - IN UINT32 Register, - IN UINT32 Value - ); - -UINT32 -PspLibPciReadPspConfig ( - IN UINT16 Offset - ); - -VOID -PspLibPciWritePspConfig ( - IN UINT16 Offset, - IN UINT32 Value - ); - -BOOLEAN -GetPspDirBase ( - IN OUT UINT32 *Address -); - -BOOLEAN -PSPEntryInfo ( - IN PSP_DIRECTORY_ENTRY_TYPE EntryType, - IN OUT UINT64 *EntryAddress, - IN OUT UINT32 *EntrySize - ); - -BOOLEAN -PspSoftWareFuseInfo ( - IN OUT UINTN *FuseSpiAddress, - IN OUT UINT64 *FuseValue - ); - -VOID -UpdataPspDirCheckSum ( - IN OUT PSP_DIRECTORY *PspDir - ); - -BOOLEAN -CheckPspDevicePresent ( - VOID - ); - -BOOLEAN -CheckPspPlatformSecureEnable ( - VOID - ); - -BOOLEAN -CheckPspRecoveryFlag ( - VOID - ); - -BOOLEAN -GetPspBar1Addr ( - IN OUT UINT32 *PspMmio - ); - -BOOLEAN -GetPspBar3Addr ( - IN OUT UINT32 *PspMmio - ); - -VOID -AcquirePspSmiRegMutex ( - VOID - ); - -VOID -ReleasePspSmiRegMutex ( - VOID - ); - -BOOLEAN -GetPspMboxStatus ( - IN OUT MBOX_STATUS **MboxStatus - ); - - -BOOLEAN -PspBarInitEarly (VOID); - -VOID -PspLibPciIndirectRead ( - IN PCI_ADDR Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - OUT VOID *Value - ); - -VOID -PspLibPciIndirectWrite ( - IN PCI_ADDR Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN VOID *Value - ); - -BOOLEAN -IsS3Resume (VOID); - - -#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h deleted file mode 100644 index f35901e..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PSP directory related functions Prototype definition - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: PSP - * @e \$Revision$ @e \$Date$ - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include <check_for_wrapper.h> - -#ifndef _PSP_DIRECTORY_H_ -#define _PSP_DIRECTORY_H_ - - -#define FIRMWARE_TABLE_SIGNATURE 0x55AA55AAul -/// Define the structure OEM signature table -typedef struct _FIRMWARE_ENTRY_TABLE { - UINT32 Signature; ///< Signature should be 0x55AA55AAul - UINT32 ImcRomBase; ///< Base Address for Imc Firmware - UINT32 GecRomBase; ///< Base Address for Gmc Firmware - UINT32 XHCRomBase; ///< Base Address for XHCI Firmware - UINT32 PspDirBase; ///< Base Address for PSP directory - UINT32 NewPspDirBase; ///< Base Address of PSP directory from program start from ST -} FIRMWARE_ENTRY_TABLE; - -/// Define structure for PSP directory -typedef struct { - UINT32 PspCookie; ///< "$PSP" - UINT32 Checksum; ///< 32 bit CRC of header items below and the entire table - UINT32 TotalEntries; ///< Number of PSP Entries - UINT32 Reserved; ///< Unused -} PSP_DIRECTORY_HEADER; - - -/// define various enum type for PSP entry type -enum _PSP_DIRECTORY_ENTRY_TYPE { - AMD_PUBLIC_KEY = 0x00, ///< PSP entry pointer to AMD public key - PSP_FW_BOOT_LOADER = 0x01, ///< PSP entry points to PSP boot loader in SPI space - PSP_FW_TRUSTED_OS = 0x02, ///< PSP entry points to PSP Firmware region in SPI space - PSP_FW_RECOVERY_BOOT_LOADER = 0x03, ///< PSP entry point to PSP recovery region. - PSP_NV_DATA = 0x04, ///< PSP entry points to PSP data region in SPI space - BIOS_PUBLIC_KEY = 0x05, ///< PSP entry points to BIOS public key stored in SPI space - BIOS_RTM_FIRMWARE = 0x06, ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space - BIOS_RTM_SIGNATURE = 0x07, ///< PSP entry points to signed BIOS RTM hash stored in SPI space - SMU_OFFCHIP_FW = 0x08, ///< PSP entry points to SMU image - AMD_SEC_DBG_PUBLIC_KEY = 0x09, ///< PSP entry pointer to Secure Unlock Public key - OEM_PSP_FW_PUBLIC_KEY = 0x0A, ///< PSP entry pointer to an optional public part of the OEM PSP Firmware Signing Key Token - AMD_SOFT_FUSE_CHAIN_01 = 0x0B, ///< PSP entry pointer to 64bit PSP Soft Fuse Chain - PSP_BOOT_TIME_TRUSTLETS = 0x0C, ///< PSP entry points to boot-loaded trustlet binaries - PSP_BOOT_TIME_TRUSTLETS_KEY = 0x0D, ///< PSP entry points to key of the boot-loaded trustlet binaries - PSP_AGESA_RESUME_FW = 0x10, ///< PSP Entry points to PSP Agesa-Resume-Firmware - SMU_OFF_CHIP_FW_2 = 0x12, ///< PSP entry points to secondary SMU image - PSP_S3_NV_DATA = 0x1A, ///< PSP entry pointer to S3 Data Blob - AMD_SCS_BINARY = 0x5F, ///< Software Configuration Settings Data Block -}; - -#define PSP_ENTRY_PROGRAM_ID_0 0 ///< Program identifier 0, used when two programs share the same root key -#define PSP_ENTRY_PROGRAM_ID_1 1 ///< Program identifier 1, used when two programs share the same root key - -#define PSP_ENTRY_CZ_PROGRAM_ID PSP_ENTRY_PROGRAM_ID_0 ///< CZ Program identifier -#define PSP_ENTRY_BR_PROGRAM_ID PSP_ENTRY_PROGRAM_ID_1 ///< BR Program identifier - -typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE; - -/// Structure for PSP Entry -typedef struct { - PSP_DIRECTORY_ENTRY_TYPE Type; ///< Type of PSP entry; 32 bit long - UINT32 Size; ///< Size of PSP Entry in bytes - UINT64 Location; ///< Location of PSP Entry (byte offset from start of SPI-ROM) -} PSP_DIRECTORY_ENTRY; - -/// Structure for PSP directory -typedef struct { - PSP_DIRECTORY_HEADER Header; ///< PSP directory header - PSP_DIRECTORY_ENTRY PspEntry[1]; ///< Array of PSP entries each pointing to a binary in SPI flash - ///< The actual size of this array comes from the - ///< header (PSP_DIRECTORY.Header.TotalEntries) -} PSP_DIRECTORY; - -#endif //_PSP_DIRECTORY_H_ -- To view, visit https://review.coreboot.org/28733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I441b3f46e2312c12771766f87b25d1dc15ff3af0 Gerrit-Change-Number: 28733 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: src/cpu/via/nano: Remove unneeded include
by Martin Roth (Code Review) 25 Sep '18

25 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28704 ) Change subject: src/cpu/via/nano: Remove unneeded include ...................................................................... src/cpu/via/nano: Remove unneeded include Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28704 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/cpu/via/nano/update_ucode.h 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index 09f4d76..ef70d23 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -16,7 +16,6 @@ #ifndef __UPDATE_UCODE_H #define __UPDATE_UCODE_H -#include <console/console.h> #include <cpu/cpu.h> #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 -- To view, visit https://review.coreboot.org/28704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2 Gerrit-Change-Number: 28704 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: northbridge: Use 'unsigned int' to bare use of 'unsigned'
by Martin Roth (Code Review) 25 Sep '18

25 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28702 ) Change subject: northbridge: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... northbridge: Use 'unsigned int' to bare use of 'unsigned' Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28702 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/lx/raminit.h M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.h M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_sandybridge/gma.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c 17 files changed, 30 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index ef54de5..2843b92 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -32,7 +32,7 @@ struct mem_controller; extern void activate_spd_rom(const struct mem_controller *ctrl); -extern int spd_read_byte(unsigned device, unsigned address); +extern int spd_read_byte(unsigned int device, unsigned int address); void fam15h_switch_dct(uint32_t dev, uint8_t dct) { diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h index 3a5d571..d106862 100644 --- a/src/northbridge/amd/lx/raminit.h +++ b/src/northbridge/amd/lx/raminit.h @@ -30,6 +30,6 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl); /* mainboard specific */ -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); #endif diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 6d351a3..a5dc6cd 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -75,8 +75,8 @@ assign_resources(dev->link_list); } -static void intel_set_subsystem(struct device *dev, - unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index eae8935..1581b82 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -35,6 +35,6 @@ /* Mainboard exports this. */ -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 27153f8..72b2761 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -173,7 +173,8 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index 2cfd1f3..cba5869 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -66,8 +66,8 @@ gnvs_ptr->aslb = aslb; } -static void gma_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index b192161..111c201 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -248,8 +248,8 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 5335fbb..b86e2b3 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -788,7 +788,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 8f60da4..efc9fa3 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -494,8 +494,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index d8b4b66..52710bb 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -103,8 +103,8 @@ } } -static void minihd_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void minihd_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index f61a478..0453246 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -408,8 +408,8 @@ mc_add_dram_resources(dev, &index); } -static void intel_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 6e2d404..b89215d 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -623,7 +623,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 8f55e3c..4c6cdd4 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -191,7 +191,8 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 02100e9..eb67c65 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -304,7 +304,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index a050e06..5adf865 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -102,7 +102,7 @@ __asm__ __volatile__("": : :"memory"); } -static inline int spd_read_byte(unsigned device, unsigned address) +static inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 042c2a9..cd8f7b9 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -669,7 +669,8 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7863810..cb0e5db 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -287,7 +287,8 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, -- To view, visit https://review.coreboot.org/28702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Gerrit-Change-Number: 28702 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb: Use 'unsigned int' to bare use of 'unsigned'
by Martin Roth (Code Review) 25 Sep '18

25 Sep '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28701 ) Change subject: mb: Use 'unsigned int' to bare use of 'unsigned' ...................................................................... mb: Use 'unsigned int' to bare use of 'unsigned' Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28701 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c 24 files changed, 32 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index e59773f..e73a0e7 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -54,7 +54,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d4397b2..5ee1fd6 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -49,7 +49,7 @@ #include "cpu/amd/quadcore/quadcore.c" void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e5766c8..0e2db04 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -55,7 +55,7 @@ #include "cpu/amd/quadcore/quadcore.c" void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index ed5a6cb..ad3157f 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -51,7 +51,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; static void memreset_setup(void) diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 89d170c..89e72eb 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -53,7 +53,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index f203dd1..d18c2ad 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -32,7 +32,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) -int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 3410762..1d616a6 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -54,10 +54,10 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index cc198c6..036f136 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -59,10 +59,10 @@ #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 95fe630..98bb1ca 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -54,10 +54,10 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address); } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 6392f8f..4e05f0f 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -55,7 +55,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index dd61c8f..b4f6293 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -56,7 +56,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index e3f3f3c..fb1a134 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -55,7 +55,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index e2ce482..d91776c 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -54,7 +54,7 @@ #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 98bc00f..680d279 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -52,7 +52,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 81d4c6b..642f70b 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -52,7 +52,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 9f4dd44..923cfbc 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -55,7 +55,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 116a53a..fc922f4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -57,7 +57,7 @@ #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -71,7 +71,7 @@ outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 866a9a8..5693cee 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -54,7 +54,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 760fc13..1041696 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -59,7 +59,7 @@ #endif void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 0b5d935..7848e9e 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -49,12 +49,12 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c360389..d5506df 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -53,12 +53,12 @@ #define SUPERIO_DEV PNP_DEV(0x2e, 0) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index ddbb97c..f438400 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -55,7 +55,7 @@ #define SMBUS_SWITCH2 0x72 void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -64,7 +64,7 @@ smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 6850995..a3d3cea 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -51,7 +51,7 @@ #include "cpu/amd/quadcore/quadcore.c" void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 373ff71..0b47f9d 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -49,12 +49,12 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) void activate_spd_rom(const struct mem_controller *ctrl); -int spd_read_byte(unsigned device, unsigned address); +int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { } -inline int spd_read_byte(unsigned device, unsigned address) +inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -- To view, visit https://review.coreboot.org/28701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Gerrit-Change-Number: 28701 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads/Kconfig: do not show compression menu for FIT
by Patrick Rudolph (Code Review) 25 Sep '18

25 Sep '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28732 ) Change subject: payloads/Kconfig: do not show compression menu for FIT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef Gerrit-Change-Number: 28732 Gerrit-PatchSet: 1 Gerrit-Owner: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 13:49:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: payloads/Kconfig: do not show compression menu for FIT
by Andrea Barberio (Code Review) 25 Sep '18

25 Sep '18

Andrea Barberio has uploaded this change for review. ( https://review.coreboot.org/28732 Change subject: payloads/Kconfig: do not show compression menu for FIT ...................................................................... payloads/Kconfig: do not show compression menu for FIT FIT payloads do not support compression. Currently this would thrown an error like the following: E: FIT images don't support whole-image compression, compress the kernel component instead! With this patch, menuconfig will correctly *not* show payload compression for FIT payloads, and this will correctly set compression to NONE. Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef Signed-off-by: Andrea Barberio <insomniac(a)slackware.it> --- M payloads/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28732/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index 5e76ebe..8e05df3 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -64,7 +64,7 @@ choice prompt "Payload compression algorithm" default COMPRESSED_PAYLOAD_LZMA - depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT + depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT help Choose the compression algorithm for the chosen payloads. You can choose between LZMA and LZ4. -- To view, visit https://review.coreboot.org/28732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef Gerrit-Change-Number: 28732 Gerrit-PatchSet: 1 Gerrit-Owner: Andrea Barberio <insomniac(a)slackware.it>

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coreboot-gerrit September 2018