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coreboot-gerrit
September 2018
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coreboot-gerrit@coreboot.org
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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review)
25 Sep '18
25 Sep '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25105
) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 21: (7 comments)
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c
File src/drivers/spi/winbond.c:
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c@33
PS21, Line 33: #define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c@502
PS21, Line 502: val = (union status_reg1_bp3){ .bp = bp, .tb = tb, .sec = 0 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c@503
PS21, Line 503: mask = (union status_reg1_bp3){ .bp = ~0, .tb = 1, .sec = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c@505
PS21, Line 505: val = (union status_reg1_bp4){ .bp = bp, .tb = tb }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c@506
PS21, Line 506: mask = (union status_reg1_bp4){ .bp = ~0, .tb = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c@513
PS21, Line 513: val = (union status_reg2){ .cmp = cmp }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/21/src/drivers/spi/winbond.c@514
PS21, Line 514: mask = (union status_reg2){ .cmp = 1 }.u; space required after that close brace '}' -- To view, visit
https://review.coreboot.org/25105
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 21 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 13:25:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No
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Change in coreboot[master]: drivers/spi/winbond: Add function to lock flash's status register
by build bot (Jenkins) (Code Review)
25 Sep '18
25 Sep '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/28697
) Change subject: drivers/spi/winbond: Add function to lock flash's status register ...................................................................... Patch Set 4: (8 comments)
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c
File src/drivers/spi/winbond.c:
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@540
PS4, Line 540: const enum spi_flash_status_reg_lockdown mode, code indent should use tabs where possible
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@541
PS4, Line 541: const bool non_volatile) code indent should use tabs where possible
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@555
PS4, Line 555: val = (union status_reg1_bp3){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@556
PS4, Line 556: mask = (union status_reg1_bp3){ .srp0 = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@558
PS4, Line 558: val = (union status_reg1_bp4){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@559
PS4, Line 559: mask = (union status_reg1_bp4){ .srp0 = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@566
PS4, Line 566: val = (union status_reg2){ .srp1 = !!(mode & 2) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/4/src/drivers/spi/winbond.c@567
PS4, Line 567: mask = (union status_reg2){ .srp1 = 1 }.u; space required after that close brace '}' -- To view, visit
https://review.coreboot.org/28697
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90e0fcdcf531b53c0fc1ffcfdb3b5ab522f088f5 Gerrit-Change-Number: 28697 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 13:25:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No
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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review)
25 Sep '18
25 Sep '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25105
) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 20: (7 comments)
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c
File src/drivers/spi/winbond.c:
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c@33
PS20, Line 33: #define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c@506
PS20, Line 506: val = (union status_reg1_bp3){ .bp = bp, .tb = tb, .sec = 0 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c@507
PS20, Line 507: mask = (union status_reg1_bp3){ .bp = ~0, .tb = 1, .sec = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c@509
PS20, Line 509: val = (union status_reg1_bp4){ .bp = bp, .tb = tb }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c@510
PS20, Line 510: mask = (union status_reg1_bp4){ .bp = ~0, .tb = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c@517
PS20, Line 517: val = (union status_reg2){ .cmp = cmp }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/20/src/drivers/spi/winbond.c@518
PS20, Line 518: mask = (union status_reg2){ .cmp = 1 }.u; space required after that close brace '}' -- To view, visit
https://review.coreboot.org/25105
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 20 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 13:08:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No
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Change in coreboot[master]: drivers/spi/winbond: Add function to lock flash's status register
by build bot (Jenkins) (Code Review)
25 Sep '18
25 Sep '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/28697
) Change subject: drivers/spi/winbond: Add function to lock flash's status register ...................................................................... Patch Set 3: (8 comments)
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c
File src/drivers/spi/winbond.c:
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@544
PS3, Line 544: const enum spi_flash_status_reg_lockdown mode, code indent should use tabs where possible
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@545
PS3, Line 545: const bool non_volatile) code indent should use tabs where possible
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@559
PS3, Line 559: val = (union status_reg1_bp3){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@560
PS3, Line 560: mask = (union status_reg1_bp3){ .srp0 = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@562
PS3, Line 562: val = (union status_reg1_bp4){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@563
PS3, Line 563: mask = (union status_reg1_bp4){ .srp0 = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@570
PS3, Line 570: val = (union status_reg2){ .srp1 = !!(mode & 2) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/3/src/drivers/spi/winbond.c@571
PS3, Line 571: mask = (union status_reg2){ .srp1 = 1 }.u; space required after that close brace '}' -- To view, visit
https://review.coreboot.org/28697
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90e0fcdcf531b53c0fc1ffcfdb3b5ab522f088f5 Gerrit-Change-Number: 28697 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 13:08:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No
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Change in coreboot[master]: drivers/spi/winbond: Add function to lock flash's status register
by build bot (Jenkins) (Code Review)
25 Sep '18
25 Sep '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/28697
) Change subject: drivers/spi/winbond: Add function to lock flash's status register ...................................................................... Patch Set 2: (8 comments)
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c
File src/drivers/spi/winbond.c:
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@544
PS2, Line 544: const enum spi_flash_status_reg_lockdown mode, code indent should use tabs where possible
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@545
PS2, Line 545: const bool non_volatile) code indent should use tabs where possible
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@559
PS2, Line 559: val = (union status_reg1_bp3){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@560
PS2, Line 560: mask = (union status_reg1_bp3){ .srp0 = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@562
PS2, Line 562: val = (union status_reg1_bp4){ .srp0 = !!(mode & 1) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@563
PS2, Line 563: mask = (union status_reg1_bp4){ .srp0 = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@570
PS2, Line 570: val = (union status_reg2){ .srp1 = !!(mode & 2) }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/28697/2/src/drivers/spi/winbond.c@571
PS2, Line 571: mask = (union status_reg2){ .srp1 = 1 }.u; space required after that close brace '}' -- To view, visit
https://review.coreboot.org/28697
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90e0fcdcf531b53c0fc1ffcfdb3b5ab522f088f5 Gerrit-Change-Number: 28697 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 13:03:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No
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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review)
25 Sep '18
25 Sep '18
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/25105
) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 19: (7 comments)
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c
File src/drivers/spi/winbond.c:
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c@33
PS19, Line 33: #define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c@506
PS19, Line 506: val = (union status_reg1_bp3){ .bp = bp, .tb = tb, .sec = 0 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c@507
PS19, Line 507: mask = (union status_reg1_bp3){ .bp = ~0, .tb = 1, .sec = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c@509
PS19, Line 509: val = (union status_reg1_bp4){ .bp = bp, .tb = tb }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c@510
PS19, Line 510: mask = (union status_reg1_bp4){ .bp = ~0, .tb = 1 }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c@517
PS19, Line 517: val = (union status_reg2){ .cmp = cmp }.u; space required after that close brace '}'
https://review.coreboot.org/#/c/25105/19/src/drivers/spi/winbond.c@518
PS19, Line 518: mask = (union status_reg2){ .cmp = 1 }.u; space required after that close brace '}' -- To view, visit
https://review.coreboot.org/25105
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 19 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 13:03:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No
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Change in coreboot[master]: drivers/spi/winbond: Fix read protection bits
by Patrick Rudolph (Code Review)
25 Sep '18
25 Sep '18
Patrick Rudolph has uploaded this change for review. (
https://review.coreboot.org/28731
Change subject: drivers/spi/winbond: Fix read protection bits ...................................................................... drivers/spi/winbond: Fix read protection bits Don't care about SRPx and print correct protected range. Change-Id: I051f1459c585a7ed6a4878dc217d11df5ef00d74 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/spi/winbond.c 1 file changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28731/1 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index a0e3884..ac7c2be 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -297,8 +297,6 @@ ret = spi_flash_cmd(&flash->spi, flash->status_cmd, ®1_bp3.u, sizeof(reg1_bp3.u)); - if (ret) - return ret; if (reg1_bp3.sec) { // FIXME: not supported @@ -312,8 +310,6 @@ ret = spi_flash_cmd(&flash->spi, flash->status_cmd, ®1_bp4.u, sizeof(reg1_bp4.u)); - if (ret) - return ret; bp = reg1_bp4.bp; tb = reg1_bp4.tb; @@ -321,6 +317,8 @@ // FIXME: not supported return -1; } + if (ret) + return ret; ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR2, ®2.u, sizeof(reg2.u)); @@ -330,14 +328,15 @@ winbond_bpbits_to_region(granularity, bp, tb, reg2.cmp, flash->size, &wp_region); - if (!reg2.srp1 || !wp_region.size) { + if (!region_sz(&wp_region)) { printk(BIOS_DEBUG, "WINBOND: flash isn't protected\n"); return 0; } printk(BIOS_DEBUG, "WINBOND: flash protected range 0x%08zx-0x%08zx\n", - wp_region.offset, wp_region.size); + region_offset(&wp_region), + region_offset(&wp_region) + region_sz(&wp_region)); return region_is_subregion(&wp_region, region); } -- To view, visit
https://review.coreboot.org/28731
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I051f1459c585a7ed6a4878dc217d11df5ef00d74 Gerrit-Change-Number: 28731 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
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Change in coreboot[master]: siemens/mc_apl1: Make the DDR memory swizzle data configurable
by Mario Scheithauer (Code Review)
25 Sep '18
25 Sep '18
Mario Scheithauer has uploaded this change for review. (
https://review.coreboot.org/28730
Change subject: siemens/mc_apl1: Make the DDR memory swizzle data configurable ...................................................................... siemens/mc_apl1: Make the DDR memory swizzle data configurable In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/romstage.c M src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc M src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h A src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c 4 files changed, 143 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28730/1 diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index d56c7ee..f2786cf 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -18,39 +18,18 @@ #include <hwilib.h> #include <lib.h> #include <string.h> +#include <soc/meminit.h> #include <soc/romstage.h> #include <fsp/api.h> #include <FspmUpd.h> #include <baseboard/variants.h> -static const uint8_t Ch0_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch1_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch2_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -static const uint8_t Ch3_Bit_swizzling[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; + const struct lpddr4_swizzle_cfg *cfg; + const struct lpddr4_chan_swizzle_cfg *chan; + const size_t sz = DQ_BITS_PER_DQS; uint8_t spd[0x80]; size_t num; @@ -58,7 +37,8 @@ pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); - /* Get DRAM configuration data from hwinfo block. + /* + * Get DRAM configuration data from hwinfo block. * The configuration data from hwinfo block is a one-to-one * representation of the FSPM_UPD data starting with parameter * 'Package' (offset 0x4d) and ending before parameter @@ -80,14 +60,70 @@ (((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)- (&memupd->FspmConfig.Package))); - memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, - sizeof(Ch0_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, - sizeof(Ch1_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, - sizeof(Ch2_Bit_swizzling)); - memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, - sizeof(Ch3_Bit_swizzling)); + /* + * Some of the mc_apl1 boards use LPDDR4 memory. In this case, the + * correct swizzle configuration is necessary. The default settings + * for swizzling are 0, since the baseboard does not use LPDDR4 memory. + */ + cfg = variant_lpddr4_swizzle_config(); + + /* + * CH0_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + chan = &cfg->phys[LP4_PHYS_CH0B]; + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], + sz); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[8], &chan->dqs[LP4_DQS0], + sz); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[16], &chan->dqs[LP4_DQS3], + sz); + memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[24], &chan->dqs[LP4_DQS2], + sz); + + /* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. */ + chan = &cfg->phys[LP4_PHYS_CH0A]; + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[0], &chan->dqs[LP4_DQS0], + sz); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[8], &chan->dqs[LP4_DQS1], + sz); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[16], &chan->dqs[LP4_DQS2], + sz); + memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3], + sz); + + /* + * CH1_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + chan = &cfg->phys[LP4_PHYS_CH1B]; + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], + sz); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[8], &chan->dqs[LP4_DQS0], + sz); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[16], &chan->dqs[LP4_DQS3], + sz); + memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[24], &chan->dqs[LP4_DQS2], + sz); + + /* CH1_DQA byte lanes in the bit swizzle configuration field are 1:1. */ + chan = &cfg->phys[LP4_PHYS_CH1A]; + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[0], &chan->dqs[LP4_DQS0], + sz); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[8], &chan->dqs[LP4_DQS1], + sz); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[16], &chan->dqs[LP4_DQS2], + sz); + memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3], + sz); memupd->FspmConfig.MsgLevelMask = 0x0; memupd->FspmConfig.MrcDataSaving = 0x0; diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc index e3e87ce..07ebf9b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc @@ -1,3 +1,4 @@ romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h index 09153c6..6828ed8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h @@ -26,6 +26,9 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +/* This function provides the swizzle data for the DRAM initialization. */ +const struct lpddr4_swizzle_cfg *variant_lpddr4_swizzle_config(void); + /* The following function performs board specific things. */ void variant_mainboard_final(void); diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c new file mode 100644 index 0000000..13b7ab8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <compiler.h> +#include <soc/meminit.h> + +const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 }, + }, +}; + +const struct lpddr4_swizzle_cfg * __weak variant_lpddr4_swizzle_config(void) +{ + return &baseboard_lpddr4_swizzle; +} -- To view, visit
https://review.coreboot.org/28730
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Gerrit-Change-Number: 28730 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
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Change in coreboot[master]: cpu/intel/model_206ax: detect number of MCE banks
by Patrick Rudolph (Code Review)
25 Sep '18
25 Sep '18
Patrick Rudolph has posted comments on this change. (
https://review.coreboot.org/28443
) Change subject: cpu/intel/model_206ax: detect number of MCE banks ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit
https://review.coreboot.org/28443
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Gerrit-Change-Number: 28443 Gerrit-PatchSet: 2 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 07:10:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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Change in coreboot[master]: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"
by Furquan Shaikh (Code Review)
25 Sep '18
25 Sep '18
Furquan Shaikh has posted comments on this change. (
https://review.coreboot.org/28690
) Change subject: Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold" ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit
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Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Gerrit-Change-Number: 28690 Gerrit-PatchSet: 3 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Enrico Granata <egranata(a)chromium.org> Gerrit-Reviewer: Enrico Granata <egranata(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Sep 2018 05:01:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes
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