coreboot-gerrit September 2018

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Change in coreboot[master]: commonlib/region: [WIP] Add region protect API
by Rizwan Qureshi (Code Review) 24 Sep '18

24 Sep '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28724 Change subject: commonlib/region: [WIP] Add region protect API ...................................................................... commonlib/region: [WIP] Add region protect API Add "protect" operation to the region_device_ops. This can be used for write protecting the region that is represented by the device. Also add an API redev_protect() which will expose the protect operation to the library user. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28724/1 diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 45484dd..901fd35 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -63,6 +63,11 @@ ssize_t rdev_eraseat(const struct region_device *rd, size_t offset, size_t size); +/* + * Returns < 0 on error otherwise returns 0 on success, < 0 0n error. + */ +int rdev_protect(const struct region_device *rd); + /**************************************** * Implementation of a region device * ****************************************/ @@ -75,6 +80,10 @@ int rdev_chain(struct region_device *child, const struct region_device *parent, size_t offset, size_t size); +struct region { + size_t offset; + size_t size; +}; /* A region_device operations. */ struct region_device_ops { @@ -84,12 +93,9 @@ ssize_t (*writeat)(const struct region_device *, const void *, size_t, size_t); ssize_t (*eraseat)(const struct region_device *, size_t, size_t); + int (*protect)(const struct region *); }; -struct region { - size_t offset; - size_t size; -}; struct region_device { const struct region_device *root; diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 541a125..58b5fa4 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -151,6 +151,18 @@ return rdev->ops->eraseat(rdev, req.offset, req.size); } +int rdev_protect(const struct region_device *rd) +{ + const struct region_device *rdev; + + rdev = rdev_root(rd); + + if (rdev->ops->protect == NULL) + return -1; + + return rdev->ops->protect(region_device_region(rdev)); +} + int rdev_chain(struct region_device *child, const struct region_device *parent, size_t offset, size_t size) { -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Stop charging with highest priority
by Sumeet R Pawnikar (Code Review) 24 Sep '18

24 Sep '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28723 Change subject: mb/google/poppy/variants/nocturne: Stop charging with highest priority ...................................................................... mb/google/poppy/variants/nocturne: Stop charging with highest priority First stop battery charging at high temperature of TSR2 sensor and later start CPU throttling for TSR2 sensor. This will control the TSR2 sensor temperature going high and prevent to hit critical temperature threshold for TSR2 to avoid shutdown. BUG=b:112550414 BRANCH=None TEST=Build coreboot for Nocturne board. Change-Id: I22bf648ff31f7bdf0ce0d147399d4f566ccdddc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/28723/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index f9773b8..6250cea 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -46,6 +46,7 @@ Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0mA (stop charging) */ }) Name (DTRT, Package () { @@ -56,17 +57,17 @@ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, /* CPU Throttle Effect on DRAM (TSR2) */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 }, /* CPU Throttle Effect on eMMC (TSR3) */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, #ifdef DPTF_ENABLE_CHARGER /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, /* Charger Throttle Effect on DRAM (TSR2) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 50, 0, 0, 0, 0 }, #endif }) -- To view, visit https://review.coreboot.org/28723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I22bf648ff31f7bdf0ce0d147399d4f566ccdddc3 Gerrit-Change-Number: 28723 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Stop charging for TSR2 sensor
by Sumeet R Pawnikar (Code Review) 24 Sep '18

24 Sep '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28722 Change subject: mb/google/poppy/variants/nocturne: Stop charging for TSR2 sensor ...................................................................... mb/google/poppy/variants/nocturne: Stop charging for TSR2 sensor Stop battery charging at high temperature for TSR2 sensor eMMC. BUG=b:112550414 BRANCH=None TEST=Build coreboot for Nocturne board. Change-Id: I960470f09f8a7d44054bb3e85046ce2f632084c9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/28722/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index f9773b8..1aef1f6 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -46,6 +46,7 @@ Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0mA (stop charging) */ }) Name (DTRT, Package () { -- To view, visit https://review.coreboot.org/28722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I960470f09f8a7d44054bb3e85046ce2f632084c9 Gerrit-Change-Number: 28722 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: ec/google/chromeec: set SCI event mask early on s0
by dhaval v sharma (Code Review) 24 Sep '18

24 Sep '18

dhaval v sharma has uploaded this change for review. ( https://review.coreboot.org/28721 Change subject: ec/google/chromeec: set SCI event mask early on s0 ...................................................................... ec/google/chromeec: set SCI event mask early on s0 Change helps in avoiding an ACPI switch SMI later Change-Id: Ib4d2b3e12d1d63dba29c5365c5a2fbf7b221226b Signed-off-by: Dhaval <dhaval.v.sharma(a)intel.com> --- M src/ec/google/chromeec/ec.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/28721/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 90fcc3d..17ee13a 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -474,9 +474,6 @@ while (google_chromeec_get_event() != 0) ; - /* Restore SCI event mask. */ - google_chromeec_set_sci_mask(info->sci_events); - } else { google_chromeec_set_smi_mask(info->smi_events); @@ -489,6 +486,13 @@ info->s3_wake_events, info->s0ix_wake_events); } + /* Should be okay to set sci mask for s0 path also because + * anyways SCI interrupt gets enabled later during PMC init + * stage this way we can avoid additional ACPI switch SMI + * later */ + + google_chromeec_set_sci_mask(info->sci_events); + /* Clear wake event mask. */ google_chromeec_set_wake_mask(0); -- To view, visit https://review.coreboot.org/28721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4d2b3e12d1d63dba29c5365c5a2fbf7b221226b Gerrit-Change-Number: 28721 Gerrit-PatchSet: 1 Gerrit-Owner: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: src/mainboard/pcengines/apu2/Kconfig: Clean up PINMUX settings
by Michał Żygowski (Code Review) 24 Sep '18

24 Sep '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/28720 Change subject: src/mainboard/pcengines/apu2/Kconfig: Clean up PINMUX settings ...................................................................... src/mainboard/pcengines/apu2/Kconfig: Clean up PINMUX settings Vendor recommendations related to PINMUX configuration are UARTs. Given that PINMUX_UART_x can be set for all boards as default. Change-Id: Ifb7dfe23a95ba0e572adc38212333d9fdd234d53 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/Kconfig 1 file changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/28720/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index af14066..3d2ed0c 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -78,9 +78,7 @@ choice prompt "J19 pins 1-10" - default APU2_PINMUX_OFF_C if BOARD_PCENGINES_APU2 || \ - BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 - default APU2_PINMUX_UART_C if BOARD_PCENGINES_APU5 + default APU2_PINMUX_UART_C config APU2_PINMUX_OFF_C bool "disable" @@ -97,9 +95,7 @@ choice prompt "J19 pins 11-20" - default APU2_PINMUX_OFF_D if BOARD_PCENGINES_APU2 || \ - BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 - default APU2_PINMUX_UART_D if BOARD_PCENGINES_APU5 + default APU2_PINMUX_UART_D config APU2_PINMUX_OFF_D bool "disable" -- To view, visit https://review.coreboot.org/28720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifb7dfe23a95ba0e572adc38212333d9fdd234d53 Gerrit-Change-Number: 28720 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support
by Piotr Król (Code Review) 24 Sep '18

24 Sep '18

Piotr Król has posted comments on this change. ( https://review.coreboot.org/28719 ) Change subject: sb/amd/pi/hudson: Add SPI controller support ...................................................................... Patch Set 2: And please add more reciewers. -- To view, visit https://review.coreboot.org/28719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Gerrit-Change-Number: 28719 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 24 Sep 2018 09:51:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support
by Piotr Król (Code Review) 24 Sep '18

24 Sep '18

Piotr Król has posted comments on this change. ( https://review.coreboot.org/28719 ) Change subject: sb/amd/pi/hudson: Add SPI controller support ...................................................................... Patch Set 2: Michał, maybe we should add little bit more extensive description of this patch. Why we need this, what was implemented, where this code came from etc. -- To view, visit https://review.coreboot.org/28719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Gerrit-Change-Number: 28719 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 24 Sep 2018 09:50:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support
by Michał Żygowski (Code Review) 24 Sep '18

24 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28719 to look at the new patch set (#2). Change subject: sb/amd/pi/hudson: Add SPI controller support ...................................................................... sb/amd/pi/hudson: Add SPI controller support Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc A src/southbridge/amd/pi/hudson/spi.c 2 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/28719/2 -- To view, visit https://review.coreboot.org/28719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Gerrit-Change-Number: 28719 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support
by build bot (Jenkins) (Code Review) 24 Sep '18

24 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28719 ) Change subject: sb/amd/pi/hudson: Add SPI controller support ...................................................................... Patch Set 1: (22 comments) https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c File src/southbridge/amd/pi/hudson/spi.c: https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 75: while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && trailing statements should be on next line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 117: for (count = 0; count < bytesout; count++, dout++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 126: for (count = 0; count < bytesout; count++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 130: for (count = 0; count < bytesin; count++, din++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 139: if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 148: if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 162: .xfer_vector = xfer_vectors, code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 162: .xfer_vector = xfer_vectors, please, no spaces at the start of a line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 163: .max_xfer_size = AMD_SB_SPI_TX_LEN, code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 163: .max_xfer_size = AMD_SB_SPI_TX_LEN, please, no spaces at the start of a line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 164: .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 164: .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, please, no spaces at the start of a line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 168: { code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 168: { please, no spaces at the start of a line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 169: .ctrlr = &spi_ctrlr, code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 169: .ctrlr = &spi_ctrlr, please, no spaces at the start of a line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 170: .bus_start = 0, code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 170: .bus_start = 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 171: .bus_end = 0, code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 171: .bus_end = 0, please, no spaces at the start of a line https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 172: }, code indent should use tabs where possible https://review.coreboot.org/#/c/28719/1/src/southbridge/amd/pi/hudson/spi.c… PS1, Line 172: }, please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Gerrit-Change-Number: 28719 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Sep 2018 08:26:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support
by Michał Żygowski (Code Review) 24 Sep '18

24 Sep '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/28719 Change subject: sb/amd/pi/hudson: Add SPI controller support ...................................................................... sb/amd/pi/hudson: Add SPI controller support Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc A src/southbridge/amd/pi/hudson/spi.c 2 files changed, 176 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/28719/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 251cb6c..e06973a 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += sm.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c diff --git a/src/southbridge/amd/pi/hudson/spi.c b/src/southbridge/amd/pi/hudson/spi.c new file mode 100644 index 0000000..76373c4 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/spi.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> +#include <console/console.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> + +#include <Proc/Fch/FchPlatform.h> + +#define SPI_REG_OPCODE 0x0 +#define SPI_REG_CNTRL02 0x2 + #define CNTRL02_FIFO_RESET (1 << 4) + #define CNTRL02_EXEC_OPCODE (1 << 0) +#define SPI_REG_CNTRL03 0x3 + #define CNTRL03_SPIBUSY (1 << 7) +#define SPI_REG_FIFO 0xc +#define SPI_REG_CNTRL11 0xd + #define CNTRL11_FIFOPTR_MASK 0x07 +#define SPI_EXT_REG_INDX 0x1e + #define SPI_EXT_REG_TXCOUNT 0x5 + #define SPI_EXT_REG_RXCOUNT 0x6 +#define SPI_EXT_REG_DATA 0x1f + +#define AMD_SB_SPI_TX_LEN 64 + +static uintptr_t spibar; + +static inline uint8_t spi_read(uint8_t reg) +{ + return read8((void *)(spibar + reg)); +} + +static inline void spi_write(uint8_t reg, uint8_t val) +{ + write8((void *)(spibar + reg), val); +} + +static void reset_internal_fifo_pointer(void) +{ + uint8_t reg8; + + do { + reg8 = spi_read(SPI_REG_CNTRL02); + reg8 |= CNTRL02_FIFO_RESET; + spi_write(SPI_REG_CNTRL02, reg8); + } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); +} + +static void execute_command(void) +{ + uint8_t reg8; + + reg8 = spi_read(SPI_REG_CNTRL02); + reg8 |= CNTRL02_EXEC_OPCODE; + spi_write(SPI_REG_CNTRL02, reg8); + + while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && + (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY)); +} + +void spi_init(void) +{ + device_t dev; + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) +{ + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + size_t count; + + bytesout--; + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_WARNING, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + + spi_write(SPI_EXT_REG_INDX, SPI_EXT_REG_TXCOUNT); + spi_write(SPI_EXT_REG_DATA, bytesout); + spi_write(SPI_EXT_REG_INDX, SPI_EXT_REG_RXCOUNT); + spi_write(SPI_EXT_REG_DATA, bytesin); + + spi_write(SPI_REG_OPCODE, cmd); + + reset_internal_fifo_pointer(); + for (count = 0; count < bytesout; count++, dout++) { + spi_write(SPI_REG_FIFO, *(uint8_t *)dout); + } + + reset_internal_fifo_pointer(); + execute_command(); + + reset_internal_fifo_pointer(); + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = spi_read(SPI_REG_FIFO); + } + + for (count = 0; count < bytesin; count++, din++) { + *(uint8_t *)din = spi_read(SPI_REG_FIFO); + } + + return 0; +} + +int chipset_volatile_group_begin(const struct spi_flash *flash) +{ + if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) + return 0; + + ImcSleep(NULL); + return 0; +} + +int chipset_volatile_group_end(const struct spi_flash *flash) +{ + if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) + return 0; + + ImcWakeup(NULL); + return 0; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); +} + +static const struct spi_ctrlr spi_ctrlr = { + .xfer_vector = xfer_vectors, + .max_xfer_size = AMD_SB_SPI_TX_LEN, + .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/28719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Gerrit-Change-Number: 28719 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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coreboot-gerrit September 2018