coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: commonlib/region: [WIP] Add region protect API
by Arthur Heymans (Code Review) 24 Sep '18

24 Sep '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/28724 ) Change subject: commonlib/region: [WIP] Add region protect API ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28724/1/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/1/src/commonlib/include/commonlib/reg… PS1, Line 67: Returns < 0 on error otherwise returns 0 on success, < 0 0n error. use enum cb_err with CB_SUCCESS and CB_ERR. -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 24 Sep 2018 16:39:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee/variants/liara: Disable NbP-state on Liara
by build bot (Jenkins) (Code Review) 24 Sep '18

24 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28726 ) Change subject: mb/google/kahlee/variants/liara: Disable NbP-state on Liara ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28726/2/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/liara/OemCustomize.c: https://review.coreboot.org/#/c/28726/2/src/mainboard/google/kahlee/variant… PS2, Line 149: VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/28726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Gerrit-Change-Number: 28726 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Sep 2018 16:29:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee/variants/liara: Disable NbP-state on Liara
by Amanda Hwang (Code Review) 24 Sep '18

24 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28726 to look at the new patch set (#2). Change subject: mb/google/kahlee/variants/liara: Disable NbP-state on Liara ...................................................................... mb/google/kahlee/variants/liara: Disable NbP-state on Liara To disable NB-Pstate, the system wouldn't auto restart on EVT board when idling. BUG=b:116082728 Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/liara/Makefile.inc A src/mainboard/google/kahlee/variants/liara/OemCustomize.c 2 files changed, 159 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/28726/2 -- To view, visit https://review.coreboot.org/28726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Gerrit-Change-Number: 28726 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/kahlee/variants/liara: Disable NbP-state on Liara
by build bot (Jenkins) (Code Review) 24 Sep '18

24 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28726 ) Change subject: mb/google/kahlee/variants/liara: Disable NbP-state on Liara ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28726/1/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/liara/OemCustomize.c: https://review.coreboot.org/#/c/28726/1/src/mainboard/google/kahlee/variant… PS1, Line 148: VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/28726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Gerrit-Change-Number: 28726 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Sep 2018 16:24:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee/variants/liara: Disable NbP-state on Liara
by Amanda Hwang (Code Review) 24 Sep '18

24 Sep '18

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/28726 Change subject: mb/google/kahlee/variants/liara: Disable NbP-state on Liara ...................................................................... mb/google/kahlee/variants/liara: Disable NbP-state on Liara To disable NB-Pstate, the system wouldn't auto restart on EVT board when idling. BUG=b:116082728 Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/liara/Makefile.inc A src/mainboard/google/kahlee/variants/liara/OemCustomize.c 2 files changed, 158 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/28726/1 diff --git a/src/mainboard/google/kahlee/variants/liara/Makefile.inc b/src/mainboard/google/kahlee/variants/liara/Makefile.inc index 0579e18..b343c31 100644 --- a/src/mainboard/google/kahlee/variants/liara/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/liara/Makefile.inc @@ -15,6 +15,9 @@ subdirs-y += ../baseboard/spd +bootblock-y += OemCustomize.c + romstage-y += ../baseboard/romstage.c +romstage-y += OemCustomize.c ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/liara/OemCustomize.c b/src/mainboard/google/kahlee/variants/liara/OemCustomize.c new file mode 100644 index 0000000..ee225fd --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/OemCustomize.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <compiler.h> +#include <amdblocks/agesawrapper.h> +#include <variant/gpio.h> +#include <boardid.h> + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 1, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + 0, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2( + PortEnabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 2, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_0_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 3, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_1_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2( + PortEnabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 4, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_2_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 5, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_3_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, +}; + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DDI0 - eDP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1) + }, + /* DDI1 - DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DDI2 - DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList +}; + +/*---------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the + * binary block interface (call-out port) to provide a user hook opportunity. + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; + InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow; + InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; + InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; + InitEarly->PlatformConfig.PlatformProfile.NbPstatesSupported = FALSE; +} -- To view, visit https://review.coreboot.org/28726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Gerrit-Change-Number: 28726 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>

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Change in coreboot[rampayload]: WIP: Port libpayload to riscv
by build bot (Jenkins) (Code Review) 24 Sep '18

24 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28606 ) Change subject: WIP: Port libpayload to riscv ...................................................................... Patch Set 7: (42 comments) https://review.coreboot.org/#/c/28606/7/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/28606/7/payloads/external/LinuxBoot/Makefil… PS7, Line 78: echo "BEFOR DEF" 'BEFOR' may be misspelled - perhaps 'BEFORE'? https://review.coreboot.org/#/c/28606/7/payloads/libpayload/arch/riscv/core… File payloads/libpayload/arch/riscv/coreboot.c: https://review.coreboot.org/#/c/28606/7/payloads/libpayload/arch/riscv/core… PS7, Line 43: switch(rec->tag) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/asm.h: https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 14: #define ALIGN .align 2 Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 16: #define ENDPROC(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 17: .type name, %function; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 20: #define ENTRY(name) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 21: .section .text.name, "ax", %progbits; \ need consistent spacing around '%' (ctx:WxV) https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 24: name: labels should not be indented https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 26: #define END(name) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 27: .size name, .-name space required before that '-' (ctx:VxV) https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/barrier.h: https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 57: #define mb() memory barrier without comment https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 58: #define rmb() memory barrier without comment https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 59: #define wmb() memory barrier without comment https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… File payloads/libpayload/include/riscv/arch/cache.h: https://review.coreboot.org/#/c/28606/7/payloads/libpayload/include/riscv/a… PS7, Line 81: } void function return statements are not generally useful https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/linuxcheck.c File payloads/linuxcheck/linuxcheck.c: https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/linuxcheck.c@27 PS7, Line 27: buts("Greetings from linuxcheck, via hard-coded calls to serial functions.\r\n"); line over 80 characters https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/linuxcheck.c@31 PS7, Line 31: buts("Bad news: lib_sysinfo.serial is NULL. Very little will work well.\r\n"); line over 80 characters https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/linuxcheck.c@41 PS7, Line 41: buts("If you did not see puts works, then you have a console issues\r\n"); line over 80 characters https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/linuxcheck.c@44 PS7, Line 44: buts(" ... if you did not see printf works, then you have a printf issue\r\n"); line over 80 characters https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c File payloads/linuxcheck/riscv-fu540.c: https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@25 PS7, Line 25: uint32_t txdata; /* Transmit data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@25 PS7, Line 25: uint32_t txdata; /* Transmit data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@26 PS7, Line 26: uint32_t rxdata; /* Receive data register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@26 PS7, Line 26: uint32_t rxdata; /* Receive data register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@27 PS7, Line 27: uint32_t txctrl; /* Transmit control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@27 PS7, Line 27: uint32_t txctrl; /* Transmit control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@28 PS7, Line 28: uint32_t rxctrl; /* Receive control register */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@28 PS7, Line 28: uint32_t rxctrl; /* Receive control register */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@29 PS7, Line 29: uint32_t ie; /* UART interrupt enable */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@29 PS7, Line 29: uint32_t ie; /* UART interrupt enable */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@30 PS7, Line 30: uint32_t ip; /* UART interrupt pending */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@30 PS7, Line 30: uint32_t ip; /* UART interrupt pending */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@31 PS7, Line 31: uint32_t div; /* Baud rate divisor */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@31 PS7, Line 31: uint32_t div; /* Baud rate divisor */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@36 PS7, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@36 PS7, Line 36: return !(read32(&regs->txdata) & TXDATA_FULL); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@41 PS7, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@41 PS7, Line 41: struct sifive_uart_registers *regs = (void *)(FU540_UART(idx)); please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@43 PS7, Line 43: while (!uart_can_tx(regs)) code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@43 PS7, Line 43: while (!uart_can_tx(regs)) please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@44 PS7, Line 44: ; /* TODO: implement a timeout */ code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@44 PS7, Line 44: ; /* TODO: implement a timeout */ please, no spaces at the start of a line https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@46 PS7, Line 46: write32(&regs->txdata, data); code indent should use tabs where possible https://review.coreboot.org/#/c/28606/7/payloads/linuxcheck/riscv-fu540.c@46 PS7, Line 46: write32(&regs->txdata, data); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: rampayload Gerrit-MessageType: comment Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 28606 Gerrit-PatchSet: 7 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Sep 2018 15:53:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/model_206ax: detect number of MCE banks
by Elyes HAOUAS (Code Review) 24 Sep '18

24 Sep '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28443 ) Change subject: cpu/intel/model_206ax: detect number of MCE banks ...................................................................... Patch Set 2: Code-Review+1 IA32_MCG_CAP is common, so, do you believe that we can use it for other CPUs? if yes, do you think that we can define IA32_MCG_CAP here: "src/cpu/intel/common/"? -- To view, visit https://review.coreboot.org/28443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Gerrit-Change-Number: 28443 Gerrit-PatchSet: 2 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Sep 2018 14:39:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by build bot (Jenkins) (Code Review) 24 Sep '18

24 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 20: (3 comments) https://review.coreboot.org/#/c/27369/20/src/soc/intel/common/basecode/fw_u… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/#/c/27369/20/src/soc/intel/common/basecode/fw_u… PS20, Line 157: printk(BIOS_INFO, "UCODE: Current ucode version: 0x%x\n", current_ucode); line over 80 characters https://review.coreboot.org/#/c/27369/20/src/soc/intel/common/basecode/fw_u… PS20, Line 197: } else { else is not generally useful after a break or return https://review.coreboot.org/#/c/27369/20/src/soc/intel/common/basecode/fw_u… PS20, Line 198: /* Update successfull */ 'successfull' may be misspelled - perhaps 'successful'? -- To view, visit https://review.coreboot.org/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 20 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 24 Sep 2018 13:14:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: commonlib/region: [WIP] Add region protect API
by build bot (Jenkins) (Code Review) 24 Sep '18

24 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28724 ) Change subject: commonlib/region: [WIP] Add region protect API ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28724/1/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/1/src/commonlib/include/commonlib/reg… PS1, Line 96: int (*protect)(const struct region *); function definition argument 'const struct region *' should also have an identifier name -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Sep 2018 13:13:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: [WIP] Implement write protect operation
by Rizwan Qureshi (Code Review) 24 Sep '18

24 Sep '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28725 Change subject: drivers/spi: [WIP] Implement write protect operation ...................................................................... drivers/spi: [WIP] Implement write protect operation Implement a write protect operation which can be used as part of a region_device_ops. This operation will protect the region using the SPI FPR. Change-Id: I87cef73852ea671ec80741af78844d32c0ed5d3c Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/drivers/spi/boot_device_rw_nommap.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/28725/1 diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index 64d81c5..aadaf4e 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -50,6 +50,11 @@ return size; } +static int spi_protect(const struct region *r) +{ + return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r); +} + static ssize_t spi_eraseat(const struct region_device *rd, size_t offset, size_t size) { @@ -68,6 +73,7 @@ .readat = spi_readat, .writeat = spi_writeat, .eraseat = spi_eraseat, + .protect = spi_protect, }; static const struct region_device spi_rw = -- To view, visit https://review.coreboot.org/28725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I87cef73852ea671ec80741af78844d32c0ed5d3c Gerrit-Change-Number: 28725 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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coreboot-gerrit September 2018