coreboot-gerrit September 2018

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Change in coreboot[master]: mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQ
by Duncan Laurie (Code Review) 26 Sep '18

26 Sep '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/28759 Change subject: mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQ ...................................................................... mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQ Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 3 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/28759/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 15a97c3..99b2dcf 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -196,7 +196,7 @@ /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_NC(GPP_D17), + PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ PAD_CFG_NC(GPP_D18), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h index 7e16801..ba481e4 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h @@ -79,4 +79,7 @@ #define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ #define EC_ENABLE_CBAS_DEVICE /* Enable "Base Attached Switch" device */ +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + #endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h index 0853893..fb7ad1a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h @@ -34,6 +34,9 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* EC sync irq is GPP_D12 */ +#define EC_SYNC_IRQ GPP_D17_IRQ + /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI -- To view, visit https://review.coreboot.org/28759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Gerrit-Change-Number: 28759 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/chromeec: Define a sync IRQ if needed
by Duncan Laurie (Code Review) 26 Sep '18

26 Sep '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/28758 Change subject: ec/google/chromeec: Define a sync IRQ if needed ...................................................................... ec/google/chromeec: Define a sync IRQ if needed Some boards are adding a second pin used for synchronization between the EC and AP. This is a direct connection between the EC and the SOC that is intended to provide a lower latency interrupt signal for sensors on the EC. Currently the runtime EC interrupts assert an SCI before eventually resulting in a Notify() on the MKBP device that the sensor driver users. These extra layers add processing time and require additional EC communication to determine the event source. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/chromeec/acpi/cros_ec.asl 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28758/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index d0a5b68..befd5a7 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -22,6 +22,16 @@ Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) #endif +#ifdef EC_ENABLE_SYNC_IRQ + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) + { + EC_SYNC_IRQ + } + }) +#endif + #ifdef EC_ENABLE_MKBP_DEVICE Device (CKSC) { -- To view, visit https://review.coreboot.org/28758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Gerrit-Change-Number: 28758 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: MAINTAINERS: Update RISC-V entry with SiFive and utils
by Jonathan Neuschäfer (Code Review) 26 Sep '18

26 Sep '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28757 Change subject: MAINTAINERS: Update RISC-V entry with SiFive and utils ...................................................................... MAINTAINERS: Update RISC-V entry with SiFive and utils Change-Id: Idd9e51fe2cb7a8497381f5b7440666cd709166b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M MAINTAINERS 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28757/1 diff --git a/MAINTAINERS b/MAINTAINERS index 4d27129..b7031c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -124,8 +124,11 @@ M: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> S: Maintained F: src/arch/riscv/ +F: src/soc/sifive/ F: src/soc/ucb/ F: src/mainboard/emulation/*-riscv/ +F: src/mainboard/sifive/ +F: util/riscv/ POWER8 ARCHITECTURE M: Ronald Minnich <rminnich(a)gmail.com> -- To view, visit https://review.coreboot.org/28757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idd9e51fe2cb7a8497381f5b7440666cd709166b8 Gerrit-Change-Number: 28757 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: soc/intel/cannonlake: Fix ACPI FADT table generation
by Furquan Shaikh (Code Review) 26 Sep '18

26 Sep '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28755 ) Change subject: soc/intel/cannonlake: Fix ACPI FADT table generation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6 Gerrit-Change-Number: 28755 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 26 Sep 2018 18:17:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Fix ACPI FADT table generation
by Duncan Laurie (Code Review) 26 Sep '18

26 Sep '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/28755 Change subject: soc/intel/cannonlake: Fix ACPI FADT table generation ...................................................................... soc/intel/cannonlake: Fix ACPI FADT table generation The function to fill out the FADT table exits early if the devicetree config option to disable the legacy timer is set. This means it never gets to the later check for s0ix config option and so the flag to indicate that it supports low-power idle in S0 is not set. Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 11 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28755/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 155756c..a27055a 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -176,19 +176,18 @@ const struct device *dev = PCH_DEV_LPC; const struct soc_intel_cannonlake_config *config = dev->chip_info; - if (config->PmTimerDisabled != 0) - return; + if (!config->PmTimerDisabled) { + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = 4; + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + } - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - if(config->s0ix_enable) + if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } uint32_t soc_read_sci_irq_select(void) -- To view, visit https://review.coreboot.org/28755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6 Gerrit-Change-Number: 28755 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: google/kahlee: Enable IOMMU device
by Marc Jones (Code Review) 26 Sep '18

26 Sep '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28754 Change subject: google/kahlee: Enable IOMMU device ...................................................................... google/kahlee: Enable IOMMU device Enable the IOMMU device on all kahlee based mainboards. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I18b9ba1a970c6973226e736d72f82fd53010f31c Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb M src/mainboard/google/kahlee/variants/careena/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/liara/devicetree.cb 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28754/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index e33ed2c..61dee6f 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -55,6 +55,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index d633134..d41e76a 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -58,6 +58,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 7da06d8..228ead2 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -58,6 +58,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 636f0c6..a213492 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -55,6 +55,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge -- To view, visit https://review.coreboot.org/28754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I18b9ba1a970c6973226e736d72f82fd53010f31c Gerrit-Change-Number: 28754 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Add IOMMU support
by Marc Jones (Code Review) 26 Sep '18

26 Sep '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28753 Change subject: soc/amd/stoneyridge: Add IOMMU support ...................................................................... soc/amd/stoneyridge: Add IOMMU support Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/iommu.c M src/soc/amd/stoneyridge/northbridge.c 5 files changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28753/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a6ed6d9..3de1e85 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -298,6 +298,7 @@ #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 +#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 5cd04ba..fdde226 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -321,6 +321,9 @@ */ AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct); + LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; + LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + timestamp_add_now(TS_AGESA_INIT_LATE_START); Status = AmdInitLate(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index a8db2c2..c54b652 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -97,6 +97,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c ramstage-y += hda.c +ramstage-y += iommu.c ramstage-y += monotonic_timer.c ramstage-y += southbridge.c ramstage-y += sb_util.c diff --git a/src/soc/amd/stoneyridge/iommu.c b/src/soc/amd/stoneyridge/iommu.c new file mode 100644 index 0000000..8c45457 --- /dev/null +++ b/src/soc/amd/stoneyridge/iommu.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> + +static void iommu_read_resources(struct device *dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, 0x44); + res->size = 512 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void iommu_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations iommu_ops = { + .read_resources = iommu_read_resources, + .set_resources = iommu_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver iommu_driver __pci_driver = { + .ops = &iommu_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, +}; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 912daa0..95c2a07 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -508,7 +508,7 @@ void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) { - params->IommuSupport = FALSE; + params->IommuSupport = TRUE; set_board_env_params(params); } -- To view, visit https://review.coreboot.org/28753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Gerrit-Change-Number: 28753 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: src: Move common IA-32 MSRs to "cpu/x86/msr.h"
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28752 Change subject: src: Move common IA-32 MSRs to "cpu/x86/msr.h" ...................................................................... src: Move common IA-32 MSRs to "cpu/x86/msr.h" Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/common_init.c M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/common.c M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/intel/speedstep/speedstep.c M src/cpu/intel/turbo/turbo.c M src/cpu/via/nano/nano_init.c M src/cpu/via/nano/update_ucode.c M src/cpu/via/nano/update_ucode.h M src/cpu/x86/pae/pgtbl.c M src/cpu/x86/sipi_vector.S M src/include/cpu/intel/l2_cache.h M src/include/cpu/intel/speedstep.h M src/include/cpu/intel/turbo.h M src/include/cpu/x86/msr.h M src/northbridge/intel/nehalem/early_init.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/romstage/cache_as_ram.inc M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/ramstage.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/msr.h M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/common/block/vmx/vmx.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_baytrail/ramstage.c M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/soc/intel/fsp_broadwell_de/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/ramstage.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/msr.h 56 files changed, 127 insertions(+), 260 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/28752/1 diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 8dd8559..02eb0e2 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -20,10 +20,6 @@ #include <cpu/x86/msr.h> #include "common.h" -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) - void set_vmx(void) { struct cpuid_result regs; @@ -105,7 +101,7 @@ config->version = version; - msr.addrl = MSR_IA32_HWP_CAPABILITIES; + msr.addrl = IA32_HWP_CAPABILITIES; /* * Highest Performance: @@ -141,7 +137,7 @@ msr.bit_offset = 8; config->regs[CPPC_GUARANTEED_PERF] = msr; - msr.addrl = MSR_IA32_HWP_REQUEST; + msr.addrl = IA32_HWP_REQUEST; /* * Desired Performance Register: @@ -182,7 +178,7 @@ */ config->regs[CPPC_COUNTER_WRAP] = unsupported; - msr.addrl = MSR_IA32_MPERF; + msr.addrl = IA32_MPERF; /* * Reference Performance Counter Register: @@ -192,7 +188,7 @@ msr.bit_offset = 0; config->regs[CPPC_REF_PERF_COUNTER] = msr; - msr.addrl = MSR_IA32_APERF; + msr.addrl = IA32_APERF; /* * Delivered Performance Counter Register: @@ -200,7 +196,7 @@ */ config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; - msr.addrl = MSR_IA32_HWP_STATUS; + msr.addrl = IA32_HWP_STATUS; /* * Performance Limited Register: @@ -210,7 +206,7 @@ msr.bit_offset = 2; config->regs[CPPC_PERF_LIMITED] = msr; - msr.addrl = MSR_IA32_PM_ENABLE; + msr.addrl = IA32_PM_ENABLE; /* * CPPC Enable Register: diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index e65b370..020b72d 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -20,25 +20,12 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 87daeac..5dfe016 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -21,25 +21,12 @@ /* Rangeley bus clock is fixed at 100MHz */ #define RANGELEY_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8498c1a..4ccb1c1 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -35,25 +35,12 @@ #define HASWELL_BCLK 100 #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 24de43e..9219839 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -649,10 +649,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0d9169b..ce5dac4 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -190,7 +190,7 @@ const u32 sub_cstates = cpuid_edx(5); - msr = rdmsr(IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 3); /* TM1 enable */ if (tm2) msr.lo |= (1 << 13); /* TM2 enable */ @@ -220,11 +220,11 @@ if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) msr.hi &= ~(1 << (38 - 32)); - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); if (eist) { msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index dd7bbc8..6bf21fd 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -56,7 +56,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f87ba77..11d86cd 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,26 +20,13 @@ /* Nehalem bus clock is fixed at 133MHz */ #define NEHALEM_BCLK 133 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 322e814..222c2ed 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -231,10 +231,10 @@ msr_t msr; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c index 9775efb..1e832c8 100644 --- a/src/cpu/intel/model_206ax/common.c +++ b/src/cpu/intel/model_206ax/common.c @@ -19,8 +19,6 @@ #include <cpu/x86/msr.h> #include "model_206ax.h" -#define IA32_PLATFORM_ID 0x17 - int get_platform_id(void) { msr_t msr; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 98203b6..f4d469c 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -20,27 +20,12 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 -#define IA32_MCG_CAP 0x179 - #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 3cc8d82..194114d 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -401,10 +401,10 @@ msr_t msr; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 96830c4..8d68b9e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -58,7 +58,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a1433f6..9dd1223 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -59,7 +59,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 #define IA32_PECI_CTL 0x5a0 static void configure_misc(void) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index cf68ecf..7cc2ce1 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -37,10 +37,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK_BIT (1 << 0) -#define SMRR_ENABLE (1 << 3) - struct ied_header { char signature[10]; u32 size; diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 441f2a3..43d5b5a 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -72,7 +72,7 @@ msr = rdmsr(MSR_FSB_CLOCK_VCC); if ((msr.hi & (1 << (63 - 32))) && /* supported and */ - !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { + !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { /* not disabled */ params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); params->turbo.is_turbo = 1; diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 5583c46..c31f4c0 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -68,7 +68,7 @@ cpuid_regs = cpuid(CPUID_LEAF_PM); turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); if (!turbo_cap && turbo_en) { @@ -97,9 +97,9 @@ /* Only possible if turbo is available but hidden */ if (get_turbo_state() == TURBO_DISABLED) { /* Clear Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi &= ~H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_ENABLED); @@ -115,9 +115,9 @@ msr_t msr; /* Set Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi |= H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_UNAVAILABLE); diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 62c6316..985a3c7 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -28,9 +28,6 @@ #define MODEL_NANO_3000_B0 0x8 #define MODEL_NANO_3000_B2 0xa -#define MSR_IA32_PERF_STATUS 0x00000198 -#define MSR_IA32_PERF_CTL 0x00000199 -#define MSR_IA32_MISC_ENABLE 0x000001a0 #define NANO_MYSTERIOUS_MSR 0x120e static void nano_finish_fid_vid_transition(void) @@ -41,7 +38,7 @@ int cnt = 0; do { udelay(16); - msr = rdmsr(MSR_IA32_PERF_STATUS); + msr = rdmsr(IA32_PERF_STATUS); cnt++; if (cnt > 128) { printk(BIOS_WARNING, @@ -61,7 +58,7 @@ { msr_t msr; /* Get voltage and frequency info */ - msr = rdmsr(MSR_IA32_PERF_STATUS); + msr = rdmsr(IA32_PERF_STATUS); u8 min_fid = (msr.hi >> 24); u8 max_fid = (msr.hi >> 8) & 0xff; u8 min_vid = (msr.hi >> 16) & 0xff; @@ -78,7 +75,7 @@ /* Set highest frequency and VID */ msr.lo = msr.hi; msr.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, msr); + wrmsr(IA32_PERF_CTL, msr); /* Wait for the transition to complete, otherwise, the CPU * might reset itself repeatedly */ nano_finish_fid_vid_transition(); @@ -96,9 +93,9 @@ { msr_t msr; /* Enable Powersaver */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable 6 bit or 7-bit VRM support * This MSR is not documented by VIA docs, other than setting these @@ -116,24 +113,24 @@ nano_set_max_fid_vid(); /* Enable TM3 */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= ( (1 << 3) | (1 << 13) ); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); u8 stepping = ( cpuid_eax(0x1) ) &0xf; if (stepping >= MODEL_NANO_3000_B0) { /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ msr.hi |= (1 << 0); /* C4e */ - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); } /* Lock on Powersaver */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 20); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); } static void nano_init(struct device *dev) diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 7c631a6..b8bfd7d 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -32,7 +32,7 @@ * not the header. The header is just there to help us. */ msr.lo = (unsigned int)(&(ucode->ucode_start)); msr.hi = 0; - wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + wrmsr(IA32_BIOS_UPDT_TRIG, msr); /* Let's see if we updated successfully */ msr = rdmsr(MSR_UCODE_UPDATE_STATUS); diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index ef70d23..acf8fdc 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -18,8 +18,6 @@ #include <cpu/cpu.h> -#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 -#define MSR_IA32_BIOS_SIGN_ID 0x0000008b #define MSR_UCODE_UPDATE_STATUS 0x00001205 #define NANO_UCODE_SIGNATURE 0x53415252 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index cf6bf16..3c1a336 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -184,7 +184,7 @@ msr_t msr; msr.lo = pat; msr.hi = pat >> 32; - wrmsr(MSR_IA32_PAT, msr); + wrmsr(IA32_PAT, msr); } /* PAT encoding used in util/x86/x86_page_tables.go. It matches the linux diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba5ae3e..a7e4522 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -16,6 +16,7 @@ #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> +#include <cpu/x86/msr.h> /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into @@ -25,9 +26,6 @@ #define CODE_SEG 0x10 #define DATA_SEG 0x18 -#define IA32_UPDT_TRIG 0x79 -#define IA32_BIOS_SIGN_ID 0x8b - .section ".module_parameters", "aw", @progbits ap_start_params: gdtaddr: @@ -145,7 +143,7 @@ load_microcode: /* Load new microcode. */ - mov $IA32_UPDT_TRIG, %ecx + mov $IA32_BIOS_UPDT_TRIG, %ecx xor %edx, %edx mov %edi, %eax /* The microcode pointer is passed in pointing to the header. Adjust diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 35059ff..1303148 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -27,7 +27,6 @@ #ifndef __P6_L2_CACHE_H #define __P6_L2_CACHE_H -#define IA32_PLATFORM_ID 0x17 #define EBL_CR_POWERON 0x2A #define BBL_CR_D0 0x88 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 4b556b7..03ba89d 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -35,11 +35,7 @@ /* Speedstep related MSRs */ -#define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STATUS 0x198 -#define IA32_PERF_CTL 0x199 -#define MSR_THERM2_CTL 0x19D -#define IA32_MISC_ENABLES 0x1A0 +#define MSR_THERM2_CTL 0x19D #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 58f4831..0880ebb 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -20,7 +20,6 @@ #define CPUID_LEAF_PM 6 #define PM_CAP_TURBO_MODE (1 << 1) -#define MSR_IA32_MISC_ENABLES 0x1a0 /* Disable the Monitor Mwait FSM feature */ #define MONITOR_MWAIT_DIS_MASK 0x40000 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 290c54a..489182f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -13,14 +13,42 @@ #define EFER_SCE (1 << 0) /* Page attribute type MSR */ -#define MSR_IA32_PAT 0x277 -#define MSR_IA32_MPERF 0xe7 -#define MSR_IA32_APERF 0xe8 -#define MSR_IA32_PM_ENABLE 0x770 -#define MSR_IA32_HWP_CAPABILITIES 0x771 -#define MSR_IA32_HWP_REQUEST 0x774 -#define MSR_IA32_HWP_STATUS 0x777 +#define IA32_PLATFORM_ID 0x17 +#define IA32_FEATURE_CONTROL 0x3a +#define FEATURE_CONTROL_LOCK_BIT (1 << 0) +#define FEATURE_ENABLE_VMX (1 << 2) +#define SMRR_ENABLE (1 << 3) +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define SGX_GLOBAL_ENABLE (1 << 18) +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define IA32_BIOS_UPDT_TRIG 0x79 +#define IA32_BIOS_SIGN_ID 0x8b +#define IA32_MPERF 0xe7 +#define IA32_APERF 0xe8 +#define IA32_MCG_CAP 0x179 +#define IA32_PERF_STATUS 0x198 +#define IA32_PERF_CTL 0x199 +#define IA32_THERM_INTERRUPT 0x19b +#define IA32_MISC_ENABLE 0x1a0 +#define IA32_ENERGY_PERF_BIAS 0x1b0 +#define ENERGY_POLICY_PERFORMANCE 0 +#define ENERGY_POLICY_NORMAL 6 +#define ENERGY_POLICY_POWERSAVE 15 +#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define IA32_PLATFORM_DCA_CAP 0x1f8 +#define IA32_PAT 0x277 +#define IA32_MC0_CTL 0x400 +#define IA32_MC0_STATUS 0x401 +#define IA32_PM_ENABLE 0x770 +#define IA32_HWP_CAPABILITIES 0x771 +#define IA32_HWP_REQUEST 0x774 +#define IA32_HWP_STATUS 0x777 +#define IA32_PQR_ASSOC 0xc8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) +#ifndef __ASSEMBLER__ #if defined(__ROMCC__) typedef __builtin_msr_t msr_t; @@ -95,5 +123,5 @@ #endif /* CONFIG_SOC_SETS_MSRS */ #endif /* __ROMCC__ */ - +#endif #endif /* CPU_X86_MSR_H */ diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 0a9b408..1ebb2a5 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -110,11 +110,11 @@ m.lo = (m.lo & ~0xff) | reg8; wrmsr(IA32_PERF_CTL, m); - m = rdmsr(MSR_IA32_MISC_ENABLES); + m = rdmsr(IA32_MISC_ENABLE); m.hi &= ~0x00000040; m.lo |= 0x10000; - wrmsr(MSR_IA32_MISC_ENABLES, m); + wrmsr(IA32_MISC_ENABLE, m); } m = rdmsr(MSR_FSB_CLOCK_VCC); @@ -124,9 +124,9 @@ m.lo = (m.lo & ~0xff) | reg8; wrmsr(IA32_PERF_CTL, m); - m = rdmsr(MSR_IA32_MISC_ENABLES); + m = rdmsr(IA32_MISC_ENABLE); m.lo |= 0x10000; - wrmsr(MSR_IA32_MISC_ENABLES, m); + wrmsr(IA32_MISC_ENABLE, m); } void nehalem_early_initialization(int chipset_type) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index caa3bbf..928679f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -54,7 +54,7 @@ REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), /* Disable support for MONITOR and MWAIT instructions */ - REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), + REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0), #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 689d4d5..dd60345 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -16,7 +16,6 @@ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -24,8 +23,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 486f5a3..e9925a2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -108,7 +108,7 @@ stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index dcb6296..9969d5d 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -17,6 +17,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/msr.h> #include "fmap_config.h" @@ -35,7 +36,6 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e -#define MCG_CAP_MSR 0x179 /* Save the BIST result. */ movl %eax, %ebp @@ -64,7 +64,7 @@ post_code(0x22) /* Zero the variable MTRRs. */ - movl $MCG_CAP_MSR, %ecx + movl $IA32_MCG_CAP, %ecx rdmsr movzx %al, %ebx /* First variable MTRR. */ diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 66fde22..f9c3014 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -60,9 +60,9 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ @@ -74,7 +74,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 85b04ac..5383fdf 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -175,7 +175,7 @@ msr_t msr_value; /* Need to make sure that all cores have microcode loaded. */ - msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID); + msr_value = rdmsr(IA32_BIOS_SIGN_ID); if (msr_value.hi == 0) intel_microcode_load_unlocked(pattrs->microcode_patch); diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 47e9bcd..ec0cbe3 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -17,8 +17,6 @@ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 -#define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -26,8 +24,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 20c09d5..a12db80 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -112,7 +112,7 @@ stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index b05a007..72dbca5 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -67,14 +67,14 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable Burst Mode */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi = 0; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of @@ -91,7 +91,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* ENV_SMM */ diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index ee1fd52..4c1b3fd 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -546,10 +546,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 41ce17c..c93d292 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,9 +18,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -32,26 +29,16 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRRphysBase_MSR 0x1f4 #define EMRRphysMask_MSR 0x1f5 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_EMRRphysBase_MSR 0x2f4 #define UNCORE_EMRRphysMask_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ba87045..1fdaf69 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -18,6 +18,7 @@ #include <chip.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> @@ -126,10 +127,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); } static void configure_c_states(void) diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 6617d7f..e3bd5f6 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -20,13 +20,6 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f9 #define MSR_VR_MISC_CONFIG2 0x636 #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 684f827..17b8dc0 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -17,6 +17,7 @@ #include <commonlib/helpers.h> #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h> @@ -306,7 +307,7 @@ wrmsr /* Set CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ wrmsr @@ -339,7 +340,7 @@ post_code(0x27) /* Cache is populated. Use mask 1 that will block evicts */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ or $1, %edx /* select mask 1 */ @@ -410,7 +411,7 @@ */ shl %cl, %eax subl $0x02, %eax - movl $MSR_IA32_L3_MASK_1, %ecx + movl $IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -419,12 +420,12 @@ * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $MSR_IA32_L3_MASK_2, %ecx + mov $IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set MSR_IA32_PQR_ASSOC = 0x02 + * Set IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -432,7 +433,7 @@ * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -444,11 +445,11 @@ cld rep stosl /* - * Set MSR_IA32_PQR_ASSOC = 0x01 + * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 86feddc..a4d16e8 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -15,6 +15,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/cr.h> #include <intelblocks/msr.h> @@ -80,7 +81,7 @@ wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr @@ -101,7 +102,7 @@ wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a049..ebbdabd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -95,7 +95,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -115,7 +115,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -135,7 +135,7 @@ perf_ctl.lo = msr.lo & 0xff00; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e1fc431..b7fe904 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,13 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK (1) -#define FEATURE_ENABLE_VMX (1 << 2) -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ @@ -46,16 +39,13 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) -#define IA32_MCG_CAP 0x179 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define MSR_IA32_PERF_CTL 0x199 -#define IA32_MISC_ENABLE 0x1a0 -/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ +/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 @@ -76,8 +66,6 @@ #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 -#define IA32_MC0_CTL 0x400 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) #define MSR_PKG_POWER_SKU_UNIT 0x606 @@ -122,11 +110,8 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -#define MSR_IA32_PQR_ASSOC 0x0c8f -/* MSR bits 33:32 encode slot number 0-3 */ -#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) -#define MSR_IA32_L3_MASK_1 0x0c91 -#define MSR_IA32_L3_MASK_2 0x0c92 +#define IA32_L3_MASK_1 0x0c91 +#define IA32_L3_MASK_2 0x0c92 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index daedcfc..6050dec 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -137,7 +137,7 @@ msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { msr.lo |= SGX_GLOBAL_ENABLE; /* Enable it */ wrmsr(IA32_FEATURE_CONTROL, msr); } diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c index 591ffbc..2cffdab 100644 --- a/src/soc/intel/common/block/vmx/vmx.c +++ b/src/soc/intel/common/block/vmx/vmx.c @@ -58,7 +58,7 @@ msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { /* Enable VMX */ msr.lo |= FEATURE_ENABLE_VMX; wrmsr(IA32_FEATURE_CONTROL, msr); @@ -68,5 +68,5 @@ msr = rdmsr(IA32_FEATURE_CONTROL); printk(BIOS_DEBUG, "VMX status: %s, %s\n", (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled", - (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked"); + (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked"); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b7b5550..676fab7 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -44,9 +44,9 @@ /* Enable speed step. */ if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 4d1ac70..082117c 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -18,12 +18,8 @@ #ifndef _DENVERTON_NS_MSR_H_ #define _DENVERTON_NS_MSR_H_ -#define MSR_PLATFORM_ID 0x17 #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 @@ -35,26 +31,16 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index ea1d790..6a2ce1a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -16,13 +16,10 @@ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index fc50e64..f4cdaa8 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -107,7 +107,7 @@ stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 1e32262..4c91b0a 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -74,7 +74,7 @@ "Bay Trail-D (Desktop)", "Bay Trail-M (Mobile)", }; - msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID); + msr_t platform_id = rdmsr(IA32_PLATFORM_ID); uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK; printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ? diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index 66fde22..f9c3014 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -60,9 +60,9 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ @@ -74,7 +74,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index ffa33da..ed42fdf 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -18,14 +18,9 @@ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce -#define IA32_MCG_CAP 0x179 -#define IA32_PERF_CTL 0x199 #define MSR_TURBO_RATIO_LIMIT 0x1ad -#define IA32_MC0_CTL 0x400 -#define IA32_MC0_STATUS 0x401 #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 #define MSR_CONFIG_TDP_NOMINAL 0x648 diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c index 7165080..7b94268 100644 --- a/src/soc/intel/fsp_broadwell_de/ramstage.c +++ b/src/soc/intel/fsp_broadwell_de/ramstage.c @@ -76,7 +76,7 @@ printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 417c4bc..605dc00 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -353,10 +353,10 @@ return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 780f94f..6da9325 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -24,13 +24,6 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_DELAY_VALUE 0x13 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -- To view, visit https://review.coreboot.org/28752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Gerrit-Change-Number: 28752 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names
by Elyes HAOUAS (Code Review) 26 Sep '18

26 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28751 Change subject: soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names ...................................................................... soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and IA32_MC0_CTL is at 0x400. So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at 0x400 by IA32_MC0_CTL. Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 2 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28751/1 diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index a50c839..a10e504 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -128,11 +128,10 @@ static void configure_mca(void) { msr_t msr; - const unsigned int mcg_cap_msr = 0x179; int i; int num_banks; - msr = rdmsr(mcg_cap_msr); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; /* TODO(adurbin): This should only be done on a cold boot. Also, some @@ -140,14 +139,17 @@ every bank. */ msr.lo = msr.hi = 0; for (i = 0; i < num_banks; i++) { - wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr); - wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr); - wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr); + /* Clear the machine check status */ + wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr); + wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr); } msr.lo = msr.hi = 0xffffffff; - for (i = 0; i < num_banks; i++) - wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr); + for (i = 0; i < num_banks; i++) { + /* Initialize machine checks */ + wrmsr(IA32_MC0_CTL + (i * 4), msr); + } } static void broadwell_de_core_init(struct device *cpu) diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index 6b87061..ffa33da 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -21,9 +21,11 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce +#define IA32_MCG_CAP 0x179 #define IA32_PERF_CTL 0x199 #define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_IA32_MC0_STATUS 0x400 +#define IA32_MC0_CTL 0x400 +#define IA32_MC0_STATUS 0x401 #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 #define MSR_CONFIG_TDP_NOMINAL 0x648 -- To view, visit https://review.coreboot.org/28751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Gerrit-Change-Number: 28751 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/clevo/n130wu: Add mainboard
by build bot (Jenkins) (Code Review) 26 Sep '18

26 Sep '18

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coreboot-gerrit September 2018