coreboot-gerrit September 2018

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Change in coreboot[master]: amd/stoneyridge: Make gnvs ASL whitespace consistent
by Martin Roth (Code Review) 27 Sep '18

27 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28764 ) Change subject: amd/stoneyridge: Make gnvs ASL whitespace consistent ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Gerrit-Change-Number: 28764 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 15:31:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: payloads: Only show supported payloads in menuconfig
by Philipp Hug (Code Review) 27 Sep '18

27 Sep '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/28774 ) Change subject: payloads: Only show supported payloads in menuconfig ...................................................................... Patch Set 1: Please cross-check for riscv. This will only leave ELF and FIT payload. -- To view, visit https://review.coreboot.org/28774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Gerrit-Change-Number: 28774 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Comment-Date: Thu, 27 Sep 2018 15:29:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: payloads: Only show supported payloads in menuconfig
by Philipp Hug (Code Review) 27 Sep '18

27 Sep '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28774 Change subject: payloads: Only show supported payloads in menuconfig ...................................................................... payloads: Only show supported payloads in menuconfig Some payloads don't depend on their supported platforms, which makes them visible in menuconfig even if they are not supported (yet). Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M payloads/Kconfig M payloads/external/FILO/Kconfig.name M payloads/external/linux/Kconfig.name M payloads/external/tianocore/Kconfig.name 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28774/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index 8e05df3..e66a6e4 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -41,6 +41,7 @@ config PAYLOAD_BAYOU bool "Bayou" + depends on ARCH_X86 || ARCH_ARM help Select this option if you want to set bayou as your primary payload. diff --git a/payloads/external/FILO/Kconfig.name b/payloads/external/FILO/Kconfig.name index ca94343..28a41dc 100644 --- a/payloads/external/FILO/Kconfig.name +++ b/payloads/external/FILO/Kconfig.name @@ -1,5 +1,6 @@ config PAYLOAD_FILO bool "FILO" + depends on ARCH_X86 help Select this option if you want to build a coreboot image with a FILO payload. If you don't know what this is diff --git a/payloads/external/linux/Kconfig.name b/payloads/external/linux/Kconfig.name index ae1d906..63621d8 100644 --- a/payloads/external/linux/Kconfig.name +++ b/payloads/external/linux/Kconfig.name @@ -1,5 +1,6 @@ config PAYLOAD_LINUX bool "A Linux payload" + depends on ARCH_X86 || ARCH_ARM help Select this option if you have a Linux bzImage which coreboot should run as soon as the basic hardware initialization diff --git a/payloads/external/tianocore/Kconfig.name b/payloads/external/tianocore/Kconfig.name index e57925f..12c62bf 100644 --- a/payloads/external/tianocore/Kconfig.name +++ b/payloads/external/tianocore/Kconfig.name @@ -1,5 +1,6 @@ config PAYLOAD_TIANOCORE bool "Tianocore coreboot payload package" + depends on ARCH_X86 || ARCH_ARM help Select this option if you want to build a coreboot image with a Tianocore payload. If you don't know what this is -- To view, visit https://review.coreboot.org/28774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Gerrit-Change-Number: 28774 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: amd/stoneyridge: Make gnvs ASL whitespace consistent
by Elyes HAOUAS (Code Review) 27 Sep '18

27 Sep '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28764 ) Change subject: amd/stoneyridge: Make gnvs ASL whitespace consistent ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Gerrit-Change-Number: 28764 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Sep 2018 15:22:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/kahlee: Run FCH PTS and WAK methods
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28773 Change subject: google/kahlee: Run FCH PTS and WAK methods ...................................................................... google/kahlee: Run FCH PTS and WAK methods The FCH ASL is now capable of controlling the D-states of most AOAC devices, as well as properly reinitializing the xHCI firmware on a resume. Call the FPTS and FWAK methods. BUG=b:77602074 TEST=On Grunt, go to S3 and wake with a USB keyboard Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28773/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl index 1e3a617..13c111e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -39,6 +39,8 @@ /* DBGO (Arg0) */ /* DBGO ("\n") */ + \_SB.PCI0.FPTS () + /* Clear wake status structure. */ Store (0, PEWD) Store (0, Index(WKST,0)) @@ -85,5 +87,7 @@ /* DBGO (Arg0) */ /* DBGO (" to S0\n") */ + \_SB.PCI0.FWAK () + Return (WKST) } -- To view, visit https://review.coreboot.org/28773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f Gerrit-Change-Number: 28773 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add USB ASL for D0/D3cold
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28772 Change subject: amd/stoneyridge: Add USB ASL for D0/D3cold ...................................................................... amd/stoneyridge: Add USB ASL for D0/D3cold Add methods, and call them, for transitioning EHCI and xHCI to D0 or D3cold. Add device objects necessary for waking the system via USB. In order for USB to wake the system, it must be in the D3cold state. Then on resume, its firmware must be reloaded. This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI package), and has been modified to fit the coreboot ASL names. In addition, AMD's methodology is to generate a SW SMI for saving/restoring certain settings. This has been ported into U3D0 and U3D3, as the necessary registers are now publicly documented. BUG=b:77602074 Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/usb.asl 2 files changed, 356 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28772/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 59daf49..5ed7c41 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -499,8 +499,8 @@ } } /* todo Case(15) { STD0()} */ /* SATA */ -/* todo Case(18) { U2D0()} */ /* EHCI */ -/* todo Case(23) { U3D0()} */ /* XHCI */ + Case(18) { U2D0()} /* EHCI */ + Case(23) { U3D0()} /* XHCI */ /* todo Case(24) { SDD0()} */ /* SD */ } } else { @@ -555,8 +555,8 @@ Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ -/* todo Case(18) { U2D3()} */ /* EHCI */ -/* todo Case(23) { U3D3()} */ /* XHCI */ + Case(18) { U2D3()} /* EHCI */ + Case(23) { U3D3()} /* XHCI */ /* todo Case(24) { SDD3()} */ /* SD */ } /* Turn off Power */ diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index 6c6ff9c..f2ee8f6 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -17,6 +17,7 @@ /* 0:12.0 - EHCI */ Device(EHC0) { Name(_ADR, 0x00120000) + Name(_PRW, Package() { 0xb, 3 }) Device (RHUB) { Name (_ADR, Zero) Device (HS01) { Name (_ADR, 1) } @@ -28,13 +29,364 @@ Device (HS07) { Name (_ADR, 7) } Device (HS08) { Name (_ADR, 8) } } + + Name(_PR0, Package() { P0U2 }) /* Indicate support for D0 */ + Name(_PR3, Package() { P3U2 }) /* Indicate support for D3cold */ + + Method(_S0W,0) { + Return(0) + } + + Method(_S3W,0) { + Return(4) + } + + Method(_S4W,0) { + Return(4) + } } /* end EHC0 */ /* 0:10.0 - XHCI 0*/ Device(XHC0) { Name(_ADR, 0x00100000) + Name(_PRW, Package() { 0xb, 3 }) Device (SS01) { Name (_ADR, 1) } Device (SS02) { Name (_ADR, 2) } Device (SS03) { Name (_ADR, 3) } + + Name(_PR0, Package() { P0U3 }) /* Indicate support for D0 */ + Name(_PR3, Package() { P3U3 }) /* Indicate support for D3cold */ + + Method(_S0W,0) { + Return(0) + } + + Method(_S3W,0) { + Return(4) + } + + Method(_S4W,0) { + Return(4) + } + } /* end XHC0 */ + +Scope(\_SB) +{ + Name(XHD0, 0) + Name(XHD3, 0) + PowerResource(P0U3, 0, 0) { + Method(_STA) { + Return(XHD0) + } + Method(_ON) { + Store(0x01, XHD0) + } + Method(_OFF) { + Store(0x00, XHD0) + } + } + PowerResource(P3U3, 0, 0) { + Method(_STA) { + Return(XHD3) + } + Method(_ON) { + Store(0x01, XHD3) + } + Method(_OFF) { + Store(0x00, XHD3) + } + } + + Name(EHD0, 0) + Name(EHD3, 0) + PowerResource(P0U2, 0, 0) { + Method(_STA) { + Return(EHD0) + } + Method(_ON) { + Store(0x01, EHD0) + } + Method(_OFF) { + Store(0x00, EHD0) + } + } + PowerResource(P3U2, 0, 0) { + Method(_STA) { + Return(EHD3) + } + Method(_ON) { + Store(0x01, EHD3) + } + Method(_OFF) { + Store(0x00, EHD3) + } + } +} + +OperationRegion(EHMC, SystemMemory, EH10, 0x100) +Field(EHMC, DwordAcc, NoLock, Preserve) +{ + Offset(0xb0), + , 5, + ESIM, 1, +} + +Method(U2D3,0, Serialized) +{ + if (LNotEqual(EH10, Zero)) { + Store (EH10, EHBA) + Store (One, EHME) + Store (ESIM, SSIM) + } + + if (LEqual(E_PS, 3)) { + Store (Zero, RQTY) + Store (One, RQ18) + + Store (U2SR, Local0) + while (Local0) { + Store (U2SR, Local0) + } + + Store (Zero, U2PD) + + Store (U2DS, Local0) + while (LNotEqual(Local0, Zero)) { + Store (U2DS, Local0) + } + + Store (0x03,U2TD) + + if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */ + PWGC (0x40, 0) + Store (One, U2RP) + } + } +} + +Method(U2D0,0, Serialized) +{ + PWGC (0x40, 1) + Store (Zero, U2RP) + Store (0x00,U2TD) + + Store (Zero, U2TD) + Store (One, U2PD) + + Store (U2DS, Local0) + while (LNotEqual(Local0,0x7)) { + Store (U2DS, Local0) + } + + Store (One, RQTY) + Store (One, RQ18) + Store (U2SR, Local0) + while (LNot(Local0)) { + Store (U2SR, Local0) + } + Store (EHID, EH2C) + + + if (LNotEqual(EH10, Zero)) { + Store (EH10, EHBA) + Store (One, EHME) + Store (SSIM, ESIM) + } + + Store (ES54, EH54) + Store (ES64, EH64) +} + +Method(LXFW,3, Serialized) //Load Xhci FirmWare +{ + Store (One, FWLM) /* Firmware Load Mode */ + Store (Arg0, ROAM) /* ROM/RAM */ + Store (Arg1, UA04) + Store (Arg2, UA08) + Store (One, FPLS) /* Firmware Preload Start */ + Store (FPLC, Local0) /* Firmware Preload Complete */ + while (LNot(Local0)) { + Store (FPLC, Local0) + } + Store (Zero, FPLS) +} + +Method(U3D3,0, Serialized) +{ + if (LEqual(U_PS, 3)) { + X0_S () + + Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */ + And (PGA3, 0x20, Local0) + while (LNot(Local0)) { /* wait for it to complete */ + And (PGA3, 0x20, Local0) + } + Store (One, UD3P) /* U3P_D3Cold_PWRDN */ + + Store (Zero, U3PD) /* PwrOnDev */ + Store (U3DS, Local0) + while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */ + Store (U3DS, Local0) + } + + Store (0x3, U3TD) /* TargetedDeviceState */ + + Store (One, U3RP) /* USB3_RefClk_Pwdn */ + + if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */ + And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */ + Store (One, U2RP) /* USB2_RefClk_Pwdn */ + } + Store (Zero, U3PG) /* XhcPwrGood */ + Store (One, U3PS) /* Usb3PowerSel */ + } +} + +Method(U3D0,0, Serialized) +{ + Store (Zero, U3PS) /* Usb3PowerSel */ + Store (One, U3PG) /* XhcPwrGood */ + + Store (Zero, U2RP) + Store (Zero, U3RP) + + And (PGA3, 0xdf, Local0) + Or (Local0, 0x40, Local0) + Store (Local0, PGA3) /* SwUsb2S5RstB */ + + Store (Zero, U3TD) /* TargetedDeviceState */ + Store (One, U3PD) /* PwrOnDev */ + + Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */ + while (LNot(Lequal(Local0, 0x7))) { + Store (U3DS, Local0) + } + + Store (U3PY, Local0) /* USB3 PHY Lock */ + while (LNot(Local0)) { + Store (U3PY, Local0) + } + + Store (Zero, U3PR) /* U3P_RESTORE_RESET */ + + Store (AUSS, Local0) /* AutoSizeStart */ + if (LNotEqual(Local0,1)) { + Store(One, AUSS) + } + Store (AUSS, Local0) + while (LNotEqual(Local0,1)) { + Store (AUSS, Local0) + } + + LXFW (1, FW00, FW01) + LXFW (0, FW02, FW03) + + X0_R () + + Store (One, U3PR) /* U3P_RESTORE_RESET */ + Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */ + Store (One, U3TD) /* TargetedDeviceState */ +} + +Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */ +CreateDWordField(SVBF, 0x000, S000) /* will be easier to add from there */ +CreateDWordField(SVBF, 0x004, S004) +CreateDWordField(SVBF, 0x008, S008) +CreateDWordField(SVBF, 0x00C, S00C) +CreateDWordField(SVBF, 0x018, S018) +CreateDWordField(SVBF, 0x01C, S01C) +CreateDWordField(SVBF, 0x020, S020) +CreateDWordField(SVBF, 0x030, S030) +CreateDWordField(SVBF, 0x118, S118) +CreateDWordField(SVBF, 0x158, S158) +CreateDWordField(SVBF, 0x198, S198) +CreateDWordField(SVBF, 0x1D8, S1D8) +CreateDWordField(SVBF, 0x300, S300) +CreateDWordField(SVBF, 0x304, S304) +CreateDWordField(SVBF, 0x308, S308) +CreateDWordField(SVBF, 0x30C, S30C) +CreateDWordField(SVBF, 0x310, S310) +CreateDWordField(SVBF, 0x428, S428) +CreateDWordField(SVBF, 0x438, S438) +CreateDWordField(SVBF, 0x43C, S43C) +CreateDWordField(SVBF, 0x458, S458) +CreateDWordField(SVBF, 0x468, S468) +CreateDWordField(SVBF, 0x46C, S46C) +CreateDWordField(SVBF, 0x470, S470) +CreateDWordField(SVBF, 0x480, S480) +CreateDWordField(SVBF, 0x484, S484) +CreateDWordField(SVBF, 0x488, S488) +CreateDWordField(SVBF, 0x48C, S48C) +CreateDWordField(SVBF, 0x730, EHID) /* EHCI SSID */ +CreateDWordField(SVBF, 0x734, XHID) /* XHCI SSID */ +CreateByteField(SVBF, 0x740, ES54) /* EHCI PCIx54 */ +CreateByteField(SVBF, 0x741, ES64) /* EHCI PCIx64 */ +CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */ + +Method(X0_S,0) +{ + Store (XH2C, XHID) + Store (0x00000000, IDEX) Store (DATA, S000) + Store (0x00000004, IDEX) Store (DATA, S004) + Store (0x00000008, IDEX) Store (DATA, S008) + Store (0x0000000c, IDEX) Store (DATA, S00C) + Store (0x00000018, IDEX) Store (DATA, S018) + Store (0x0000001c, IDEX) Store (DATA, S01C) + Store (0x00000020, IDEX) Store (DATA, S020) + Store (0x00000030, IDEX) Store (DATA, S030) + Store (0x00000118, IDEX) Store (DATA, S118) + Store (0x00000158, IDEX) Store (DATA, S158) + Store (0x00000198, IDEX) Store (DATA, S198) + Store (0x000001d8, IDEX) Store (DATA, S1D8) + Store (0x00000300, IDEX) Store (DATA, S300) + Store (0x00000304, IDEX) Store (DATA, S304) + Store (0x00000308, IDEX) Store (DATA, S308) + Store (0x0000030c, IDEX) Store (DATA, S30C) + Store (0x00000310, IDEX) Store (DATA, S310) + Store (0x40000028, IDEX) Store (DATA, S428) + Store (0x40000038, IDEX) Store (DATA, S438) + Store (0x4000003c, IDEX) Store (DATA, S43C) + Store (0x40000058, IDEX) Store (DATA, S458) + Store (0x40000068, IDEX) Store (DATA, S468) + Store (0x4000006c, IDEX) Store (DATA, S46C) + Store (0x40000070, IDEX) Store (DATA, S470) + Store (0x40000080, IDEX) Store (DATA, S480) + Store (0x40000084, IDEX) Store (DATA, S484) + Store (0x40000088, IDEX) Store (DATA, S488) + Store (0x4000008c, IDEX) Store (DATA, S48C) +} + +Method(X0_R,0) +{ + Store (XHID, XH2C) + Store (0x00000000, IDEX) Store (S000, DATA) + Store (0x00000004, IDEX) Store (S004, DATA) + Store (0x00000008, IDEX) Store (S008, DATA) + Store (0x0000000c, IDEX) Store (S00C, DATA) + Store (0x00000018, IDEX) Store (S018, DATA) + Store (0x0000001c, IDEX) Store (S01C, DATA) + Store (0x00000020, IDEX) Store (S020, DATA) + Store (0x00000030, IDEX) Store (S030, DATA) + Store (0x00000118, IDEX) Store (S118, DATA) + Store (0x00000158, IDEX) Store (S158, DATA) + Store (0x00000198, IDEX) Store (S198, DATA) + Store (0x000001d8, IDEX) Store (S1D8, DATA) + Store (0x00000300, IDEX) Store (S300, DATA) + Store (0x00000304, IDEX) Store (S304, DATA) + Store (0x00000308, IDEX) Store (S308, DATA) + Store (0x0000030c, IDEX) Store (S30C, DATA) + Store (0x00000310, IDEX) Store (S310, DATA) + Store (0x40000028, IDEX) Store (S428, DATA) + Store (0x40000038, IDEX) Store (S438, DATA) + Store (0x4000003c, IDEX) Store (S43C, DATA) + Store (0x40000058, IDEX) Store (S458, DATA) + Store (0x40000068, IDEX) Store (S468, DATA) + Store (0x4000006c, IDEX) Store (S46C, DATA) + Store (0x40000070, IDEX) Store (S470, DATA) + Store (0x40000080, IDEX) Store (S480, DATA) + Store (0x40000084, IDEX) Store (S484, DATA) + Store (0x40000088, IDEX) Store (S488, DATA) + Store (0x4000008c, IDEX) Store (S48C, DATA) +} -- To view, visit https://review.coreboot.org/28772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb Gerrit-Change-Number: 28772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28771 Change subject: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control ...................................................................... amd/stoneyridge: Add ASL helper for AOAC PwrGood Control Add a method to assist with setting the PwrGood Control register, which will be useful for various devices. BUG=b:77602074 Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28771/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index b8956b4..59daf49 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -639,3 +639,28 @@ } } } + +/* + * Helper for setting a bit in AOACxA0 PwrGood Control + * Arg0 bit location + * Arg1 clear or set if Arg0 5, setting exceptions + */ +Method(PWGC,2, Serialized) +{ + And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */ + if(Arg1) { + Or(Arg0, Local0, Local0) + } else { + Not(Arg0, Local1) + And(Local1, Local0, Local0) + } + Store(Local0, PGA3) + if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */ + Store(PGA3, Local0) + And(Arg0, Local0, Local0) + while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */ + Store(PGA3, Local0) + And(Arg0, Local0, Local0) + } + } +} -- To view, visit https://review.coreboot.org/28771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Gerrit-Change-Number: 28771 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add FCH WAK and PTS methods
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28770 Change subject: amd/stoneyridge: Add FCH WAK and PTS methods ...................................................................... amd/stoneyridge: Add FCH WAK and PTS methods Add methods that can be used for preparing all controller hub devices for sleep, and that will turn the devices back on. BUG=b:77602074 Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28770/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 2271d67..b8956b4 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -581,3 +581,61 @@ } Release(FDAS) } + +Method(FPTS,0, Serialized) /* FCH _PTS */ +{ + if(LEqual(\XHCE, one)) { + if(LNotEqual(U3TD, 0x03)) { + FDDC(23, 3) + } + } + if(LNotEqual(U2TD, 0x03)) { + FDDC(18, 3) + } + + if(LNotEqual(SATD, 0x00)) { + FDDC(15, 0) /* wake SATA before sleep */ + } +} + +Method(FWAK,0, Serialized) /* FCH _WAK */ +{ + if(LEqual(\XHCE, one)) { + if(LEqual(U3TD, 0x03)) { + FDDC(23, 0) + } + } + if(LEqual(U2TD, 0x03)) { + FDDC(18, 0) + } + if(LEqual(\UT0E, zero)) { + if(LNotEqual(U0TD, 0x03)) { + FDDC(11, 3) + } + } + if(LEqual(\UT1E, zero)) { + if(LNotEqual(U1TD, 0x03)) { + FDDC(12, 3) + } + } + if(LEqual(\IC0E, zero)) { + if(LNotEqual(I0TD, 0x03)) { + FDDC(5, 3) + } + } + if(LEqual(\IC1E, zero)) { + if(LNotEqual(I1TD, 0x03)) { + FDDC(6, 3) + } + } + if(LEqual(\IC2E, zero)) { + if(LNotEqual(I2TD, 0x03)) { + FDDC(7, 3) + } + } + if(LEqual(\IC3E, zero)) { + if(LNotEqual(I3TD, 0x03)) { + FDDC(8, 3) + } + } +} -- To view, visit https://review.coreboot.org/28770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda Gerrit-Change-Number: 28770 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28768 Change subject: amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL ...................................................................... amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define various PCI config space registers. These are duplicated from AMD's FchCarrizo.asl file. BUG=b:77602074 Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28768/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index cdda503..923c90f 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -185,3 +185,245 @@ } Return(OSVR) } + +OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) +Field( SMIC, ByteAcc, NoLock, Preserve) { + offset (0x03ee), + U3PS, 2, /* Usb3PowerSel */ + + offset (0x0e28), + ,29 , + SARP, 1, /* Sata Ref Clock Powerdown */ + U2RP, 1, /* Usb2 Ref Clock Powerdown */ + U3RP, 1, /* Usb3 Ref Clock Powerdown */ + + offset (0x1c00), + , 1, + ,6, + U3PY, 1, + , 7, + UD3P, 1, /* bit 15 */ + U3PR, 1, /* bit 16 */ + , 11, + FWLM, 1, /* FirmWare Load Mode */ + FPLS, 1, /* Fw PreLoad Start */ + FPLC, 1, /* Fw PreLoad Complete */ + + offset (0x1c04), + UA04, 16, + , 15, + ROAM, 1, /* 1= ROM 0=RAM */ + + offset (0x1c08), + UA08, 32, + + offset (0x1e4a), + I0TD, 2, + , 1, + I0PD, 1, + offset (0x1e4b), + I0DS, 3, + + offset (0x1e4c), + I1TD, 2, + , 1, + I1PD, 1, + offset (0x1e4d), + I1DS, 3, + + offset (0x1e4e), + I2TD, 2, + , 1, + I2PD, 1, + offset (0x1e4f), + I2DS, 3, + + offset (0x1e50), + I3TD, 2, + , 1, + I3PD, 1, + offset (0x1e51), + I3DS, 3, + + offset (0x1e56), + U0TD, 2, + , 1, + U0PD, 1, + offset (0x1e57), + U0DS, 3, + + offset (0x1e58), + U1TD, 2, + , 1, + U1PD, 1, + offset (0x1e59), + U1DS, 3, + + offset (0x1e5e), + SATD, 2, + , 1, + SAPD, 1, + offset (0x1e5f), + SADS, 3, + + offset (0x1e64), + U2TD, 2, + , 1, + U2PD, 1, + offset (0x1e65), + U2DS, 3, + + offset (0x1e6e), + U3TD, 2, + , 1, + U3PD, 1, + offset (0x1e6f), + U3DS, 3, + + offset (0x1e70), + SDTD, 2, + , 1, + , 1, + , 2, + SDRT, 1, + SDSC, 1, + + offset (0x1e71), + SDDS, 3, + + offset (0x1e80), + , 15, + RQ15, 1, + , 2, + RQ18, 1, + , 4, + RQ23, 1, + RQ24, 1, + , 5, + RQTY, 1, + offset (0x1e84), + , 15, + SASR, 1, /* SATA 15 Shadow Reg Request Status Register */ + , 2, + U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */ + , 4, + U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */ + SDSR, 1, /* SD 24 Shadow Reg Request Status Register */ + offset (0x1e88), + SRSA, 32, /* Shadow Reg SRAM Addr */ + SRSD, 32, /* Shadow Reg SRAM DATA */ + + offset (0x1e94), + SRDY, 1, /* S0i3 bios ready */ + + offset (0x1ea0), + PG1A, 1, + PG2_, 1, + ,1, + U3PG, 1, /* Usb3 Power Good BIT3 */ + + offset (0x1ea3), /* Power Good Control */ + PGA3, 8 , +} + +OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000) +Field(FCFG, DwordAcc, NoLock, Preserve) +{ + /* XHCI */ + Offset(0x00080010), + XHBA, 32, + Offset(0x0008002c), + XH2C, 32, + + Offset(0x00080048), + IDEX, 32, + DATA, 32, + Offset(0x00080054), + U_PS, 2, + + /* SATA */ + Offset(0x00088010), + ST10, 32, + ST14, 32, + ST18, 32, + ST1C, 32, + ST20, 32, + ST24, 32, + + Offset(0x0008802c), + ST2C, 32, + + Offset(0x00088040), + ST40, 1, + + Offset(0x00088044), + ST44, 1, + + Offset(0x0008804c), + , 2, + DDIC, 1, /* DisableDynamicInterfaceClockPowerSaving */ + + Offset(0x00088064), + S_PS, 2, + + Offset(0x00088084), + , 1, + ST84, 1, + , 28, + DSDN, 1, /* DShutDowN */ + + Offset(0x0008808c), + ST8C, 8, + + /* EHCI */ + Offset(0x00090004), + , 1, + EHME, 1, + Offset(0x00090010), + EHBA, 32, + Offset(0x0009002c), + EH2C, 32, + Offset(0x00090054), + EH54, 8, + Offset(0x00090064), + EH64, 8, + + Offset(0x000900c4), + E_PS, 2, + + /* LPC Bridge */ + Offset(0x000a3078), + , 2, + LDQ0, 1, + + Offset(0x000a30cb), + , 7, + AUSS, 1, /* AutoSizeStart */ + + /* SD */ + Offset(0x000a7004), + , 1, + SDME, 1, + + Offset(0x000a7010), + SDBA, 32, + Offset(0x000a702c), + SD2C, 32, + Offset(0x000a7094), + D_PS, 2, + , 6, + SDPE, 1, + , 6, + PMES, 1, + + Offset(0x000a70b3), /* Version 2.0 = 0x1, Version 3.0 = 0x2 */ + SDB3, 8, + Offset(0x000a70b4), /* Set Enable */ + , 8, + SETE, 1, + + Offset(0x000a70d0), + , 17, + FC18, 1, /* Force 1.8v */ + +} -- To view, visit https://review.coreboot.org/28768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Gerrit-Change-Number: 28768 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add ASL for D-states on AOAC devices
by Marshall Dawson (Code Review) 27 Sep '18

27 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28769 Change subject: amd/stoneyridge: Add ASL for D-states on AOAC devices ...................................................................... amd/stoneyridge: Add ASL for D-states on AOAC devices Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package) that can put AOAC devices into D0 or D3cold. The argument numbers coincide with the AOAC register offsets for the various devices. SATA, USB, and SD require additional device configuration. Add a placeholder and mark as todo. BUG=b:77602074 Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 154 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28769/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 923c90f..2271d67 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -427,3 +427,157 @@ FC18, 1, /* Force 1.8v */ } + +/* + * Arg0:device: + * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1, + * 15=SATA, 18=EHCI, 23=xHCI, 24=SD + * Arg1:D-state + */ +Mutex (FDAS, 0) /* FCH Device AOAC Semophore */ +Method(FDDC, 2, Serialized) +{ + Acquire(FDAS, 0xffff) + + if(LEqual(Arg1, 0)) { + Switch(ToInteger(Arg0)) { + Case(Package() {5, 15, 24}) { + Store(One, PG1A) + } + Case(Package() {6, 7, 8, 11, 12, 18}) { + Store(One, PG2_) + } + } + /* put device into D0 */ + Switch(ToInteger(Arg0)) + { + Case(5) { + Store(0x00, I0TD) + Store(One, I0PD) + Store(I0DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I0DS, Local0) + } + } + Case(6) { + Store(0x00, I1TD) + Store(One, I1PD) + Store(I1DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I1DS, Local0) + } + } + Case(7) { + Store(0x00, I2TD) + Store(One, I2PD) + Store(I2DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I2DS, Local0) + } + } + Case(8) {Store(0x00, I3TD) + Store(One, I3PD) + Store(I3DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I3DS, Local0) + } + } + Case(11) { + Store(0x00, U0TD) + Store(One, U0PD) + Store(U0DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(U0DS, Local0) + } + } + Case(12) { + Store(0x00, U1TD) + Store(One, U1PD) + Store(U1DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(U1DS, Local0) + } + } +/* todo Case(15) { STD0()} */ /* SATA */ +/* todo Case(18) { U2D0()} */ /* EHCI */ +/* todo Case(23) { U3D0()} */ /* XHCI */ +/* todo Case(24) { SDD0()} */ /* SD */ + } + } else { + /* put device into D3cold */ + Switch(ToInteger(Arg0)) + { + Case(5) { + Store(Zero, I0PD) + Store(I0DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I0DS, Local0) + } + Store(0x03, I0TD) + } + Case(6) { + Store(Zero, I1PD) + Store(I1DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I1DS, Local0) + } + Store(0x03, I1TD) + } + Case(7) { + Store(Zero, I2PD) + Store(I2DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I2DS, Local0) + } + Store(0x03, I2TD)} + Case(8) { + Store(Zero, I3PD) + Store(I3DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I3DS, Local0) + } + Store(0x03, I3TD) + } + Case(11) { + Store(Zero, U0PD) + Store(U0DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(U0DS, Local0) + } + Store(0x03, U0TD) + } + Case(12) { + Store(Zero, U1PD) + Store(U1DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(U1DS, Local0) + } + Store(0x03, U1TD) + } +/* todo Case(15) { STD3()} */ /* SATA */ +/* todo Case(18) { U2D3()} */ /* EHCI */ +/* todo Case(23) { U3D3()} */ /* XHCI */ +/* todo Case(24) { SDD3()} */ /* SD */ + } + /* Turn off Power */ + if(LEqual(I0TD, 3)) { + if(LEqual(SATD, 3)) { + if(LEqual(SDTD, 3)) { Store(Zero, PG1A) } + } + } + if(LEqual(I1TD, 3)) { + if(LEqual(I2TD, 3)) { + if(LEqual(I3TD, 3)) { + if(LEqual(U0TD, 3)) { + if(LEqual(U1TD, 3)) { + if(LEqual(U2TD, 3)) { + Store(Zero, PG2_) + } + } + } + } + } + } + } + Release(FDAS) +} -- To view, visit https://review.coreboot.org/28769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Gerrit-Change-Number: 28769 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit September 2018